[llvm] [DAG] Apply Disjoint flag. (PR #118045)

[via llvm-commits]

https://github.com/fengfeng09 updated https://github.com/llvm/llvm-project/pull/118045

>From 6f794b3cf0c64719db669cdfa647e841eb273eeb Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Mon, 2 Dec 2024 16:07:33 +0800
Subject: [PATCH 1/2] [DAG] Precommit test case for or disjoint flag.

---
 .../AArch64/apply-disjoint-flag-in-dagcombine.ll  | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll

diff --git a/llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll b/llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll
new file mode 100644
index 00000000000000..49fba906d0a938
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s  -start-before=aarch64-isel -o - | FileCheck %s
+
+define i32 @test(i32 %a) {
+; CHECK-LABEL: test:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add w8, w0, #1
+; CHECK-NEXT:    orr w0, w8, #0xc0
+; CHECK-NEXT:    ret
+entry:
+  %add = add i32 %a, 1
+  %or1 = or disjoint i32 %add, 64
+  %or = or disjoint i32 %or1, 128
+  ret i32 %or
+}

>From 7b3f0d1a0cb495f194318118f1ac713483db0964 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 29 Nov 2024 11:17:54 +0800
Subject: [PATCH 2/2] [DAG] Apply Disjoint flag.

or disjoint (or disjoint (x, c0), c1)
-->
or disjont x, or (c0, c1)
Alive2: https://alive2.llvm.org/ce/z/3wPth5

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp                | 5 ++++-
 .../CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll     | 3 +--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6c8e9969784c92..6435a2119077f5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1220,8 +1220,11 @@ SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
 
     if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
       // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
-      if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, {N01, N1}))
+      if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, {N01, N1})) {
+        NewFlags.setDisjoint(Flags.hasDisjoint() &&
+                             N0->getFlags().hasDisjoint());
         return DAG.getNode(Opc, DL, VT, N00, OpNode, NewFlags);
+      }
       return SDValue();
     }
     if (TLI.isReassocProfitable(DAG, N0, N1)) {
diff --git a/llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll b/llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll
index 49fba906d0a938..75b6ddf86fd77a 100644
--- a/llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll
+++ b/llvm/test/CodeGen/AArch64/apply-disjoint-flag-in-dagcombine.ll
@@ -4,8 +4,7 @@
 define i32 @test(i32 %a) {
 ; CHECK-LABEL: test:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    add w8, w0, #1
-; CHECK-NEXT:    orr w0, w8, #0xc0
+; CHECK-NEXT:    add w0, w0, #193
 ; CHECK-NEXT:    ret
 entry:
   %add = add i32 %a, 1