[compiler-rt] [llvm] [X86][compiler-rt] Split CPU names even they have the same subtype (PR #118237)
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 1 21:28:42 PST 2024
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/118237
>From 6a852d907426d0ae9ca49174e3d99c3437b3aae7 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe" <phoebe.wang at intel.com>
Date: Mon, 2 Dec 2024 08:56:23 +0800
Subject: [PATCH 1/2] [X86][compiler-rt] Split CPU names even they have the
same subtype
Fixes: #118205
---
compiler-rt/lib/builtins/cpu_model/x86.c | 29 ++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index 3315dceb7f5622..f9b95d2faf06ae 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -461,16 +461,31 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family,
// Alderlake:
case 0x97:
case 0x9a:
+ CPU = "alderlake";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ALDERLAKE;
+ break;
+
// Raptorlake:
case 0xb7:
case 0xba:
case 0xbf:
+ CPU = "raptorlake";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ALDERLAKE;
+ break;
+
// Meteorlake:
case 0xaa:
case 0xac:
+ CPU = "meteorlake";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ALDERLAKE;
+ break;
+
// Gracemont:
case 0xbe:
- CPU = "alderlake";
+ CPU = "gracement";
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_ALDERLAKE;
break;
@@ -486,9 +501,14 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family,
// Arrowlake S:
case 0xc6:
+ CPU = "arrowlake-s";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ARROWLAKE_S;
+ break;
+
// Lunarlake:
case 0xbd:
- CPU = "arrowlake-s";
+ CPU = "lunarlake";
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_ARROWLAKE_S;
break;
@@ -510,6 +530,11 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family,
// Emerald Rapids:
case 0xcf:
+ CPU = "emeraldrapids";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_SAPPHIRERAPIDS;
+ break;
+
// Sapphire Rapids:
case 0x8f:
CPU = "sapphirerapids";
>From 805fb38e182231699d654fc6a99684473566e109 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe" <phoebe.wang at intel.com>
Date: Mon, 2 Dec 2024 13:28:27 +0800
Subject: [PATCH 2/2] Add changes in Host.cpp
---
llvm/lib/TargetParser/Host.cpp | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 6e06de323fadad..60e73e6ea64116 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -808,16 +808,31 @@ static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
// Alderlake:
case 0x97:
case 0x9a:
+ CPU = "alderlake";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ALDERLAKE;
+ break;
+
// Gracemont
case 0xbe:
+ CPU = "gracement";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ALDERLAKE;
+ break;
+
// Raptorlake:
case 0xb7:
case 0xba:
case 0xbf:
+ CPU = "raptorlake";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ALDERLAKE;
+ break;
+
// Meteorlake:
case 0xaa:
case 0xac:
- CPU = "alderlake";
+ CPU = "meteorlake";
*Type = X86::INTEL_COREI7;
*Subtype = X86::INTEL_COREI7_ALDERLAKE;
break;
@@ -833,9 +848,14 @@ static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
// Arrowlake S:
case 0xc6:
+ CPU = "arrowlake-s";
+ *Type = X86::INTEL_COREI7;
+ *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
+ break;
+
// Lunarlake:
case 0xbd:
- CPU = "arrowlake-s";
+ CPU = "lunarlake";
*Type = X86::INTEL_COREI7;
*Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
break;
@@ -871,6 +891,11 @@ static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
// Emerald Rapids:
case 0xcf:
+ CPU = "emeraldrapids";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_SAPPHIRERAPIDS;
+ break;
+
// Sapphire Rapids:
case 0x8f:
CPU = "sapphirerapids";
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