[llvm] [NFCI][test] Use lit.local.cfg in test/MachineVerifier/RISCV to gate tests (PR #118217)

[Alex Bradbury via llvm-commits]

https://github.com/asb created https://github.com/llvm/llvm-project/pull/118217

87cc4b48c08a627f330396f941b84671c5e591d5 added `REQUIRES: riscv64-registered-target` to the only test in this directory. It seems better (and also reflects what we do elsewhere, including in the AMDGPU/ subdir in MachineVerifier) to gate for all files in the directory via lit.local.cfg.

---
I'd normally directly commit such a simple change, but just wanted to make sure there wasn't a reason to prefer it the way it was done before.

>From f31cdb1baaa3374e45cc57014b1dcdcb18af9e03 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Sun, 1 Dec 2024 15:40:43 +0000
Subject: [PATCH] [NFCI][test] Use lit.local.cfg in test/MachineVerifier/RISCV
 to gate tests

87cc4b48c08a627f330396f941b84671c5e591d5 added `REQUIRES:
riscv64-registered-target` to the only test in this directory. It seems
better (and also reflects what we do elsewhere, including in the AMDGPU/
subdir in MachineVerifier) to gate for all files in the directory via
lit.local.cfg.
---
 llvm/test/MachineVerifier/RISCV/lit.local.cfg       | 2 ++
 llvm/test/MachineVerifier/RISCV/subreg-liveness.mir | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MachineVerifier/RISCV/lit.local.cfg

diff --git a/llvm/test/MachineVerifier/RISCV/lit.local.cfg b/llvm/test/MachineVerifier/RISCV/lit.local.cfg
new file mode 100644
index 00000000000000..17351748513d98
--- /dev/null
+++ b/llvm/test/MachineVerifier/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "RISCV" in config.root.targets:
+    config.unsupported = True
diff --git a/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir b/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
index c69bc1b5eca649..cb73f500ddc218 100644
--- a/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
+++ b/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
@@ -1,6 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s
-# REQUIRES: riscv64-registered-target
 
 # During the MachineVerifier, it assumes that used registers have been defined
 # In this test case, while $v12_v13_v14_v15_v16 covers $v14_v15,