[compiler-rt] [llvm] [win/asan] Support instructions in GetInstructionSize used by Wine. (PR #113085)
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Sun Dec 1 06:36:02 PST 2024
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>,
Bernhard =?utf-8?q?Übelacker?= <bernhardu at mailbox.org>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/113085 at github.com>
https://github.com/bernhardu updated https://github.com/llvm/llvm-project/pull/113085
>From d050de6f3a3a59521ace62fb475dad788a2b7a59 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sun, 24 Nov 2024 14:44:28 +0100
Subject: [PATCH 01/20] TEMP: .gitignore: Exclude build directories.
---
.gitignore | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/.gitignore b/.gitignore
index 0e7c6c79001338..2486241f7da09b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -71,3 +71,7 @@ pythonenv*
/clang/utils/analyzer/projects/*/RefScanBuildResults
# automodapi puts generated documentation files here.
/lldb/docs/python_api/
+
+/compiler-rt/build*
+/openmp/build*
+/runtimes/build*
>From 65df3c2fbb75bd6a744bc9745b016e6bde575de3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sun, 24 Nov 2024 14:47:24 +0100
Subject: [PATCH 02/20] TEMP: Allow to run test at i686.
At least in Wine.
---
compiler-rt/lib/interception/tests/interception_win_test.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index cfa1b592f1e466..f46153ad8c1ccd 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -332,6 +332,7 @@ int InterceptorFunction(int x);
u8 *AllocateCode2GBAway(u8 *Base) {
// Find a 64K aligned location after Base plus 2GB.
size_t TwoGB = 0x80000000;
+ TwoGB = sizeof(void*) == 4 ? 0x20000000 : TwoGB; // lower requirement with i686
size_t AllocGranularity = 0x10000;
Base = (u8 *)((((uptr)Base + TwoGB + AllocGranularity)) & ~(AllocGranularity - 1));
>From ca6593f9ceebf49893cad4d24de1959a75f3ce88 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sun, 24 Nov 2024 14:49:27 +0100
Subject: [PATCH 03/20] TEMP: Add debugging output.
---
.../tests/interception_win_test.cpp | 27 ++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index f46153ad8c1ccd..600eb3779775f4 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -410,8 +410,18 @@ int InterceptorFunction(int x) {
} // namespace
+struct DebugOutputPrinter {
+ static void Report(const char *format, ...) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stdout, format, args);
+ va_end(args);
+ }
+};
+
// Tests for interception_win.h
TEST(Interception, InternalGetProcAddress) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
HMODULE ntdll_handle = ::GetModuleHandle("ntdll");
ASSERT_NE(nullptr, ntdll_handle);
uptr DbgPrint_expected = (uptr)::GetProcAddress(ntdll_handle, "DbgPrint");
@@ -471,6 +481,7 @@ static void TestIdentityFunctionPatching(
# if !SANITIZER_WINDOWS64
TEST(Interception, OverrideFunctionWithDetour) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithDetour;
FunctionPrefixKind prefix = FunctionPrefixDetour;
TestIdentityFunctionPatching(kIdentityCodeWithPrologue, override, prefix);
@@ -481,6 +492,7 @@ TEST(Interception, OverrideFunctionWithDetour) {
#endif // !SANITIZER_WINDOWS64
TEST(Interception, OverrideFunctionWithRedirectJump) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithRedirectJump;
TestIdentityFunctionPatching(kIdentityCodeWithJump, override);
TestIdentityFunctionPatching(kIdentityCodeWithJumpBackwards, override,
@@ -489,12 +501,14 @@ TEST(Interception, OverrideFunctionWithRedirectJump) {
}
TEST(Interception, OverrideFunctionWithHotPatch) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithHotPatch;
FunctionPrefixKind prefix = FunctionPrefixHotPatch;
TestIdentityFunctionPatching(kIdentityCodeWithMov, override, prefix);
}
TEST(Interception, OverrideFunctionWithTrampoline) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithTrampoline;
FunctionPrefixKind prefix = FunctionPrefixNone;
TestIdentityFunctionPatching(kIdentityCodeWithPrologue, override, prefix);
@@ -506,6 +520,7 @@ TEST(Interception, OverrideFunctionWithTrampoline) {
}
TEST(Interception, OverrideFunction) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunction;
FunctionPrefixKind prefix = FunctionPrefixNone;
TestIdentityFunctionPatching(kIdentityCodeWithPrologue, override, prefix);
@@ -557,6 +572,7 @@ static void TestIdentityFunctionMultiplePatching(
}
TEST(Interception, OverrideFunctionMultiplePatchingIsFailing) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
#if !SANITIZER_WINDOWS64
TestIdentityFunctionMultiplePatching(kIdentityCodeWithPrologue,
OverrideFunctionWithDetour,
@@ -573,6 +589,7 @@ TEST(Interception, OverrideFunctionMultiplePatchingIsFailing) {
}
TEST(Interception, OverrideFunctionTwice) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
uptr identity_address1;
LoadActiveCode(kIdentityTwice, &identity_address1);
uptr identity_address2 = identity_address1 + kIdentityTwiceOffset;
@@ -615,6 +632,7 @@ static bool TestFunctionPatching(
}
TEST(Interception, PatchableFunction) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunction;
// Test without function padding.
EXPECT_TRUE(TestFunctionPatching(kPatchableCode1, override));
@@ -640,6 +658,7 @@ TEST(Interception, PatchableFunction) {
#if !SANITIZER_WINDOWS64
TEST(Interception, PatchableFunctionWithDetour) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithDetour;
// Without the prefix, no function can be detoured.
EXPECT_FALSE(TestFunctionPatching(kPatchableCode1, override));
@@ -669,6 +688,7 @@ TEST(Interception, PatchableFunctionWithDetour) {
#endif // !SANITIZER_WINDOWS64
TEST(Interception, PatchableFunctionWithRedirectJump) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithRedirectJump;
EXPECT_FALSE(TestFunctionPatching(kPatchableCode1, override));
EXPECT_FALSE(TestFunctionPatching(kPatchableCode2, override));
@@ -683,6 +703,7 @@ TEST(Interception, PatchableFunctionWithRedirectJump) {
}
TEST(Interception, PatchableFunctionWithHotPatch) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithHotPatch;
FunctionPrefixKind prefix = FunctionPrefixHotPatch;
@@ -704,6 +725,7 @@ TEST(Interception, PatchableFunctionWithHotPatch) {
}
TEST(Interception, PatchableFunctionWithTrampoline) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithTrampoline;
FunctionPrefixKind prefix = FunctionPrefixPadding;
@@ -734,6 +756,7 @@ TEST(Interception, PatchableFunctionWithTrampoline) {
}
TEST(Interception, UnsupportedInstructionWithTrampoline) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunctionWithTrampoline;
FunctionPrefixKind prefix = FunctionPrefixPadding;
@@ -764,13 +787,14 @@ TEST(Interception, UnsupportedInstructionWithTrampoline) {
SetErrorReportCallback(Local::Report);
EXPECT_FALSE(TestFunctionPatching(kUnsupportedCode1, override, prefix));
- SetErrorReportCallback(nullptr);
+ SetErrorReportCallback(DebugOutputPrinter::Report);
if (!reportCalled)
ADD_FAILURE() << "Report not called";
}
TEST(Interception, PatchableFunctionPadding) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
TestOverrideFunction override = OverrideFunction;
FunctionPrefixKind prefix = FunctionPrefixPadding;
@@ -824,6 +848,7 @@ std::string dumpInstruction(unsigned arrayIndex,
}
TEST(Interception, GetInstructionSize) {
+ SetErrorReportCallback(DebugOutputPrinter::Report);
for (unsigned i = 0; i < sizeof(data) / sizeof(*data); i++) {
size_t rel_offset = ~0L;
size_t size = __interception::TestOnlyGetInstructionSize(
>From 9e4315dccfc96d728272211ba16d0aff6bc14f1b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 23 Nov 2024 16:56:06 +0100
Subject: [PATCH 04/20] TEMP: Import minimal copy of bddisasm for evaluation.
---
compiler-rt/lib/interception/bddisasm/LICENSE | 201 +
.../bddisasm/bddisasm/bdx86_decoder.c | 4640 +
.../bddisasm/bddisasm/include/bddisasm_crt.h | 49 +
.../bddisasm/include/bdx86_instructions.h | 122121 +++++++++++++++
.../bddisasm/include/bdx86_mnemonics.h | 356 +
.../bddisasm/include/bdx86_prefixes.h | 34 +
.../bddisasm/include/bdx86_table_evex.h | 39825 +++++
.../bddisasm/include/bdx86_table_root.h | 16886 ++
.../bddisasm/include/bdx86_table_vex.h | 14742 ++
.../bddisasm/include/bdx86_table_xop.h | 1557 +
.../bddisasm/include/bdx86_tabledefs.h | 550 +
.../lib/interception/bddisasm/inc/bddisasm.h | 10 +
.../bddisasm/inc/bddisasm_status.h | 65 +
.../bddisasm/inc/bddisasm_types.h | 108 +
.../bddisasm/inc/bddisasm_version.h | 16 +
.../lib/interception/bddisasm/inc/bdshemu.h | 484 +
.../interception/bddisasm/inc/bdshemu_x86.h | 89 +
.../bddisasm/inc/bdx86_constants.h | 2044 +
.../interception/bddisasm/inc/bdx86_core.h | 1720 +
.../bddisasm/inc/bdx86_cpuidflags.h | 148 +
.../bddisasm/inc/bdx86_registers.h | 160 +
.../bddisasm/llvm-project-import.txt | 2 +
22 files changed, 205807 insertions(+)
create mode 100644 compiler-rt/lib/interception/bddisasm/LICENSE
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/bdx86_decoder.c
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bddisasm_crt.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_instructions.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_mnemonics.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_prefixes.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_evex.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_root.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_vex.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_xop.h
create mode 100644 compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_tabledefs.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bddisasm.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bddisasm_status.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bddisasm_types.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bddisasm_version.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bdshemu.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bdshemu_x86.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bdx86_constants.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bdx86_core.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bdx86_cpuidflags.h
create mode 100644 compiler-rt/lib/interception/bddisasm/inc/bdx86_registers.h
create mode 100644 compiler-rt/lib/interception/bddisasm/llvm-project-import.txt
diff --git a/compiler-rt/lib/interception/bddisasm/LICENSE b/compiler-rt/lib/interception/bddisasm/LICENSE
new file mode 100644
index 00000000000000..7652714e6d96d7
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/LICENSE
@@ -0,0 +1,201 @@
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diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/bdx86_decoder.c b/compiler-rt/lib/interception/bddisasm/bddisasm/bdx86_decoder.c
new file mode 100644
index 00000000000000..c03acc978aa4fb
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/bdx86_decoder.c
@@ -0,0 +1,4640 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "include/bddisasm_crt.h"
+#include "../inc/bddisasm.h"
+
+// The table definitions.
+#include "include/bdx86_tabledefs.h"
+
+#ifndef UNREFERENCED_PARAMETER
+#define UNREFERENCED_PARAMETER(P) ((void)(P))
+#endif
+
+
+static const ND_UINT8 gDispsizemap16[4][8] =
+{
+ { 0, 0, 0, 0, 0, 0, 2, 0 },
+ { 1, 1, 1, 1, 1, 1, 1, 1 },
+ { 2, 2, 2, 2, 2, 2, 2, 2 },
+ { 0, 0, 0, 0, 0, 0, 0, 0 },
+};
+
+static const ND_UINT8 gDispsizemap[4][8] =
+{
+ { 0, 0, 0, 0, 0, 4, 0, 0 },
+ { 1, 1, 1, 1, 1, 1, 1, 1 },
+ { 4, 4, 4, 4, 4, 4, 4, 4 },
+ { 0, 0, 0, 0, 0, 0, 0, 0 },
+};
+
+
+//
+// NdGetVersion
+//
+void
+NdGetVersion(
+ ND_UINT32 *Major,
+ ND_UINT32 *Minor,
+ ND_UINT32 *Revision,
+ const char **BuildDate,
+ const char **BuildTime
+ )
+{
+ if (ND_NULL != Major)
+ {
+ *Major = DISASM_VERSION_MAJOR;
+ }
+
+ if (ND_NULL != Minor)
+ {
+ *Minor = DISASM_VERSION_MINOR;
+ }
+
+ if (ND_NULL != Revision)
+ {
+ *Revision = DISASM_VERSION_REVISION;
+ }
+
+//
+// Do not use __TIME__ and __DATE__ macros when compiling against a kernel tree.
+//
+#if defined(__KERNEL__)
+
+ if (ND_NULL != BuildDate)
+ {
+ *BuildDate = (char *)ND_NULL;
+ }
+
+ if (ND_NULL != BuildTime)
+ {
+ *BuildTime = (char *)ND_NULL;
+ }
+
+#else
+
+ if (ND_NULL != BuildDate)
+ {
+ *BuildDate = __DATE__;
+ }
+
+ if (ND_NULL != BuildTime)
+ {
+ *BuildTime = __TIME__;
+ }
+
+#endif
+
+}
+
+//
+// NdFetchData
+//
+static ND_UINT64
+NdFetchData(
+ const ND_UINT8 *Buffer,
+ ND_UINT8 Size
+ )
+{
+ switch (Size)
+ {
+ case 1:
+ return ND_FETCH_8(Buffer);
+ case 2:
+ return ND_FETCH_16(Buffer);
+ case 4:
+ return ND_FETCH_32(Buffer);
+ case 8:
+ return ND_FETCH_64(Buffer);
+ default:
+ return 0;
+ }
+}
+
+
+//
+// NdFetchXop
+//
+static NDSTATUS
+NdFetchXop(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ // Offset points to the 0x8F XOP prefix.
+ // One more byte has to follow, the modrm or the second XOP byte.
+ RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ if (((Code[Offset + 1] & 0x1F) >= 8))
+ {
+ // XOP found, make sure the third byte is here.
+ RET_GT((ND_SIZET)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // Make sure we don't have any other prefix.
+ if (Instrux->HasOpSize ||
+ Instrux->HasRepnzXacquireBnd ||
+ Instrux->HasRepRepzXrelease ||
+ Instrux->HasRex ||
+ Instrux->HasRex2)
+ {
+ return ND_STATUS_XOP_WITH_PREFIX;
+ }
+
+ // Fill in XOP info.
+ Instrux->HasXop = ND_TRUE;
+ Instrux->EncMode = ND_ENCM_XOP;
+ Instrux->Xop.Xop[0] = Code[Offset];
+ Instrux->Xop.Xop[1] = Code[Offset + 1];
+ Instrux->Xop.Xop[2] = Code[Offset + 2];
+
+ Instrux->Exs.w = Instrux->Xop.w;
+ Instrux->Exs.r = (ND_UINT32)~Instrux->Xop.r;
+ Instrux->Exs.x = (ND_UINT32)~Instrux->Xop.x;
+ Instrux->Exs.b = (ND_UINT32)~Instrux->Xop.b;
+ Instrux->Exs.l = Instrux->Xop.l;
+ Instrux->Exs.v = (ND_UINT32)~Instrux->Xop.v;
+ Instrux->Exs.m = Instrux->Xop.m;
+ Instrux->Exs.p = Instrux->Xop.p;
+
+ // if we are in non 64 bit mode, we must make sure that none of the extended registers are being addressed.
+ if (Instrux->DefCode != ND_CODE_64)
+ {
+ // Xop.R and Xop.X must be 1 (inverted).
+ if ((Instrux->Exs.r | Instrux->Exs.x) == 1)
+ {
+ return ND_STATUS_INVALID_ENCODING_IN_MODE;
+ }
+
+ // Xop.V must be less than 8.
+ if ((Instrux->Exs.v & 0x8) == 0x8)
+ {
+ return ND_STATUS_INVALID_ENCODING_IN_MODE;
+ }
+
+ // Xop.B is ignored, so we force it to 0.
+ Instrux->Exs.b = 0;
+ }
+
+ // Update Instrux length & offset, and make sure we don't exceed 15 bytes.
+ Instrux->Length += 3;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchVex2
+//
+static NDSTATUS
+NdFetchVex2(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ // One more byte has to follow, the modrm or the second VEX byte.
+ RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // VEX is available only in 32 & 64 bit mode.
+ if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0))
+ {
+ // Make sure we don't have any other prefix.
+ if (Instrux->HasOpSize ||
+ Instrux->HasRepnzXacquireBnd ||
+ Instrux->HasRepRepzXrelease ||
+ Instrux->HasRex ||
+ Instrux->HasRex2 ||
+ Instrux->HasLock)
+ {
+ return ND_STATUS_VEX_WITH_PREFIX;
+ }
+
+ // Fill in VEX2 info.
+ Instrux->VexMode = ND_VEXM_2B;
+ Instrux->HasVex = ND_TRUE;
+ Instrux->EncMode = ND_ENCM_VEX;
+ Instrux->Vex2.Vex[0] = Code[Offset];
+ Instrux->Vex2.Vex[1] = Code[Offset + 1];
+
+ Instrux->Exs.m = 1; // For VEX2 instructions, always use the second table.
+ Instrux->Exs.r = (ND_UINT32)~Instrux->Vex2.r;
+ Instrux->Exs.v = (ND_UINT32)~Instrux->Vex2.v;
+ Instrux->Exs.l = Instrux->Vex2.l;
+ Instrux->Exs.p = Instrux->Vex2.p;
+
+ // Update Instrux length & offset, and make sure we don't exceed 15 bytes.
+ Instrux->Length += 2;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchVex3
+//
+static NDSTATUS
+NdFetchVex3(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ // One more byte has to follow, the modrm or the second VEX byte.
+ RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // VEX is available only in 32 & 64 bit mode.
+ if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0))
+ {
+ // VEX found, make sure the third byte is here.
+ RET_GT((ND_SIZET)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // Make sure we don't have any other prefix.
+ if (Instrux->HasOpSize ||
+ Instrux->HasRepnzXacquireBnd ||
+ Instrux->HasRepRepzXrelease ||
+ Instrux->HasRex ||
+ Instrux->HasRex2 ||
+ Instrux->HasLock)
+ {
+ return ND_STATUS_VEX_WITH_PREFIX;
+ }
+
+ // Fill in XOP info.
+ Instrux->VexMode = ND_VEXM_3B;
+ Instrux->HasVex = ND_TRUE;
+ Instrux->EncMode = ND_ENCM_VEX;
+ Instrux->Vex3.Vex[0] = Code[Offset];
+ Instrux->Vex3.Vex[1] = Code[Offset + 1];
+ Instrux->Vex3.Vex[2] = Code[Offset + 2];
+
+ Instrux->Exs.r = (ND_UINT32)~Instrux->Vex3.r;
+ Instrux->Exs.x = (ND_UINT32)~Instrux->Vex3.x;
+ Instrux->Exs.b = (ND_UINT32)~Instrux->Vex3.b;
+ Instrux->Exs.m = Instrux->Vex3.m;
+ Instrux->Exs.w = Instrux->Vex3.w;
+ Instrux->Exs.v = (ND_UINT32)~Instrux->Vex3.v;
+ Instrux->Exs.l = Instrux->Vex3.l;
+ Instrux->Exs.p = Instrux->Vex3.p;
+
+ // Do validations in case of VEX outside 64 bits.
+ if (Instrux->DefCode != ND_CODE_64)
+ {
+ // Vex.R and Vex.X have been tested by the initial if.
+
+ // Vex.vvvv must be less than 8.
+ Instrux->Exs.v &= 7;
+
+ // Vex.B is ignored, so we force it to 0.
+ Instrux->Exs.b = 0;
+ }
+
+ // Update Instrux length & offset, and make sure we don't exceed 15 bytes.
+ Instrux->Length += 3;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchEvex
+//
+static NDSTATUS
+NdFetchEvex(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ // One more byte has to follow, the modrm or the second VEX byte.
+ RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ if ((ND_CODE_64 != Instrux->DefCode) && ((Code[Offset + 1] & 0xC0) != 0xC0))
+ {
+ // BOUND instruction in non-64 bit mode, not EVEX.
+ return ND_STATUS_SUCCESS;
+ }
+
+ // EVEX found, make sure all the bytes are present. At least 4 bytes in total must be present.
+ RET_GT((ND_SIZET)Offset + 4, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // This is EVEX.
+ Instrux->HasEvex = ND_TRUE;
+ Instrux->EncMode = ND_ENCM_EVEX;
+ Instrux->Evex.Evex[0] = Code[Offset + 0];
+ Instrux->Evex.Evex[1] = Code[Offset + 1];
+ Instrux->Evex.Evex[2] = Code[Offset + 2];
+ Instrux->Evex.Evex[3] = Code[Offset + 3];
+
+ // Legacy prefixes are not accepted with EVEX.
+ if (Instrux->HasOpSize ||
+ Instrux->HasRepnzXacquireBnd ||
+ Instrux->HasRepRepzXrelease ||
+ Instrux->HasRex ||
+ Instrux->HasRex2 ||
+ Instrux->HasLock)
+ {
+ return ND_STATUS_EVEX_WITH_PREFIX;
+ }
+
+ // Do the opcode independent checks. Opcode dependent checks are done when decoding each instruction.
+ if (Instrux->Evex.m == 0)
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ // Check map. Maps 4 & 7 are allowed only if APX is enabled.
+ if (Instrux->Evex.m == 4 || Instrux->Evex.m == 7)
+ {
+ if (!(Instrux->FeatMode & ND_FEAT_APX))
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+ }
+
+
+ // Fill in the generic extension bits. We initially optimistically fill in all possible values.
+ // Once we determine the opcode and, subsequently, the EVEX extension mode, we will do further
+ // validations, and reset unused fields to 0.
+ Instrux->Exs.r = (ND_UINT32)~Instrux->Evex.r;
+ Instrux->Exs.x = (ND_UINT32)~Instrux->Evex.x;
+ Instrux->Exs.b = (ND_UINT32)~Instrux->Evex.b;
+ Instrux->Exs.rp = (ND_UINT32)~Instrux->Evex.rp;
+ Instrux->Exs.x4 = (ND_UINT32)~Instrux->Evex.u;
+ Instrux->Exs.b4 = Instrux->Evex.b4;
+ Instrux->Exs.m = Instrux->Evex.m;
+ Instrux->Exs.w = Instrux->Evex.w;
+ Instrux->Exs.v = (ND_UINT32)~Instrux->Evex.v;
+ Instrux->Exs.vp = (ND_UINT32)~Instrux->Evex.vp;
+ Instrux->Exs.p = Instrux->Evex.p;
+
+ Instrux->Exs.z = Instrux->Evex.z;
+ Instrux->Exs.l = Instrux->Evex.l;
+ Instrux->Exs.bm = Instrux->Evex.bm;
+ Instrux->Exs.k = Instrux->Evex.a;
+
+ // EVEX extensions. The fields are undefined if the encoding does not use them.
+ Instrux->Exs.nf = (Instrux->Evex.Evex[3] >> 2) & 1;
+ Instrux->Exs.nd = (Instrux->Evex.Evex[3] >> 4) & 1;
+ Instrux->Exs.sc = (Instrux->Evex.Evex[3] & 0xF);
+
+ // Do EVEX validations outside 64 bits mode.
+ if (ND_CODE_64 != Instrux->DefCode)
+ {
+ // Evex.R and Evex.X must be 1. If they're not, we have BOUND instruction. This is checked in the
+ // first if. Note that they are inverted inside the Evex prefix.
+ Instrux->Exs.r = 0;
+ Instrux->Exs.x = 0;
+
+ // Evex.B is ignored, so we force it to 0.
+ Instrux->Exs.b = 0;
+
+ // Evex.R' is ignored, so we force it to 0.
+ Instrux->Exs.rp = 0;
+
+ // Evex.B4 & Evex.X4 are ignored, so we force them to 0.
+ Instrux->Exs.b4 = Instrux->Exs.x4 = 0;
+
+ // High bit inside Evex.VVVV is ignored, so we force it to 0.
+ Instrux->Exs.v &= 0x7;
+
+ // Evex.V' must be 1 (negated to 0) in 32-bit mode.
+ if (Instrux->Exs.vp == 1)
+ {
+ return ND_STATUS_BAD_EVEX_V_PRIME;
+ }
+ }
+
+ // Update Instrux length & offset, and make sure we don't exceed 15 bytes.
+ Instrux->Length += 4;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchRex2
+//
+static NDSTATUS
+NdFetchRex2(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ if (ND_CODE_64 != Instrux->DefCode)
+ {
+ // AAD instruction outside 64-bit mode.
+ return ND_STATUS_SUCCESS;
+ }
+
+ if (!(Instrux->FeatMode & ND_FEAT_APX))
+ {
+ // APX not enabled, #UD.
+ return ND_STATUS_SUCCESS;
+ }
+
+ // One more byte has to follow.
+ RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // This is REX2.
+ Instrux->HasRex2 = ND_TRUE;
+ Instrux->EncMode = ND_ENCM_LEGACY;
+ Instrux->Rex2.Rex2[0] = Code[Offset + 0];
+ Instrux->Rex2.Rex2[1] = Code[Offset + 1];
+
+ // REX illegal with REX2.
+ if (Instrux->HasRex)
+ {
+ return ND_STATUS_INVALID_PREFIX_SEQUENCE;
+ }
+
+ // Fill in the generic extension bits
+ Instrux->Exs.r = Instrux->Rex2.r3;
+ Instrux->Exs.rp = Instrux->Rex2.r4;
+ Instrux->Exs.x = Instrux->Rex2.x3;
+ Instrux->Exs.x4 = Instrux->Rex2.x4;
+ Instrux->Exs.b = Instrux->Rex2.b3;
+ Instrux->Exs.b4 = Instrux->Rex2.b4;
+ Instrux->Exs.w = Instrux->Rex2.w;
+
+ // Update Instrux length & offset, and make sure we don't exceed 15 bytes.
+ Instrux->Length += 2;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchPrefixes
+//
+static NDSTATUS
+NdFetchPrefixes(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ NDSTATUS status;
+ ND_BOOL morePrefixes;
+ ND_UINT8 prefix;
+
+ morePrefixes = ND_TRUE;
+
+ while (morePrefixes)
+ {
+ morePrefixes = ND_FALSE;
+
+ RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ prefix = Code[Offset];
+
+ // Speedup: if the current byte is not a prefix of any kind, leave now. This will be the case most of the times.
+ if (ND_PREF_CODE_NONE == gPrefixesMap[prefix])
+ {
+ status = ND_STATUS_SUCCESS;
+ goto done_prefixes;
+ }
+
+ if (ND_PREF_CODE_STANDARD == gPrefixesMap[prefix])
+ {
+ switch (prefix)
+ {
+ case ND_PREFIX_G0_LOCK:
+ Instrux->HasLock = ND_TRUE;
+ morePrefixes = ND_TRUE;
+ break;
+ case ND_PREFIX_G1_REPE_REPZ:
+ Instrux->Rep = ND_PREFIX_G1_REPE_REPZ;
+ Instrux->HasRepRepzXrelease = ND_TRUE;
+ morePrefixes = ND_TRUE;
+ break;
+ case ND_PREFIX_G1_REPNE_REPNZ:
+ Instrux->Rep = ND_PREFIX_G1_REPNE_REPNZ;
+ Instrux->HasRepnzXacquireBnd = ND_TRUE;
+ morePrefixes = ND_TRUE;
+ break;
+ case ND_PREFIX_G2_SEG_CS:
+ case ND_PREFIX_G2_SEG_SS:
+ case ND_PREFIX_G2_SEG_DS:
+ case ND_PREFIX_G2_SEG_ES:
+ case ND_PREFIX_G2_SEG_FS:
+ case ND_PREFIX_G2_SEG_GS:
+ if (ND_CODE_64 == Instrux->DefCode)
+ {
+ if (prefix == ND_PREFIX_G2_SEG_FS ||
+ prefix == ND_PREFIX_G2_SEG_GS)
+ {
+ // The last FS/GS is always used, if present.
+ Instrux->Seg = prefix;
+ Instrux->HasSeg = ND_TRUE;
+ }
+ else if (prefix == ND_PREFIX_G2_NO_TRACK &&
+ Instrux->Seg != ND_PREFIX_G2_SEG_FS &&
+ Instrux->Seg != ND_PREFIX_G2_SEG_GS)
+ {
+ // The Do Not Track prefix is considered only if there isn't a FS/GS prefix.
+ Instrux->Seg = prefix;
+ Instrux->HasSeg = ND_TRUE;
+ }
+ else if (Instrux->Seg != ND_PREFIX_G2_SEG_FS &&
+ Instrux->Seg != ND_PREFIX_G2_SEG_GS &&
+ Instrux->Seg != ND_PREFIX_G2_NO_TRACK)
+ {
+ // All other prefixes are considered if Do Not Track, FS, GS are not present.
+ Instrux->Seg = prefix;
+ Instrux->HasSeg = ND_TRUE;
+ }
+ }
+ else
+ {
+ Instrux->Seg = prefix;
+ Instrux->HasSeg = ND_TRUE;
+ }
+ morePrefixes = ND_TRUE;
+ break;
+ case ND_PREFIX_G3_OPERAND_SIZE:
+ Instrux->HasOpSize = ND_TRUE;
+ morePrefixes = ND_TRUE;
+ break;
+ case ND_PREFIX_G4_ADDR_SIZE:
+ Instrux->HasAddrSize = ND_TRUE;
+ morePrefixes = ND_TRUE;
+ break;
+ default:
+ break;
+ }
+ }
+
+ // REX must precede the opcode byte. However, if one or more other prefixes are present, the instruction
+ // will still decode & execute properly, but REX will be ignored.
+ if (morePrefixes && Instrux->HasRex)
+ {
+ Instrux->HasRex = ND_FALSE;
+ Instrux->Rex.Rex = 0;
+ Instrux->Exs.w = 0;
+ Instrux->Exs.r = 0;
+ Instrux->Exs.x = 0;
+ Instrux->Exs.b = 0;
+ }
+
+ // Check for REX.
+ if ((ND_CODE_64 == Instrux->DefCode) && (ND_PREF_CODE_REX == gPrefixesMap[prefix]))
+ {
+ Instrux->HasRex = ND_TRUE;
+ Instrux->Rex.Rex = prefix;
+ Instrux->Exs.w = Instrux->Rex.w;
+ Instrux->Exs.r = Instrux->Rex.r;
+ Instrux->Exs.x = Instrux->Rex.x;
+ Instrux->Exs.b = Instrux->Rex.b;
+ morePrefixes = ND_TRUE;
+ }
+
+ // We have found prefixes, update the instruction length and the current offset.
+ if (morePrefixes)
+ {
+ Instrux->Length++, Offset++;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+ }
+ }
+
+ // We must have at least one more free byte after the prefixes, which will be either the opcode, either
+ // XOP/VEX/EVEX/MVEX prefix.
+ RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // Try to match a XOP/VEX/EVEX/MVEX prefix.
+ if (ND_PREF_CODE_EX == gPrefixesMap[Code[Offset]])
+ {
+ // Check for XOP
+ if (Code[Offset] == ND_PREFIX_XOP)
+ {
+ status = NdFetchXop(Instrux, Code, Offset, Size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+ else if (Code[Offset] == ND_PREFIX_VEX_2B)
+ {
+ status = NdFetchVex2(Instrux, Code, Offset, Size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+ else if (Code[Offset] == ND_PREFIX_VEX_3B)
+ {
+ status = NdFetchVex3(Instrux, Code, Offset, Size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+ else if (Code[Offset] == ND_PREFIX_EVEX)
+ {
+ status = NdFetchEvex(Instrux, Code, Offset, Size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+ else if (Code[Offset] == ND_PREFIX_REX2)
+ {
+ status = NdFetchRex2(Instrux, Code, Offset, Size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+ else
+ {
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+ }
+
+done_prefixes:
+ // The total length of the instruction is the total length of the prefixes right now.
+ Instrux->PrefLength = Instrux->OpOffset = Instrux->Length;
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchOpcode
+//
+static NDSTATUS
+NdFetchOpcode(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ // At least one byte must be available, for the fetched opcode.
+ RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // With REX2, only legacy map & 0x0F map are valid. A single opcode byte can be present, and no
+ // opcode extensions are accepted (for example, 0x0F 0x38 is invalid).
+ if (Instrux->HasRex2 && Instrux->OpLength != 0)
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ Instrux->OpCodeBytes[Instrux->OpLength++] = Code[Offset];
+
+ Instrux->Length++;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchModrm
+//
+static NDSTATUS
+NdFetchModrm(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ // At least one byte must be available, for the modrm byte.
+ RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // If we get called, we assume we have ModRM.
+ Instrux->HasModRm = ND_TRUE;
+
+ // Fetch the ModRM byte & update the offset and the instruction length.
+ Instrux->ModRm.ModRm = Code[Offset];
+ Instrux->ModRmOffset = Offset;
+
+ Instrux->Length++, Offset++;
+
+ // Make sure we don't exceed the maximum instruction length.
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchModrmAndSib
+//
+static NDSTATUS
+NdFetchModrmAndSib(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ // At least one byte must be available, for the modrm byte.
+ RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // If we get called, we assume we have ModRM.
+ Instrux->HasModRm = ND_TRUE;
+
+ // Fetch the ModRM byte & update the offset and the instruction length.
+ Instrux->ModRm.ModRm = Code[Offset];
+ Instrux->ModRmOffset = Offset;
+
+ Instrux->Length++, Offset++;
+
+ // Make sure we don't exceed the maximum instruction length.
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ // If needed, fetch the SIB.
+ if ((Instrux->ModRm.rm == NDR_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16))
+ {
+ // At least one more byte must be available, for the sib.
+ RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // SIB present.
+ Instrux->HasSib = ND_TRUE;
+
+ Instrux->Sib.Sib = Code[Offset];
+ Instrux->Length++;
+
+ // Make sure we don't exceed the maximum instruction length.
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchDisplacement
+//
+static NDSTATUS
+NdFetchDisplacement(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+//
+// Will decode the displacement from the instruction. Will fill in extracted information in Instrux,
+// and will update the instruction length.
+//
+{
+ ND_UINT8 displSize;
+
+ displSize = 0;
+
+ if (ND_ADDR_16 == Instrux->AddrMode)
+ {
+ displSize = gDispsizemap16[Instrux->ModRm.mod][Instrux->ModRm.rm];
+ }
+ else
+ {
+ displSize = gDispsizemap[Instrux->ModRm.mod][Instrux->HasSib ? Instrux->Sib.base : Instrux->ModRm.rm];
+ }
+
+ if (0 != displSize)
+ {
+ // Make sure enough buffer space is available.
+ RET_GT((ND_SIZET)Offset + displSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ // If we get here, we have displacement.
+ Instrux->HasDisp = ND_TRUE;
+
+ Instrux->Displacement = (ND_UINT32)NdFetchData(Code + Offset, displSize);
+
+ // Fill in displacement info.
+ Instrux->DispLength = displSize;
+ Instrux->DispOffset = Offset;
+ Instrux->Length += displSize;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchModrmSibDisplacement
+//
+static NDSTATUS
+NdFetchModrmSibDisplacement(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size
+ )
+{
+ NDSTATUS status;
+
+ status = NdFetchModrmAndSib(Instrux, Code, Offset, Size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ return NdFetchDisplacement(Instrux, Code, Instrux->Length, Size);
+}
+
+
+//
+// NdFetchAddressFar
+//
+static NDSTATUS
+NdFetchAddressFar(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size,
+ ND_UINT8 AddressSize
+ )
+{
+ RET_GT((ND_SIZET)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ Instrux->HasAddr = ND_TRUE;
+ Instrux->AddrLength = AddressSize;
+ Instrux->AddrOffset = Offset;
+
+ Instrux->Address.Ip = (ND_UINT32)NdFetchData(Code + Offset, Instrux->AddrLength - 2);
+ Instrux->Address.Cs = (ND_UINT16)NdFetchData(Code + Offset + Instrux->AddrLength - 2, 2);
+
+ Instrux->Length += Instrux->AddrLength;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchAddressNear
+//
+static NDSTATUS
+NdFetchAddressNear(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size,
+ ND_UINT8 AddressSize
+ )
+{
+ RET_GT((ND_SIZET)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ Instrux->HasAddrNear = ND_TRUE;
+ Instrux->AddrLength = AddressSize;
+ Instrux->AddrOffset = Offset;
+
+ Instrux->AddressNear = (ND_UINT64)NdFetchData(Code + Offset, Instrux->AddrLength);
+
+ Instrux->Length += Instrux->AddrLength;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchImmediate
+//
+static NDSTATUS
+NdFetchImmediate(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size,
+ ND_UINT8 ImmediateSize
+ )
+{
+ ND_UINT64 imm;
+
+ RET_GT((ND_SIZET)Offset + ImmediateSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ imm = NdFetchData(Code + Offset, ImmediateSize);
+
+ if (Instrux->HasImm2)
+ {
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+ else if (Instrux->HasImm1)
+ {
+ Instrux->HasImm2 = ND_TRUE;
+ Instrux->Imm2Length = ImmediateSize;
+ Instrux->Imm2Offset = Offset;
+ Instrux->Immediate2 = (ND_UINT8)imm;
+ }
+ else
+ {
+ Instrux->HasImm1 = ND_TRUE;
+ Instrux->Imm1Length = ImmediateSize;
+ Instrux->Imm1Offset = Offset;
+ Instrux->Immediate1 = imm;
+ }
+
+ Instrux->Length += ImmediateSize;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchRelativeOffset
+//
+static NDSTATUS
+NdFetchRelativeOffset(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size,
+ ND_UINT8 RelOffsetSize
+ )
+{
+ // Make sure we don't outrun the buffer.
+ RET_GT((ND_SIZET)Offset + RelOffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ Instrux->HasRelOffs = ND_TRUE;
+ Instrux->RelOffsLength = RelOffsetSize;
+ Instrux->RelOffsOffset = Offset;
+
+ Instrux->RelativeOffset = (ND_UINT32)NdFetchData(Code + Offset, RelOffsetSize);
+
+ Instrux->Length += RelOffsetSize;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchMoffset
+//
+static NDSTATUS
+NdFetchMoffset(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size,
+ ND_UINT8 MoffsetSize
+ )
+{
+ RET_GT((ND_SIZET)Offset + MoffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ Instrux->HasMoffset = ND_TRUE;
+ Instrux->MoffsetLength = MoffsetSize;
+ Instrux->MoffsetOffset = Offset;
+
+ Instrux->Moffset = NdFetchData(Code + Offset, MoffsetSize);
+
+ Instrux->Length += MoffsetSize;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdFetchSseImmediate
+//
+static NDSTATUS
+NdFetchSseImmediate(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size,
+ ND_UINT8 SseImmSize
+ )
+{
+ RET_GT((ND_SIZET)Offset + SseImmSize, Size, ND_STATUS_BUFFER_TOO_SMALL);
+
+ Instrux->HasSseImm = ND_TRUE;
+ Instrux->SseImmOffset = Offset;
+ Instrux->SseImmediate = *(Code + Offset);
+
+ Instrux->Length += SseImmSize;
+ if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH)
+ {
+ return ND_STATUS_INSTRUCTION_TOO_LONG;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdGetSegOverride
+//
+static ND_UINT8
+NdGetSegOverride(
+ INSTRUX *Instrux,
+ ND_UINT8 DefaultSeg
+ )
+{
+ // Return default seg, if no override present.
+ if (Instrux->Seg == 0)
+ {
+ return DefaultSeg;
+ }
+
+ // In 64 bit mode, the segment override is ignored, except for FS and GS.
+ if ((Instrux->DefCode == ND_CODE_64) &&
+ (Instrux->Seg != ND_PREFIX_G2_SEG_FS) &&
+ (Instrux->Seg != ND_PREFIX_G2_SEG_GS))
+ {
+ return DefaultSeg;
+ }
+
+ switch (Instrux->Seg)
+ {
+ case ND_PREFIX_G2_SEG_CS:
+ return NDR_CS;
+ case ND_PREFIX_G2_SEG_DS:
+ return NDR_DS;
+ case ND_PREFIX_G2_SEG_ES:
+ return NDR_ES;
+ case ND_PREFIX_G2_SEG_SS:
+ return NDR_SS;
+ case ND_PREFIX_G2_SEG_FS:
+ return NDR_FS;
+ case ND_PREFIX_G2_SEG_GS:
+ return NDR_GS;
+ default:
+ return DefaultSeg;
+ }
+}
+
+
+//
+// NdGetCompDispSize
+//
+static ND_UINT8
+NdGetCompDispSize(
+ const INSTRUX *Instrux,
+ ND_UINT32 MemSize
+ )
+{
+ static const ND_UINT8 fvszLut[4] = { 16, 32, 64, 0 };
+ static const ND_UINT8 hvszLut[4] = { 8, 16, 32, 0 };
+ static const ND_UINT8 qvszLut[4] = { 4, 8, 16, 0 };
+ static const ND_UINT8 dupszLut[4] = { 8, 32, 64, 0 };
+ static const ND_UINT8 fvmszLut[4] = { 16, 32, 64, 0 };
+ static const ND_UINT8 hvmszLut[4] = { 8, 16, 32, 0 };
+ static const ND_UINT8 qvmszLut[4] = { 4, 8, 16, 0 };
+ static const ND_UINT8 ovmszLut[4] = { 2, 4, 8, 0 };
+
+ if (Instrux->HasBroadcast)
+ {
+ // If the instruction uses broadcast, then compressed displacement will use the size of the element as scale:
+ // - 2 when broadcasting 16 bit
+ // - 4 when broadcasting 32 bit
+ // - 8 when broadcasting 64 bit
+ return (ND_UINT8)MemSize;
+ }
+
+ switch (Instrux->TupleType)
+ {
+ case ND_TUPLE_FV:
+ return fvszLut[Instrux->Exs.l];
+ case ND_TUPLE_HV:
+ return hvszLut[Instrux->Exs.l];
+ case ND_TUPLE_QV:
+ return qvszLut[Instrux->Exs.l];
+ case ND_TUPLE_DUP:
+ return dupszLut[Instrux->Exs.l];
+ case ND_TUPLE_FVM:
+ return fvmszLut[Instrux->Exs.l];
+ case ND_TUPLE_HVM:
+ return hvmszLut[Instrux->Exs.l];
+ case ND_TUPLE_QVM:
+ return qvmszLut[Instrux->Exs.l];
+ case ND_TUPLE_OVM:
+ return ovmszLut[Instrux->Exs.l];
+ case ND_TUPLE_M128:
+ return 16;
+ case ND_TUPLE_T1S8:
+ return 1;
+ case ND_TUPLE_T1S16:
+ return 2;
+ case ND_TUPLE_T1S:
+ return !!(Instrux->Attributes & ND_FLAG_WIG) ? 4 : Instrux->Exs.w ? 8 : 4;
+ case ND_TUPLE_T1F:
+ return (ND_UINT8)MemSize;
+ case ND_TUPLE_T2:
+ return Instrux->Exs.w ? 16 : 8;
+ case ND_TUPLE_T4:
+ return Instrux->Exs.w ? 32 : 16;
+ case ND_TUPLE_T8:
+ return 32;
+ case ND_TUPLE_T1_4X:
+ return 16;
+ default:
+ // Default - we assume byte granularity for memory accesses, therefore, no scaling will be done.
+ return 1;
+ }
+}
+
+
+//
+// NdParseMemoryOperand16
+//
+static NDSTATUS
+NdParseMemoryOperand16(
+ INSTRUX *Instrux,
+ ND_OPERAND *Operand
+ )
+{
+ if (Instrux->Attributes & ND_FLAG_NOA16)
+ {
+ return ND_STATUS_16_BIT_ADDRESSING_NOT_SUPPORTED;
+ }
+
+ switch (Instrux->ModRm.rm)
+ {
+ case 0:
+ // [bx + si]
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.HasIndex = ND_TRUE;
+ Operand->Info.Memory.Scale = 1;
+ Operand->Info.Memory.Base = NDR_BX;
+ Operand->Info.Memory.Index = NDR_SI;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_DS;
+ break;
+ case 1:
+ // [bx + di]
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.HasIndex = ND_TRUE;
+ Operand->Info.Memory.Scale = 1;
+ Operand->Info.Memory.Base = NDR_BX;
+ Operand->Info.Memory.Index = NDR_DI;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_DS;
+ break;
+ case 2:
+ // [bp + si]
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.HasIndex = ND_TRUE;
+ Operand->Info.Memory.Scale = 1;
+ Operand->Info.Memory.Base = NDR_BP;
+ Operand->Info.Memory.Index = NDR_SI;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_SS;
+ break;
+ case 3:
+ // [bp + di]
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.HasIndex = ND_TRUE;
+ Operand->Info.Memory.Scale = 1;
+ Operand->Info.Memory.Base = NDR_BP;
+ Operand->Info.Memory.Index = NDR_DI;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_SS;
+ break;
+ case 4:
+ // [si]
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.Base = NDR_SI;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_DS;
+ break;
+ case 5:
+ // [di]
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.Base = NDR_DI;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_DS;
+ break;
+ case 6:
+ // [bp]
+ if (Instrux->ModRm.mod != 0)
+ {
+ // If mod is not zero, than we have "[bp + displacement]".
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.Base = NDR_BP;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_SS;
+ }
+ else
+ {
+ // If mod is zero, than we only have a displacement that is used to directly address mem.
+ Operand->Info.Memory.Seg = NDR_DS;
+ }
+ break;
+ case 7:
+ // [bx]
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.Base = NDR_BX;
+ Operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
+ Operand->Info.Memory.Seg = NDR_DS;
+ break;
+ }
+
+ // Store the displacement.
+ Operand->Info.Memory.HasDisp = !!Instrux->HasDisp;
+ Operand->Info.Memory.DispSize = Instrux->DispLength;
+ Operand->Info.Memory.Disp = Instrux->HasDisp ? ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement) : 0;
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdParseMemoryOperand3264
+//
+static NDSTATUS
+NdParseMemoryOperand3264(
+ INSTRUX *Instrux,
+ ND_OPERAND *Operand,
+ ND_REG_SIZE VsibRegSize
+ )
+{
+ ND_UINT8 defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT);
+
+ // Implicit segment is DS.
+ Operand->Info.Memory.Seg = NDR_DS;
+
+ if (Instrux->HasSib)
+ {
+ // Check for base.
+ if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == NDR_RBP))
+ {
+ // Mod is mem without displacement and base reg is RBP -> no base reg used.
+ // Note that this addressing mode is not RIP relative.
+ }
+ else
+ {
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.BaseSize = defsize;
+ Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->Sib.base;
+
+ if (Instrux->Exs.b4 != 0)
+ {
+ // If APX is present, extend the base.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP))
+ {
+ Operand->Info.Memory.Seg = NDR_SS;
+ }
+ }
+
+ // Check for index.
+ if (ND_HAS_VSIB(Instrux))
+ {
+ // With VSIB, the index reg can be 4 (RSP equivalent). Bit 4 of the 32-bit index register is given by the
+ // EVEX.V' field.
+ Operand->Info.Memory.HasIndex = ND_TRUE;
+ Operand->Info.Memory.IndexSize = defsize;
+ Operand->Info.Memory.Index = (ND_UINT8)((Instrux->Exs.vp << 4) | (Instrux->Exs.x << 3) | Instrux->Sib.index);
+ Operand->Info.Memory.IndexSize = (ND_UINT8)VsibRegSize;
+ Operand->Info.Memory.Scale = 1 << Instrux->Sib.scale;
+ }
+ else
+ {
+ // Regular SIB, index RSP is ignored. Bit 4 of the 32-bit index register is given by the X4 field.
+ Operand->Info.Memory.Index = (ND_UINT8)(Instrux->Exs.x << 3) | Instrux->Sib.index;
+
+ if (Instrux->Exs.x4 != 0)
+ {
+ // If APX is present, extend the index.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ Operand->Info.Memory.Index |= Instrux->Exs.x4 << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ if (Operand->Info.Memory.Index != NDR_RSP)
+ {
+ // Index * Scale is present.
+ Operand->Info.Memory.HasIndex = ND_TRUE;
+ Operand->Info.Memory.IndexSize = defsize;
+ Operand->Info.Memory.Scale = 1 << Instrux->Sib.scale;
+ }
+ }
+ }
+ else
+ {
+ if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == NDR_RBP))
+ {
+ //
+ // RIP relative addressing addresses a memory region relative to the current RIP; However,
+ // the current RIP, when executing the current instruction, is already updated and points
+ // to the next instruction, therefore, we must add the instruction length also to the final
+ // address. Note that RIP relative addressing is used even if the instruction uses 32 bit
+ // addressing, as long as we're in long mode.
+ //
+ Operand->Info.Memory.IsRipRel = Instrux->IsRipRelative = (Instrux->DefCode == ND_CODE_64);
+
+ // Some instructions (example: MPX) don't support RIP relative addressing.
+ if (Operand->Info.Memory.IsRipRel && !!(Instrux->Attributes & ND_FLAG_NO_RIP_REL))
+ {
+ return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED;
+ }
+ }
+ else
+ {
+ Operand->Info.Memory.HasBase = ND_TRUE;
+ Operand->Info.Memory.BaseSize = defsize;
+ Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm;
+
+ if (Instrux->Exs.b4 != 0)
+ {
+ // If APX is present, extend the base register.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP))
+ {
+ Operand->Info.Memory.Seg = NDR_SS;
+ }
+ }
+ }
+
+ Operand->Info.Memory.HasDisp = Instrux->HasDisp;
+ Operand->Info.Memory.DispSize = Instrux->DispLength;
+ Operand->Info.Memory.Disp = Instrux->HasDisp ? ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement) : 0;
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+
+//
+// NdParseOperand
+//
+static NDSTATUS
+NdParseOperand(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 Offset,
+ ND_SIZET Size,
+ ND_UINT32 Index,
+ ND_UINT64 Specifier
+ )
+{
+ NDSTATUS status;
+ PND_OPERAND operand;
+ ND_UINT8 opt, ops, opf, opa, opd, opb;
+ ND_REG_SIZE vsibRegSize;
+ ND_UINT8 vsibIndexSize, vsibIndexCount;
+ ND_OPERAND_SIZE size;
+ ND_BOOL width;
+
+ // pre-init
+ status = ND_STATUS_SUCCESS;
+ vsibRegSize = 0;
+ vsibIndexSize = vsibIndexCount = 0;
+ size = 0;
+
+ // Get actual width.
+ width = Instrux->Exs.w && !(Instrux->Attributes & ND_FLAG_WIG);
+
+ // Get operand components.
+ opt = ND_OP_TYPE(Specifier);
+ ops = ND_OP_SIZE(Specifier);
+ opf = ND_OP_FLAGS(Specifier);
+ opa = ND_OP_ACCESS(Specifier);
+ opd = ND_OP_DECORATORS(Specifier);
+ opb = ND_OP_BLOCK(Specifier);
+
+ // Get a pointer to our op.
+ operand = &Instrux->Operands[Index];
+
+ // Fill in the flags.
+ operand->Flags.Flags = opf;
+
+ // Store operand access modes.
+ operand->Access.Access = opa;
+
+ // Implicit operand access, by default.
+ operand->Encoding = ND_OPE_S;
+
+
+ //
+ // Fill in operand size.
+ //
+ switch (ops)
+ {
+ case ND_OPS_asz:
+ // Size given by the address mode.
+ size = 2 << Instrux->AddrMode;
+ break;
+
+ case ND_OPS_ssz:
+ // Size given by the stack mode.
+ size = 2 << Instrux->DefStack;
+ break;
+
+ case ND_OPS_0:
+ // No memory access. 0 operand size.
+ size = 0;
+ break;
+
+ case ND_OPS_b:
+ // 8 bits.
+ size = ND_SIZE_8BIT;
+ break;
+
+ case ND_OPS_w:
+ // 16 bits.
+ size = ND_SIZE_16BIT;
+ break;
+
+ case ND_OPS_d:
+ // 32 bits.
+ size = ND_SIZE_32BIT;
+ break;
+
+ case ND_OPS_q:
+ // 64 bits.
+ size = ND_SIZE_64BIT;
+ break;
+
+ case ND_OPS_dq:
+ // 128 bits.
+ size = ND_SIZE_128BIT;
+ break;
+
+ case ND_OPS_qq:
+ // 256 bits.
+ size = ND_SIZE_256BIT;
+ break;
+
+ case ND_OPS_oq:
+ // 512 bits.
+ size = ND_SIZE_512BIT;
+ break;
+
+ case ND_OPS_fa:
+ // 80 bits packed BCD.
+ size = ND_SIZE_80BIT;
+ break;
+
+ case ND_OPS_fw:
+ // 16 bits real number.
+ size = ND_SIZE_16BIT;
+ break;
+
+ case ND_OPS_fd:
+ // 32 bits real number.
+ size = ND_SIZE_32BIT;
+ break;
+
+ case ND_OPS_fq:
+ // 64 bits real number.
+ size = ND_SIZE_64BIT;
+ break;
+
+ case ND_OPS_ft:
+ // 80 bits real number.
+ size = ND_SIZE_80BIT;
+ break;
+
+ case ND_OPS_fe:
+ // 14 bytes or 28 bytes FPU environment.
+ size = (Instrux->EfOpMode == ND_OPSZ_16) ? ND_SIZE_112BIT : ND_SIZE_224BIT;
+ break;
+
+ case ND_OPS_fs:
+ // 94 bytes or 108 bytes FPU state.
+ size = (Instrux->EfOpMode == ND_OPSZ_16) ? ND_SIZE_752BIT : ND_SIZE_864BIT;
+ break;
+
+ case ND_OPS_rx:
+ // 512 bytes extended state.
+ size = ND_SIZE_4096BIT;
+ break;
+
+ case ND_OPS_cl:
+ // The size of one cache line.
+ size = ND_SIZE_CACHE_LINE;
+ break;
+
+ case ND_OPS_v:
+ // 16, 32 or 64 bits.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+
+ size = szLut[Instrux->EfOpMode];
+ }
+ break;
+
+ case ND_OPS_y:
+ // 64 bits (64-bit opsize), 32 bits othwerwise.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+
+ size = szLut[Instrux->EfOpMode];
+ }
+ break;
+
+ case ND_OPS_yf:
+ // 64 bits (64-bit mode), 32 bits (16, 32-bit opsize).
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+
+ size = szLut[Instrux->DefCode];
+ }
+ break;
+
+ case ND_OPS_z:
+ // 16 bits (16-bit opsize) or 32 bits (32 or 64-bit opsize).
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_32BIT };
+
+ size = szLut[Instrux->EfOpMode];
+ }
+ break;
+
+ case ND_OPS_a:
+ // 2 x 16 bits (16-bit opsize) or 2 x 32 bits (32-bit opsize).
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT * 2, ND_SIZE_32BIT * 2, 0 };
+
+ if (Instrux->DefCode > ND_CODE_32)
+ {
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+
+ size = szLut[Instrux->EfOpMode];
+ }
+ break;
+
+ case ND_OPS_c:
+ // 8 bits (16-bit opsize) or 16 bits (32-bit opsize).
+ switch (Instrux->DefCode)
+ {
+ case ND_CODE_16:
+ size = Instrux->HasOpSize ? ND_SIZE_16BIT : ND_SIZE_8BIT;
+ break;
+ case ND_CODE_32:
+ size = Instrux->HasOpSize ? ND_SIZE_16BIT : ND_SIZE_32BIT;
+ break;
+ case ND_CODE_64:
+ size = ND_SIZE_64BIT;
+ break;
+ default:
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+ break;
+
+ case ND_OPS_p:
+ // 32, 48 or 80 bits pointer.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_48BIT, ND_SIZE_80BIT };
+
+ size = szLut[Instrux->EfOpMode];
+ }
+ break;
+
+ case ND_OPS_s:
+ // 48 or 80 bits descriptor.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_48BIT, ND_SIZE_48BIT, ND_SIZE_80BIT };
+
+ size = szLut[Instrux->DefCode];
+ }
+ break;
+
+ case ND_OPS_l:
+ // 64 (16 or 32-bit opsize) or 128 bits (64-bit opsize).
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_64BIT, ND_SIZE_64BIT, ND_SIZE_128BIT };
+
+ size = szLut[Instrux->DefCode];
+ }
+ break;
+
+ case ND_OPS_x:
+ // lower vector = 128 (128-bit vlen) or 256 bits (256-bit vlen).
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
+
+ size = szLut[Instrux->EfVecMode];
+ }
+ break;
+
+ case ND_OPS_fv:
+ // full vector = 128, 256 or 512 bits.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
+
+ size = szLut[Instrux->EfVecMode];
+ }
+ break;
+
+ case ND_OPS_uv:
+ // upper vector = 256 bits (256-bit vlen) or 512 bits (512-bit vlen)
+ {
+ static const ND_UINT8 szLut[3] = { 0, ND_SIZE_256BIT, ND_SIZE_512BIT };
+
+ if (ND_VECM_128 == Instrux->EfVecMode)
+ {
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+
+ size = szLut[Instrux->EfVecMode];
+ }
+ break;
+
+ case ND_OPS_ev:
+ // eighth vector = 16, 32 or 64 bits.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+
+ size = szLut[Instrux->EfVecMode];
+ }
+ break;
+
+ case ND_OPS_qv:
+ // quarter vector = 32, 64 or 128 bits.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_32BIT, ND_SIZE_64BIT, ND_SIZE_128BIT };
+
+ size = szLut[Instrux->EfVecMode];
+ }
+ break;
+
+ case ND_OPS_hv:
+ // half vector = 64, 128 or 256 bits.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_64BIT, ND_SIZE_128BIT, ND_SIZE_256BIT };
+
+ size = szLut[Instrux->EfVecMode];
+ }
+ break;
+
+ case ND_OPS_pd:
+ case ND_OPS_ps:
+ case ND_OPS_ph:
+ // 128 or 256 bits.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
+
+ size = szLut[Instrux->EfVecMode];
+ }
+ break;
+
+ case ND_OPS_sd:
+ // 128 bits scalar element (double precision).
+ size = ND_SIZE_64BIT;
+ break;
+
+ case ND_OPS_ss:
+ // 128 bits scalar element (single precision).
+ size = ND_SIZE_32BIT;
+ break;
+
+ case ND_OPS_sh:
+ // FP16 Scalar element.
+ size = ND_SIZE_16BIT;
+ break;
+
+ case ND_OPS_mib:
+ // MIB addressing, the base & the index are used to form a pointer.
+ size = 0;
+ break;
+
+ case ND_OPS_vm32x:
+ case ND_OPS_vm32y:
+ case ND_OPS_vm32z:
+ // 32 bit indexes from XMM, YMM or ZMM register.
+ vsibIndexSize = ND_SIZE_32BIT;
+ vsibIndexCount = (Instrux->Exs.l == 0) ? 4 : ((Instrux->Exs.l == 1) ? 8 : 16);
+ vsibRegSize = (ops == ND_OPS_vm32x) ? ND_SIZE_128BIT :
+ (ops == ND_OPS_vm32y) ? ND_SIZE_256BIT :
+ ND_SIZE_512BIT;
+ size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT);
+ break;
+
+ case ND_OPS_vm32h:
+ // 32 bit indexes from XMM or YMM.
+ vsibIndexSize = ND_SIZE_32BIT;
+ vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8);
+ vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT :
+ (Instrux->Exs.l == 1) ? ND_SIZE_128BIT :
+ ND_SIZE_256BIT;
+ size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT);
+ break;
+
+ case ND_OPS_vm32n:
+ // 32 bit indexes from XMM, YMM or ZMM register.
+ vsibIndexSize = ND_SIZE_32BIT;
+ vsibIndexCount = (Instrux->Exs.l == 0) ? 4 : ((Instrux->Exs.l == 1) ? 8 : 16);
+ vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT :
+ (Instrux->Exs.l == 1) ? ND_SIZE_256BIT :
+ ND_SIZE_512BIT;
+ size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT);
+ break;
+
+ case ND_OPS_vm64x:
+ case ND_OPS_vm64y:
+ case ND_OPS_vm64z:
+ // 64 bit indexes from XMM, YMM or ZMM register.
+ vsibIndexSize = ND_SIZE_64BIT;
+ vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8);
+ vsibRegSize = (ops == ND_OPS_vm64x) ? ND_SIZE_128BIT :
+ (ops == ND_OPS_vm64y) ? ND_SIZE_256BIT :
+ ND_SIZE_512BIT;
+ size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT);
+ break;
+
+ case ND_OPS_vm64h:
+ // 64 bit indexes from XMM or YMM.
+ vsibIndexSize = ND_SIZE_64BIT;
+ vsibIndexCount = (Instrux->Exs.l == 0) ? 1 : ((Instrux->Exs.l == 1) ? 2 : 4);
+ vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT :
+ (Instrux->Exs.l == 1) ? ND_SIZE_128BIT :
+ ND_SIZE_256BIT;
+ size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT);
+ break;
+
+ case ND_OPS_vm64n:
+ // 64 bit indexes from XMM, YMM or ZMM register.
+ vsibIndexSize = ND_SIZE_64BIT;
+ vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8);
+ vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT :
+ (Instrux->Exs.l == 1) ? ND_SIZE_256BIT :
+ ND_SIZE_512BIT;
+ size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT);
+ break;
+
+ case ND_OPS_v2:
+ case ND_OPS_v3:
+ case ND_OPS_v4:
+ case ND_OPS_v5:
+ case ND_OPS_v8:
+ // Multiple words accessed.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+ ND_UINT8 scale = 1;
+
+ scale = (ops == ND_OPS_v2) ? 2 :
+ (ops == ND_OPS_v3) ? 3 :
+ (ops == ND_OPS_v4) ? 4 :
+ (ops == ND_OPS_v5) ? 5 : 8;
+
+ size = scale * szLut[Instrux->EfOpMode];
+ }
+ break;
+
+ case ND_OPS_12:
+ // SAVPREVSSP instruction reads/writes 4 + 8 bytes from the shadow stack.
+ size = 12;
+ break;
+
+ case ND_OPS_t:
+ // Tile register. The actual size depends on how the TILECFG register has been programmed, but it can be
+ // up to 1K in size.
+ size = ND_SIZE_1KB;
+ break;
+
+ case ND_OPS_384:
+ // 384 bit Key Locker handle.
+ size = ND_SIZE_384BIT;
+ break;
+
+ case ND_OPS_512:
+ // 512 bit Key Locker handle.
+ size = ND_SIZE_512BIT;
+ break;
+
+ case ND_OPS_4096:
+ // 64 entries x 64 bit per entry = 4096 bit MSR address/value list.
+ size = ND_SIZE_4096BIT;
+ break;
+
+ case ND_OPS_unknown:
+ size = ND_SIZE_UNKNOWN;
+ break;
+
+ default:
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+
+ // Store operand info.
+ operand->Size = size;
+
+ //
+ // Fill in the operand type.
+ //
+ switch (opt)
+ {
+ case ND_OPT_1:
+ // operand is an implicit constant (used by shift/rotate instruction).
+ operand->Type = ND_OP_CONST;
+ operand->Encoding = ND_OPE_1;
+ operand->Info.Constant.Const = 1;
+ break;
+
+ case ND_OPT_rIP:
+ // The operand is the instruction pointer.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_RIP;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = 0;
+ Instrux->RipAccess |= operand->Access.Access;
+ // Fill in branch information.
+ Instrux->BranchInfo.IsBranch = 1;
+ Instrux->BranchInfo.IsConditional = Instrux->Category == ND_CAT_COND_BR;
+ // Indirect branches are those which get their target address from a register or memory, including RET family.
+ Instrux->BranchInfo.IsIndirect = ((!Instrux->Operands[0].Flags.IsDefault) &&
+ ((Instrux->Operands[0].Type == ND_OP_REG) || (Instrux->Operands[0].Type == ND_OP_MEM))) ||
+ (Instrux->Category == ND_CAT_RET);
+ // CS operand is ALWAYS before rIP.
+ Instrux->BranchInfo.IsFar = !!(Instrux->CsAccess & ND_ACCESS_ANY_WRITE);
+ break;
+
+ case ND_OPT_rAX:
+ // Operand is the accumulator.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RAX;
+ break;
+
+ case ND_OPT_AH:
+ // Operand is the accumulator.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = ND_SIZE_8BIT;
+ operand->Info.Register.Reg = NDR_AH;
+ operand->Info.Register.IsHigh8 = ND_TRUE;
+ break;
+
+ case ND_OPT_rCX:
+ // Operand is the counter register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RCX;
+ break;
+
+ case ND_OPT_rDX:
+ // Operand is rDX.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RDX;
+ break;
+
+ case ND_OPT_rBX:
+ // Operand is BX.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RBX;
+ break;
+
+ case ND_OPT_rBP:
+ // Operand is rBP.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RBP;
+ break;
+
+ case ND_OPT_rSP:
+ // Operand is rSP.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RSP;
+ break;
+
+ case ND_OPT_rSI:
+ // Operand is rSI.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RSI;
+ break;
+
+ case ND_OPT_rDI:
+ // Operand is rDI.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_RDI;
+ break;
+
+ case ND_OPT_rR8:
+ // Operand is R8.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_R8;
+ break;
+
+ case ND_OPT_rR9:
+ // Operand is R9.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_R9;
+ break;
+
+ case ND_OPT_rR11:
+ // Operand is R11.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_R11;
+ break;
+
+ case ND_OPT_CS:
+ // Operand is the CS register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SEG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_CS;
+ Instrux->CsAccess |= operand->Access.Access;
+ break;
+
+ case ND_OPT_SS:
+ // Operand is the SS register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SEG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_SS;
+ break;
+
+ case ND_OPT_DS:
+ // Operand is the DS register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SEG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_DS;
+ break;
+
+ case ND_OPT_ES:
+ // Operand is the ES register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SEG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_ES;
+ break;
+
+ case ND_OPT_FS:
+ // Operand is the FS register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SEG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_FS;
+ break;
+
+ case ND_OPT_GS:
+ // Operand is the GS register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SEG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_GS;
+ break;
+
+ case ND_OPT_ST0:
+ // Operand is the ST(0) register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_FPU;
+ operand->Info.Register.Size = ND_SIZE_80BIT;
+ operand->Info.Register.Reg = 0;
+ break;
+
+ case ND_OPT_STi:
+ // Operand is the ST(i) register.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_FPU;
+ operand->Info.Register.Size = ND_SIZE_80BIT;
+ operand->Info.Register.Reg = Instrux->ModRm.rm;
+ break;
+
+ case ND_OPT_XMM0:
+ case ND_OPT_XMM1:
+ case ND_OPT_XMM2:
+ case ND_OPT_XMM3:
+ case ND_OPT_XMM4:
+ case ND_OPT_XMM5:
+ case ND_OPT_XMM6:
+ case ND_OPT_XMM7:
+ // Operand is a hard-coded XMM register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SSE;
+ operand->Info.Register.Size = ND_SIZE_128BIT;
+ operand->Info.Register.Reg = opt - ND_OPT_XMM0;
+ break;
+
+ // Special operands. These are always implicit, and can't be encoded inside the instruction.
+ case ND_OPT_CR0:
+ // The operand is implicit and is control register 0.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_CR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_CR0;
+ break;
+
+ case ND_OPT_GDTR:
+ // The operand is implicit and is the global descriptor table register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SYS;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_GDTR;
+ break;
+
+ case ND_OPT_IDTR:
+ // The operand is implicit and is the interrupt descriptor table register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SYS;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_IDTR;
+ break;
+
+ case ND_OPT_LDTR:
+ // The operand is implicit and is the local descriptor table register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SYS;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_LDTR;
+ break;
+
+ case ND_OPT_TR:
+ // The operand is implicit and is the task register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SYS;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = NDR_TR;
+ break;
+
+ case ND_OPT_X87CONTROL:
+ // The operand is implicit and is the x87 control word.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SYS;
+ operand->Info.Register.Size = ND_SIZE_16BIT;
+ operand->Info.Register.Reg = NDR_X87_CONTROL;
+ break;
+
+ case ND_OPT_X87TAG:
+ // The operand is implicit and is the x87 tag word.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SYS;
+ operand->Info.Register.Size = ND_SIZE_16BIT;
+ operand->Info.Register.Reg = NDR_X87_TAG;
+ break;
+
+ case ND_OPT_X87STATUS:
+ // The operand is implicit and is the x87 status word.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SYS;
+ operand->Info.Register.Size = ND_SIZE_16BIT;
+ operand->Info.Register.Reg = NDR_X87_STATUS;
+ break;
+
+ case ND_OPT_MXCSR:
+ // The operand is implicit and is the MXCSR.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MXCSR;
+ operand->Info.Register.Size = ND_SIZE_32BIT;
+ operand->Info.Register.Reg = 0;
+ break;
+
+ case ND_OPT_PKRU:
+ // The operand is the PKRU register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_PKRU;
+ operand->Info.Register.Size = ND_SIZE_32BIT;
+ operand->Info.Register.Reg = 0;
+ break;
+
+ case ND_OPT_SSP:
+ // The operand is the SSP register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_SSP;
+ operand->Info.Register.Size = operand->Size;
+ operand->Info.Register.Reg = 0;
+ break;
+
+ case ND_OPT_UIF:
+ // The operand is the User Interrupt Flag.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_UIF;
+ operand->Info.Register.Size = ND_SIZE_8BIT; // 1 bit, in fact, but there is no size defined for one bit.
+ operand->Info.Register.Reg = 0;
+ break;
+
+ case ND_OPT_MSR:
+ // The operand is implicit and is a MSR (usually selected by the ECX register).
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_E;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = 0xFFFFFFFF;
+ break;
+
+ case ND_OPT_TSC:
+ // The operand is implicit and is the IA32_TSC.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_TSC;
+ break;
+
+ case ND_OPT_TSCAUX:
+ // The operand is implicit and is the IA32_TSCAUX.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_TSC_AUX;
+ break;
+
+ case ND_OPT_SCS:
+ // The operand is implicit and is the IA32_SYSENTER_CS.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_SYSENTER_CS;
+ break;
+
+ case ND_OPT_SESP:
+ // The operand is implicit and is the IA32_SYSENTER_ESP.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_SYSENTER_ESP;
+ break;
+
+ case ND_OPT_SEIP:
+ // The operand is implicit and is the IA32_SYSENTER_EIP.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_SYSENTER_EIP;
+ break;
+
+ case ND_OPT_STAR:
+ // The operand is implicit and is the IA32_STAR.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_STAR;
+ break;
+
+ case ND_OPT_LSTAR:
+ // The operand is implicit and is the IA32_LSTAR.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_LSTAR;
+ break;
+
+ case ND_OPT_FMASK:
+ // The operand is implicit and is the IA32_FMASK.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_FMASK;
+ break;
+
+ case ND_OPT_FSBASE:
+ // The operand is implicit and is the IA32_FS_BASE MSR.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_FS_BASE;
+ break;
+
+ case ND_OPT_GSBASE:
+ // The operand is implicit and is the IA32_GS_BASE MSR.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_GS_BASE;
+ break;
+
+ case ND_OPT_KGSBASE:
+ // The operand is implicit and is the IA32_KERNEL_GS_BASE MSR.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_MSR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = NDR_IA32_KERNEL_GS_BASE;
+ break;
+
+ case ND_OPT_XCR:
+ // The operand is implicit and is an extended control register (usually selected by ECX register).
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_E;
+ operand->Info.Register.Type = ND_REG_XCR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = 0xFF;
+ break;
+
+ case ND_OPT_XCR0:
+ // The operand is implicit and is XCR0.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_XCR;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = 0;
+ break;
+
+ case ND_OPT_BANK:
+ // Multiple registers are accessed.
+ if ((Instrux->Instruction == ND_INS_PUSHA) || (Instrux->Instruction == ND_INS_POPA))
+ {
+ operand->Type = ND_OP_REG;
+ operand->Size = Instrux->WordLength;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = Instrux->WordLength;
+ operand->Info.Register.Reg = NDR_EAX;
+ operand->Info.Register.Count = 8;
+ operand->Info.Register.IsBlock = ND_TRUE;
+ }
+ else
+ {
+ operand->Type = ND_OP_BANK;
+ }
+ break;
+
+ case ND_OPT_A:
+ // Fetch the address. NOTE: The size can't be larger than 8 bytes.
+ if (ops == ND_OPS_p)
+ {
+ status = NdFetchAddressFar(Instrux, Code, Offset, Size, (ND_UINT8)size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // Fill in operand info.
+ operand->Type = ND_OP_ADDR_FAR;
+ operand->Encoding = ND_OPE_D;
+ operand->Info.Address.BaseSeg = Instrux->Address.Cs;
+ operand->Info.Address.Offset = Instrux->Address.Ip;
+ }
+ else
+ {
+ status = NdFetchAddressNear(Instrux, Code, Offset, Size, (ND_UINT8)size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // Fill in operand info.
+ operand->Type = ND_OP_ADDR_NEAR;
+ operand->Encoding = ND_OPE_D;
+ operand->Info.AddressNear.Target = Instrux->AddressNear;
+ }
+ break;
+
+ case ND_OPT_B:
+ // General purpose register encoded in VEX.vvvv field.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_V;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)Instrux->Exs.v;
+
+ // EVEX.V' must be 0, if a GPR is encoded using EVEX encoding.
+ if (Instrux->Exs.vp != 0)
+ {
+ // If APX is present, V' can be used to extend the GPR to R16-R31.
+ // Otherwise, #UD is triggered.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.vp << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ break;
+
+ case ND_OPT_C:
+ // Control register, encoded in modrm.reg.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_CR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (Instrux->Exs.rp << 4) | (Instrux->Exs.r << 3) | Instrux->ModRm.reg;
+
+ // On some AMD processors, the presence of the LOCK prefix before MOV to/from control registers allows accessing
+ // higher 8 control registers.
+ if ((ND_CODE_64 != Instrux->DefCode) && (Instrux->HasLock))
+ {
+ operand->Info.Register.Reg |= 0x8;
+ }
+
+ // Only CR0, CR2, CR3, CR4 & CR8 valid.
+ if (operand->Info.Register.Reg != 0 &&
+ operand->Info.Register.Reg != 2 &&
+ operand->Info.Register.Reg != 3 &&
+ operand->Info.Register.Reg != 4 &&
+ operand->Info.Register.Reg != 8)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_D:
+ // Debug register, encoded in modrm.reg.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_DR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (Instrux->Exs.rp << 4) | (Instrux->Exs.r << 3) | Instrux->ModRm.reg;
+
+ // Only DR0-DR7 valid.
+ if (operand->Info.Register.Reg >= 8)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_T:
+ // Test register, encoded in modrm.reg.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_TR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+
+ // Only TR0-TR7 valid, only on 486.
+ if (operand->Info.Register.Reg >= 8)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_S:
+ // Segment register, encoded in modrm.reg.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_SEG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+
+ // When addressing segment registers, any extension field (REX.R, REX2.R3, REX2.R4) is ignored.
+ operand->Info.Register.Reg = Instrux->ModRm.reg;
+
+ // Only ES, CS, SS, DS, FS, GS valid.
+ if (operand->Info.Register.Reg >= 6)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ // If CS is loaded - #UD.
+ if ((operand->Info.Register.Reg == NDR_CS) && operand->Access.Write)
+ {
+ return ND_STATUS_CS_LOAD;
+ }
+
+ break;
+
+ case ND_OPT_E:
+ // General purpose register or memory, encoded in modrm.rm.
+ if (Instrux->ModRm.mod != 3)
+ {
+ goto memory;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm;
+
+ // If APX is present, use B4 as well.
+ if (Instrux->Exs.b4 != 0)
+ {
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
+ (operand->Info.Register.Reg >= 4) &&
+ (ND_ENCM_LEGACY == Instrux->EncMode) &&
+ !Instrux->HasRex && !Instrux->HasRex2;
+ break;
+
+ case ND_OPT_F:
+ // The flags register.
+ operand->Type = ND_OP_REG;
+ operand->Info.Register.Type = ND_REG_FLG;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = 0;
+ Instrux->RflAccess |= operand->Access.Access;
+ break;
+
+ case ND_OPT_K:
+ // The operand is the stack.
+ {
+ static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.IsStack = ND_TRUE;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.Base = NDR_RSP;
+ operand->Info.Memory.BaseSize = szLut[Instrux->DefStack];
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NDR_SS;
+ Instrux->StackWords = (ND_UINT8)(operand->Size / Instrux->WordLength);
+ Instrux->StackAccess |= operand->Access.Access;
+ }
+ break;
+
+ case ND_OPT_G:
+ // General purpose register encoded in modrm.reg.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg;
+
+ if (Instrux->Exs.rp != 0)
+ {
+ // If APX is present, use R' (R4) to extent the register to 5 bits.
+ // Otherwise, generate #UD.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.rp << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
+ (operand->Info.Register.Reg >= 4) &&
+ (ND_ENCM_LEGACY == Instrux->EncMode) &&
+ !Instrux->HasRex && !Instrux->HasRex2;
+ break;
+
+ case ND_OPT_R:
+ // General purpose register encoded in modrm.rm.
+ if ((Instrux->ModRm.mod != 3) && (0 == (Instrux->Attributes & ND_FLAG_MFR)))
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm;
+
+ if (Instrux->Exs.b4 != 0)
+ {
+ // If APX is present, use B4 as well.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
+ (operand->Info.Register.Reg >= 4) &&
+ (ND_ENCM_LEGACY == Instrux->EncMode) &&
+ !Instrux->HasRex && !Instrux->HasRex2;
+ break;
+
+ case ND_OPT_I:
+ // Immediate, encoded in instructon bytes.
+ {
+ ND_UINT64 imm;
+
+ // Fetch the immediate. NOTE: The size won't exceed 8 bytes.
+ status = NdFetchImmediate(Instrux, Code, Offset, Size, (ND_UINT8)size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // Get the last immediate.
+ if (Instrux->HasImm2)
+ {
+ imm = Instrux->Immediate2;
+ }
+ else
+ {
+ imm = Instrux->Immediate1;
+ }
+
+ operand->Type = ND_OP_IMM;
+ operand->Encoding = ND_OPE_I;
+ operand->Info.Immediate.RawSize = (ND_UINT8)size;
+
+ if (operand->Flags.SignExtendedDws)
+ {
+ static const ND_UINT8 wszLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+
+ // Get the default word size: the immediate is sign extended to the default word size.
+ operand->Size = wszLut[Instrux->EfOpMode];
+
+ operand->Info.Immediate.Imm = ND_SIGN_EX(size, imm);
+ }
+ else if (operand->Flags.SignExtendedOp1)
+ {
+ // The immediate is sign extended to the size of the first operand.
+ operand->Size = Instrux->Operands[0].Size;
+
+ operand->Info.Immediate.Imm = ND_SIGN_EX(size, imm);
+ }
+ else
+ {
+ operand->Info.Immediate.Imm = imm;
+ }
+ }
+ break;
+
+ case ND_OPT_m2zI:
+ operand->Type = ND_OP_IMM;
+ operand->Encoding = ND_OPE_L;
+ operand->Info.Immediate.Imm = Instrux->SseImmediate & 3;
+ operand->Info.Immediate.RawSize = (ND_UINT8)size;
+ break;
+
+ case ND_OPT_J:
+ // Fetch the relative offset. NOTE: The size of the relative can't exceed 4 bytes.
+ status = NdFetchRelativeOffset(Instrux, Code, Offset, Size, (ND_UINT8)size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // The instruction is RIP relative.
+ Instrux->IsRipRelative = ND_TRUE;
+
+ operand->Type = ND_OP_OFFS;
+ operand->Encoding = ND_OPE_D;
+ // The relative offset is forced to the default word length. Care must be taken with the 32 bit
+ // branches that have 0x66 prefix (in 32 bit mode)!
+ operand->Size = Instrux->WordLength;
+ operand->Info.RelativeOffset.Rel = ND_SIGN_EX(size, Instrux->RelativeOffset);
+ operand->Info.RelativeOffset.RawSize = (ND_UINT8)size;
+
+ break;
+
+ case ND_OPT_N:
+ // The R/M field of the ModR/M byte selects a packed-quadword, MMX technology register.
+ if (Instrux->ModRm.mod != 3)
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_MMX;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = Instrux->ModRm.rm;
+ break;
+
+ case ND_OPT_P:
+ // The reg field of the ModR/M byte selects a packed quadword MMX technology register.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_MMX;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = Instrux->ModRm.reg;
+ break;
+
+ case ND_OPT_Q:
+ // The rm field inside Mod R/M encodes a MMX register or memory.
+ if (Instrux->ModRm.mod != 3)
+ {
+ goto memory;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_MMX;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = Instrux->ModRm.rm;
+ break;
+
+ case ND_OPT_O:
+ // Absolute address, encoded in instruction bytes.
+ // NOTE: The moffset len can't exceed 8 bytes.
+ status = NdFetchMoffset(Instrux, Code, Offset, Size, 2 << Instrux->AddrMode);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // operand info.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Encoding = ND_OPE_D;
+ operand->Info.Memory.HasDisp = ND_TRUE;
+ operand->Info.Memory.IsDirect = ND_TRUE;
+ operand->Info.Memory.DispSize = Instrux->MoffsetLength;
+ operand->Info.Memory.Disp = Instrux->Moffset;
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
+ break;
+
+ case ND_OPT_M:
+ // Modrm based memory addressing.
+ if (Instrux->ModRm.mod == 3)
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+memory:
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Memory.HasSeg = ND_TRUE;
+
+ // Parse mode specific memory information.
+ if (ND_ADDR_16 != Instrux->AddrMode)
+ {
+ status = NdParseMemoryOperand3264(Instrux, operand, vsibRegSize);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+ else
+ {
+ status = NdParseMemoryOperand16(Instrux, operand);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+
+ // Get the segment. Note that in long mode, segment prefixes are ignored, except for FS and GS.
+ if (Instrux->HasSeg)
+ {
+ operand->Info.Memory.Seg = NdGetSegOverride(Instrux, operand->Info.Memory.Seg);
+ }
+
+ // Handle VSIB addressing.
+ if (ND_HAS_VSIB(Instrux))
+ {
+ // VSIB requires SIB.
+ if (!Instrux->HasSib)
+ {
+ return ND_STATUS_VSIB_WITHOUT_SIB;
+ }
+
+ operand->Info.Memory.IsVsib = ND_TRUE;
+
+ operand->Info.Memory.Vsib.IndexSize = vsibIndexSize;
+ operand->Info.Memory.Vsib.ElemCount = vsibIndexCount;
+ operand->Info.Memory.Vsib.ElemSize = (ND_UINT8)(size / vsibIndexCount);
+ }
+
+ // Handle sibmem addressing, as used by Intel AMX instructions.
+ if (ND_HAS_SIBMEM(Instrux))
+ {
+ // sibmem requires SIB to be present.
+ if (!Instrux->HasSib)
+ {
+ return ND_STATUS_SIBMEM_WITHOUT_SIB;
+ }
+
+ operand->Info.Memory.IsSibMem = ND_TRUE;
+ }
+
+ // If we have broadcast, the operand size is fixed to either 16, 32 or 64 bit, depending on bcast size.
+ // Therefore, we will override the rawSize with either 16, 32 or 64 bits. Note that bcstSize will save the
+ // total size of the access, and it will be used to compute the number of broadcasted elements:
+ // bcstSize / rawSize.
+ if (Instrux->HasBroadcast)
+ {
+ ND_OPERAND_SIZE bcstSize = size;
+ operand->Info.Memory.HasBroadcast = ND_TRUE;
+
+ if (opd & ND_OPD_B32)
+ {
+ size = ND_SIZE_32BIT;
+ }
+ else if (opd & ND_OPD_B64)
+ {
+ size = ND_SIZE_64BIT;
+ }
+ else if (opd & ND_OPD_B16)
+ {
+ size = ND_SIZE_16BIT;
+ }
+ else
+ {
+ size = width ? ND_SIZE_64BIT : ND_SIZE_32BIT;
+ }
+
+ // Override operand size.
+ operand->Size = size;
+
+ operand->Info.Memory.Broadcast.Size = (ND_UINT8)operand->Size;
+ operand->Info.Memory.Broadcast.Count = (ND_UINT8)(bcstSize / operand->Size);
+ }
+
+ // Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement
+ // use compressed displacement addressing.
+ if (Instrux->HasCompDisp)
+ {
+ operand->Info.Memory.HasCompDisp = ND_TRUE;
+ operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size);
+ }
+
+ // MIB, if any. Used by some MPX instructions.
+ operand->Info.Memory.IsMib = ND_HAS_MIB(Instrux);
+
+ // Bitbase, if any. Used by BT* instructions when the first op is mem and the second one reg.
+ operand->Info.Memory.IsBitbase = ND_HAS_BITBASE(Instrux);
+
+ // AG, if this is the case.
+ if (ND_HAS_AG(Instrux))
+ {
+ operand->Info.Memory.IsAG = ND_TRUE;
+
+ // Address generation instructions ignore the segment prefixes. Examples are LEA and MPX instructions.
+ operand->Info.Memory.HasSeg = ND_FALSE;
+ operand->Info.Memory.Seg = 0;
+ }
+
+ // Shadow Stack Access, if this is the case.
+ if (ND_HAS_SHS(Instrux))
+ {
+ operand->Info.Memory.IsShadowStack = ND_TRUE;
+ operand->Info.Memory.ShStkType = ND_SHSTK_EXPLICIT;
+ }
+
+ break;
+
+
+ case ND_OPT_H:
+ // Vector register, encoded in VEX/EVEX.vvvv.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_V;
+ operand->Info.Register.Type = ND_REG_SSE;
+ operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
+ // V' will be 0 for any non-EVEX encoded instruction.
+ operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.vp << 4) | Instrux->Exs.v);
+ break;
+
+ case ND_OPT_L:
+ // Vector register, encoded in immediate.
+ status = NdFetchSseImmediate(Instrux, Code, Offset, Size, 1);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_L;
+ operand->Info.Register.Type = ND_REG_SSE;
+ operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
+ operand->Info.Register.Reg = (Instrux->SseImmediate >> 4) & 0xF;
+
+ if (Instrux->DefCode != ND_CODE_64)
+ {
+ operand->Info.Register.Reg &= 0x7;
+ }
+
+ break;
+
+ case ND_OPT_U:
+ // Vector register encoded in modrm.rm.
+ if (Instrux->ModRm.mod != 3)
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_SSE;
+ operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
+ operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+
+ if (Instrux->HasEvex)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.x << 4;
+ }
+
+ break;
+
+ case ND_OPT_V:
+ // Vector register encoded in modrm.reg.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_SSE;
+ operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
+ operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+
+ if (Instrux->HasEvex)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.rp << 4;
+ }
+
+ break;
+
+ case ND_OPT_W:
+ // Vector register or memory encoded in modrm.rm.
+ if (Instrux->ModRm.mod != 3)
+ {
+ goto memory;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_SSE;
+ operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
+ operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+
+ // For vector registers, the X extension bit is used to extend the register to 5 bits.
+ if (Instrux->HasEvex)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.x << 4;
+ }
+
+ break;
+
+ case ND_OPT_X:
+ case ND_OPT_Y:
+ case ND_OPT_pDI:
+ // RSI/RDI based addressing, as used by string instructions.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Base = (ND_UINT8)(((opt == ND_OPT_X) ? NDR_RSI : NDR_RDI));
+ operand->Info.Memory.IsString = (ND_OPT_X == opt || ND_OPT_Y == opt);
+ // DS:rSI supports segment overriding. ES:rDI does not.
+ if (opt == ND_OPT_Y)
+ {
+ operand->Info.Memory.Seg = NDR_ES;
+ }
+ else
+ {
+ operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
+ }
+ break;
+
+ case ND_OPT_pBXAL:
+ // [rBX + AL], used by XLAT.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.HasIndex = ND_TRUE;
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.IndexSize = ND_SIZE_8BIT; // Always 1 Byte.
+ operand->Info.Memory.Base = NDR_RBX; // Always rBX.
+ operand->Info.Memory.Index = NDR_AL; // Always AL.
+ operand->Info.Memory.Scale = 1; // Always 1.
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
+ break;
+
+ case ND_OPT_pAX:
+ // [rAX], used implicitly by MONITOR, MONITORX and RMPADJUST instructions.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.Base = NDR_RAX; // Always rAX.
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
+ break;
+
+ case ND_OPT_pCX:
+ // [rCX], used implicitly by RMPUPDATE.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.Base = NDR_RCX; // Always rCX.
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
+ break;
+
+ case ND_OPT_pBP:
+ // [sBP], used implicitly by ENTER, when nesting level is > 1.
+ // Operand size bytes accessed from memory. Base reg size determined by stack address size attribute.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.BaseSize = 2 << Instrux->DefStack;
+ operand->Info.Memory.Base = NDR_RBP; // Always rBP.
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NDR_SS;
+ break;
+
+ case ND_OPT_SHS:
+ // Shadow stack access using the current SSP.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.IsShadowStack = ND_TRUE;
+ operand->Info.Memory.ShStkType = ND_SHSTK_SSP_LD_ST;
+ break;
+
+ case ND_OPT_SHS0:
+ // Shadow stack access using the IA32_PL0_SSP.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.IsShadowStack = ND_TRUE;
+ operand->Info.Memory.ShStkType = ND_SHSTK_PL0_SSP;
+ break;
+
+ case ND_OPT_SMT:
+ // Table of MSR addresses, encoded in [RSI].
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.Base = NDR_RSI; // Always rSI.
+ operand->Info.Memory.HasSeg = ND_FALSE; // Linear Address directly, only useable in 64 bit mode.
+ break;
+
+ case ND_OPT_DMT:
+ // Table of MSR addresses, encoded in [RDI].
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.Base = NDR_RDI; // Always rDI.
+ operand->Info.Memory.HasSeg = ND_FALSE; // Linear Address directly, only useable in 64 bit mode.
+ break;
+
+ case ND_OPT_SHSP:
+ // Shadow stack push/pop access.
+ Instrux->MemoryAccess |= operand->Access.Access;
+ operand->Type = ND_OP_MEM;
+ operand->Info.Memory.IsShadowStack = ND_TRUE;
+ operand->Info.Memory.ShStkType = ND_SHSTK_SSP_PUSH_POP;
+ break;
+
+ case ND_OPT_Z:
+ // A GPR Register is selected by the low 3 bits inside the opcode. REX.B can be used to extend it.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_O;
+ operand->Info.Register.Type = ND_REG_GPR;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7);
+
+ if (Instrux->Exs.b4 != 0)
+ {
+ // If APX is present, extend the register.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
+ (operand->Info.Register.Reg >= 4) &&
+ (ND_ENCM_LEGACY == Instrux->EncMode) &&
+ !Instrux->HasRex && !Instrux->HasRex2;
+ break;
+
+ case ND_OPT_rB:
+ // reg inside modrm selects a BND register.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_BND;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+
+ if (operand->Info.Register.Reg >= 4)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_mB:
+ // rm inside modrm selects either a BND register, either memory.
+ if (Instrux->ModRm.mod != 3)
+ {
+ goto memory;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_BND;
+ operand->Info.Register.Size = (ND_REG_SIZE)size;
+ operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+
+ if (operand->Info.Register.Reg >= 4)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_rK:
+ // reg inside modrm selects a mask register.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_MSK;
+
+ // Opcode dependent #UD, R and R' must be zero (1 actually, but they're inverted).
+ if ((Instrux->Exs.r != 0) || (Instrux->Exs.rp != 0))
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = (ND_UINT8)(Instrux->ModRm.reg);
+ break;
+
+ case ND_OPT_vK:
+ // vex.vvvv selects a mask register.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_V;
+ operand->Info.Register.Type = ND_REG_MSK;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = (ND_UINT8)Instrux->Exs.v;
+
+ if (operand->Info.Register.Reg >= 8)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_mK:
+ // rm inside modrm selects either a mask register, either memory.
+ if (Instrux->ModRm.mod != 3)
+ {
+ goto memory;
+ }
+
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_MSK;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ // X and B are ignored when Msk registers are being addressed.
+ operand->Info.Register.Reg = Instrux->ModRm.rm;
+ break;
+
+ case ND_OPT_aK:
+ // aaa inside evex selects either a mask register, which is used for masking a destination operand.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_A;
+ operand->Info.Register.Type = ND_REG_MSK;
+ operand->Info.Register.Size = ND_SIZE_64BIT;
+ operand->Info.Register.Reg = Instrux->Exs.k;
+ break;
+
+ case ND_OPT_rM:
+ // Sigh. reg field inside mod r/m encodes memory. This encoding is used by MOVDIR64b and ENQCMD instructions.
+ // When the ModR/M.reg field is used to select a memory operand, the following apply:
+ // - The ES segment register is used as a base
+ // - The ES segment register cannot be overridden
+ // - The size of the base register is selected by the address size, not the operand size.
+ operand->Type = ND_OP_MEM;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
+
+ if (Instrux->Exs.rp != 0)
+ {
+ // If APX is present, extend the base register.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ operand->Info.Memory.Base |= Instrux->Exs.rp << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NDR_ES;
+ break;
+
+ case ND_OPT_mM:
+ // Sigh. rm field inside mod r/m encodes memory, even if mod is 3.
+ operand->Type = ND_OP_MEM;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Memory.HasBase = ND_TRUE;
+ operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
+
+ if (Instrux->Exs.b4 != 0)
+ {
+ // If APX is present, extend the base register.
+ if (Instrux->FeatMode & ND_FEAT_APX)
+ {
+ operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
+ }
+ else
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+ }
+
+ operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
+ operand->Info.Memory.HasSeg = ND_TRUE;
+ operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
+ break;
+
+ case ND_OPT_rT:
+ // Tile register encoded in ModR/M.reg field.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_R;
+ operand->Info.Register.Type = ND_REG_TILE;
+ operand->Info.Register.Size = size;
+ operand->Info.Register.Reg = Instrux->ModRm.reg;
+
+ // #UD if a tile register > 7 is encoded.
+ if (Instrux->Exs.r != 0 || Instrux->Exs.rp != 0)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_mT:
+ // Tile register encoded in ModR/M.rm field.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_M;
+ operand->Info.Register.Type = ND_REG_TILE;
+ operand->Info.Register.Size = size;
+ operand->Info.Register.Reg = Instrux->ModRm.rm;
+
+ // #UD if a tile register > 7 is encoded.
+ if (Instrux->Exs.b != 0 || Instrux->Exs.b4 != 0)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_vT:
+ // Tile register encoded in vex.vvvv field.
+ operand->Type = ND_OP_REG;
+ operand->Encoding = ND_OPE_V;
+ operand->Info.Register.Type = ND_REG_TILE;
+ operand->Info.Register.Size = size;
+ operand->Info.Register.Reg = Instrux->Exs.v;
+
+ // #UD if a tile register > 7 is encoded.
+ if (operand->Info.Register.Reg > 7 || Instrux->Exs.vp != 0)
+ {
+ return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
+ }
+
+ break;
+
+ case ND_OPT_dfv:
+ // Default flags value encoded in vex.vvvv field.
+ operand->Type = ND_OP_DFV;
+ operand->Encoding = ND_OPE_V;
+ operand->Info.DefaultFlags.CF = (Instrux->Exs.v >> 0) & 1;
+ operand->Info.DefaultFlags.ZF = (Instrux->Exs.v >> 1) & 1;
+ operand->Info.DefaultFlags.SF = (Instrux->Exs.v >> 2) & 1;
+ operand->Info.DefaultFlags.OF = (Instrux->Exs.v >> 3) & 1;
+ operand->Size = 0;
+ break;
+
+ default:
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+
+ if (operand->Type == ND_OP_REG)
+ {
+ // Handle block addressing - used by AVX512_4FMAPS and AVX512_4VNNIW instructions. Also used by VP2INTERSECTD/Q
+ // instructions. Also note that in block addressing, the base of the block is masked using the size of the block;
+ // for example, for a block size of 1, the first register must be even; For a block size of 4, the first register
+ // must be divisible by 4.
+ if (opb != 0)
+ {
+ operand->Info.Register.Count = opb;
+ operand->Info.Register.Reg &= (ND_UINT32)~(opb - 1);
+ operand->Info.Register.IsBlock = ND_TRUE;
+ }
+ else
+ {
+ operand->Info.Register.Count = 1;
+ }
+
+ // Handle zero-upper semantic for destination operands. Applies to destination registers only.
+ if ((Instrux->HasNd || Instrux->HasZu) && operand->Access.Write && !operand->Flags.IsDefault)
+ {
+ operand->Info.Register.IsZeroUpper = 1;
+ }
+ }
+
+ // Handle decorators. Note that only Mask, Zero and Broadcast are stored per-operand.
+ if (0 != opd)
+ {
+ // Check for mask register. Mask if present only if the operand supports masking and if the
+ // mask register is not k0 (which implies "no masking").
+ if ((opd & ND_OPD_MASK) && (Instrux->HasMask))
+ {
+ operand->Decorator.HasMask = ND_TRUE;
+ operand->Decorator.Msk = (ND_UINT8)Instrux->Exs.k;
+ }
+
+ // Check for zeroing. The operand must support zeroing and the z bit inside evex3 must be set. Note that
+ // zeroing is allowed only for register destinations, and NOT for memory.
+ if ((opd & ND_OPD_ZERO) && (Instrux->HasZero))
+ {
+ if (operand->Type == ND_OP_MEM)
+ {
+ return ND_STATUS_ZEROING_ON_MEMORY;
+ }
+
+ operand->Decorator.HasZero = ND_TRUE;
+ }
+
+ // Check for broadcast again. We've already filled the broadcast size before parsing the op size.
+ if ((opd & ND_OPD_BCAST) && (Instrux->HasBroadcast))
+ {
+ operand->Decorator.HasBroadcast = ND_TRUE;
+ }
+ }
+
+ return status;
+}
+
+
+//
+// NdFindInstruction
+//
+static NDSTATUS
+NdFindInstruction(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_SIZET Size,
+ ND_IDBE **InsDef
+ )
+{
+ NDSTATUS status;
+ const ND_TABLE *pTable;
+ ND_IDBE *pIns;
+ ND_BOOL stop, redf2, redf3;
+ ND_UINT32 nextOpcode;
+
+ // pre-init
+ status = ND_STATUS_SUCCESS;
+ pIns = (ND_IDBE *)ND_NULL;
+ stop = ND_FALSE;
+ nextOpcode = 0;
+ redf2 = redf3 = ND_FALSE;
+
+ switch (Instrux->EncMode)
+ {
+ case ND_ENCM_LEGACY:
+ if (Instrux->Rex2.m0 == 1)
+ {
+ // Legacy map ID 1.
+ pTable = (const ND_TABLE*)gLegacyMap_opcode.Table[0x0F];
+ }
+ else
+ {
+ // Legacy map ID 0.
+ pTable = (const ND_TABLE*)&gLegacyMap_opcode;
+ }
+ break;
+ case ND_ENCM_XOP:
+ pTable = (const ND_TABLE *)gXopMap_mmmmm.Table[Instrux->Exs.m];
+ break;
+ case ND_ENCM_VEX:
+ pTable = (const ND_TABLE *)gVexMap_mmmmm.Table[Instrux->Exs.m];
+ break;
+ case ND_ENCM_EVEX:
+ pTable = (const ND_TABLE *)gEvexMap_mmmmm.Table[Instrux->Exs.m];
+ break;
+ default:
+ pTable = (const ND_TABLE *)ND_NULL;
+ break;
+ }
+
+ while ((!stop) && (ND_NULL != pTable))
+ {
+ switch (pTable->Type)
+ {
+ case ND_ILUT_INSTRUCTION:
+ // We've found the leaf entry, which is an instruction - we can leave.
+ pIns = (ND_IDBE *)(((ND_TABLE_INSTRUCTION *)pTable)->Instruction);
+ stop = ND_TRUE;
+ break;
+
+ case ND_ILUT_OPCODE:
+ // We need an opcode to keep going.
+ status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ stop = ND_TRUE;
+ break;
+ }
+
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]];
+ break;
+
+ case ND_ILUT_OPCODE_LAST:
+ // We need an opcode to select the next table, but the opcode is AFTER the modrm/sib/displacement.
+ if (!Instrux->HasModRm)
+ {
+ // Fetch modrm, SIB & displacement
+ status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ stop = ND_TRUE;
+ break;
+ }
+ }
+
+ // Fetch the opcode, which is after the modrm and displacement.
+ status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ stop = ND_TRUE;
+ break;
+ }
+
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]];
+ break;
+
+ case ND_ILUT_MODRM_MOD:
+ // We need modrm.mod to select the next table.
+ if (!Instrux->HasModRm)
+ {
+ // Fetch modrm, SIB & displacement
+ status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ stop = ND_TRUE;
+ break;
+ }
+ }
+
+ // Next index is either 0 (mem) or 1 (reg)
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.mod == 3 ? 1 : 0];
+ break;
+
+ case ND_ILUT_MODRM_REG:
+ // We need modrm.reg to select the next table.
+ if (!Instrux->HasModRm)
+ {
+ // Fetch modrm, SIB & displacement
+ status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ stop = ND_TRUE;
+ break;
+ }
+ }
+
+ // Next index is the reg.
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.reg];
+ break;
+
+ case ND_ILUT_MODRM_RM:
+ // We need modrm.rm to select the next table.
+ if (!Instrux->HasModRm)
+ {
+ // Fetch modrm, SIB & displacement
+ status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ stop = ND_TRUE;
+ break;
+ }
+ }
+
+ // Next index is the rm.
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.rm];
+ break;
+
+ case ND_ILUT_MAN_PREFIX:
+ // We have mandatory prefixes.
+ if ((Instrux->Rep == 0xF2) && !redf2)
+ {
+ // We can only redirect once through one mandatory prefix, otherwise we may
+ // enter an infinite loop (see CRC32 Gw Eb -> 0x66 0xF2 0x0F ...)
+ redf2 = ND_TRUE;
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_F2];
+ Instrux->HasMandatoryF2 = ND_TRUE;
+ }
+ else if ((Instrux->Rep == 0xF3) && !redf3)
+ {
+ redf3 = ND_TRUE;
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_F3];
+ Instrux->HasMandatoryF3 = ND_TRUE;
+ }
+ else if (Instrux->HasOpSize)
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_66];
+ Instrux->HasMandatory66 = ND_TRUE;
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_NP];
+ }
+ break;
+
+ case ND_ILUT_MODE:
+ if (ND_NULL != pTable->Table[Instrux->DefCode + 1])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->DefCode + 1];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MODE_NONE];
+ }
+ break;
+
+ case ND_ILUT_DSIZE:
+ // Handle default/forced redirections in 64 bit mode.
+ if (ND_CODE_64 == Instrux->DefCode)
+ {
+ // 64-bit mode, we may have forced/default operand sizes.
+ if ((ND_NULL != pTable->Table[4]) && (!Instrux->HasOpSize || Instrux->Exs.w))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[4];
+ }
+ else if (ND_NULL != pTable->Table[5])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[5];
+ }
+ else if (ND_NULL != pTable->Table[Instrux->OpMode + 1])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->OpMode + 1];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_DSIZE_NONE];
+ }
+ }
+ else if (ND_NULL != pTable->Table[Instrux->OpMode + 1])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->OpMode + 1];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_DSIZE_NONE];
+ }
+ break;
+
+ case ND_ILUT_ASIZE:
+ if (ND_NULL != pTable->Table[Instrux->AddrMode + 1])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->AddrMode + 1];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_ASIZE_NONE];
+ }
+ break;
+
+ case ND_ILUT_AUXILIARY:
+ // Auxiliary redirection. Default to table[0] if nothing matches.
+ if ((Instrux->Exs.b || Instrux->Exs.b4) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXB]))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REXB];
+ }
+ else if (Instrux->Exs.w && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW]))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REXW];
+ }
+ else if ((Instrux->DefCode == ND_CODE_64) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_MO64]))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_MO64];
+ }
+ else if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REPZ]))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REPZ];
+ }
+ else if ((Instrux->Rep != 0) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REP]))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REP];
+ }
+ else if (Instrux->DefCode == ND_CODE_64 && Instrux->HasModRm &&
+ Instrux->ModRm.mod == 0 && Instrux->ModRm.rm == NDR_RBP &&
+ ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_RIPREL])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_RIPREL];
+ }
+ else if (Instrux->HasRex2 && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REX2]))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REX2];
+ }
+ else if (Instrux->HasRex2 && Instrux->Rex2.w && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REX2W]))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REX2W];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_NONE];
+ }
+ break;
+
+ case ND_ILUT_VENDOR:
+ // Vendor redirection. Go to the vendor specific entry.
+ if (ND_NULL != pTable->Table[Instrux->VendMode])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->VendMode];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_VEND_ANY];
+ }
+ break;
+
+ case ND_ILUT_FEATURE:
+ // Feature redirection. Normally NOP if feature is not set, but may be something else if feature is set.
+ if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_MPX]) && !!(Instrux->FeatMode & ND_FEAT_MPX))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_MPX];
+ }
+ else if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_CET]) && !!(Instrux->FeatMode & ND_FEAT_CET))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_CET];
+ }
+ else if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_CLDEMOTE]) && !!(Instrux->FeatMode & ND_FEAT_CLDEMOTE))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_CLDEMOTE];
+ }
+ else if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_PITI]) && !!(Instrux->FeatMode & ND_FEAT_PITI))
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_PITI];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_NONE];
+ }
+ break;
+
+ case ND_ILUT_EX_M:
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.m];
+ break;
+
+ case ND_ILUT_EX_PP:
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.p];
+ break;
+
+ case ND_ILUT_EX_L:
+ if (Instrux->HasEvex && Instrux->Exs.m != 4 && Instrux->Exs.bm)
+ {
+ // We have evex; we need to fetch the modrm now, because we have to make sure we don't have SAE or ER;
+ // if we do have SAE or ER, we have to check the modrm byte and see if it is a reg-reg form (mod = 3),
+ // in which case L'L is forced to the maximum vector length of the instruction. We know for sure that
+ // all EVEX instructions have modrm.
+ // Skip these checks for EVEX map 4, which are legacy instructions promoted to EVEX, and which do not
+ // support SAE, ER or broadcast.
+ if (!Instrux->HasModRm)
+ {
+ // Fetch modrm, SIB & displacement
+ status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ stop = ND_TRUE;
+ break;
+ }
+ }
+
+ if (3 == Instrux->ModRm.mod)
+ {
+ // We use the maximum vector length of the instruction. If the instruction does not support
+ // SAE or ER, a #UD would be generated. We check for this later.
+ if (ND_NULL != pTable->Table[2])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[2];
+ }
+ else if (ND_NULL != pTable->Table[1])
+ {
+ pTable = (const ND_TABLE *)pTable->Table[1];
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[0];
+ }
+ }
+ else
+ {
+ // Mod is mem, we simply use L'L for indexing, as no SAE or ER can be present.
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.l];
+ }
+ }
+ else
+ {
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.l];
+ }
+ break;
+
+ case ND_ILUT_EX_W:
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.w];
+ break;
+
+ case ND_ILUT_EX_WI:
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->DefCode == ND_CODE_64 ? Instrux->Exs.w : 0];
+ break;
+
+ case ND_ILUT_EX_ND:
+ // New data modified field encoded in EVEX payload byte 3.
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.nd];
+ break;
+
+ case ND_ILUT_EX_NF:
+ // No flags modifier field encoded in EVEX payload byte 3.
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.nf];
+ break;
+
+ case ND_ILUT_EX_SC:
+ // Standard condition field encoded in EVEX payload byte 3.
+ pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.sc];
+ break;
+
+ default:
+ status = ND_STATUS_INTERNAL_ERROR;
+ stop = ND_TRUE;
+ break;
+ }
+ }
+
+ // Error - leave now.
+ if (!ND_SUCCESS(status))
+ {
+ goto cleanup_and_exit;
+ }
+
+ // No encoding found - leave now.
+ if (ND_NULL == pIns)
+ {
+ status = ND_STATUS_INVALID_ENCODING;
+ goto cleanup_and_exit;
+ }
+
+ // Bingo! Valid instruction found for the encoding. If Modrm is needed and we didn't fetch it - do it now.
+ if ((pIns->Attributes & ND_FLAG_MODRM) && (!Instrux->HasModRm))
+ {
+ if (0 == (pIns->Attributes & ND_FLAG_MFR))
+ {
+ // Fetch Mod R/M, SIB & displacement.
+ status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ goto cleanup_and_exit;
+ }
+ }
+ else
+ {
+ // Handle special MOV with control and debug registers - the mod is always forced to register. SIB
+ // and displacement is ignored.
+ status = NdFetchModrm(Instrux, Code, Instrux->Length, Size);
+ if (!ND_SUCCESS(status))
+ {
+ goto cleanup_and_exit;
+ }
+ }
+ }
+
+ // Store primary opcode.
+ Instrux->PrimaryOpCode = Instrux->OpCodeBytes[Instrux->OpLength - 1];
+
+ Instrux->MainOpOffset = ND_IS_3DNOW(Instrux) ? Instrux->Length - 1 : Instrux->OpOffset + Instrux->OpLength - 1;
+
+cleanup_and_exit:
+ *InsDef = pIns;
+
+ return status;
+}
+
+
+//
+// NdGetAddrAndOpMode
+//
+static NDSTATUS
+NdGetAddrAndOpMode(
+ INSTRUX *Instrux
+ )
+{
+ // Fill in addressing mode & default op size.
+ switch (Instrux->DefCode)
+ {
+ case ND_CODE_16:
+ Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_16;
+ Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_32 : ND_OPSZ_16;
+ break;
+ case ND_CODE_32:
+ Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_16 : ND_ADDR_32;
+ Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32;
+ break;
+ case ND_CODE_64:
+ Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_64;
+ Instrux->OpMode = Instrux->Exs.w ? ND_OPSZ_64 : (Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32);
+ break;
+ default:
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdGetEffectiveAddrAndOpMode
+//
+static NDSTATUS
+NdGetEffectiveAddrAndOpMode(
+ INSTRUX *Instrux
+ )
+{
+ static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
+ ND_BOOL w64, f64, d64, has66;
+
+ if ((ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64))
+ {
+ // Some instructions ignore VEX/EVEX.W field outside 64 bit mode, and treat it as 0.
+ Instrux->Exs.w = 0;
+ }
+
+ // Extract the flags.
+ w64 = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG);
+
+ // In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored.
+ f64 = 0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD != Instrux->VendMode);
+
+ // In 64 bit mode, the operand defaults to 64 bit. No 32 bit form of the instruction exists. Note that on AMD,
+ // only default 64 bit operands exist, even for branches - no operand is forced to 64 bit.
+ d64 = (0 != (Instrux->Attributes & ND_FLAG_D64)) ||
+ (0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD == Instrux->VendMode));
+
+ // Check if 0x66 is indeed interpreted as a size changing prefix. Note that if 0x66 is a mandatory prefix,
+ // then it won't be interpreted as a size changing prefix. However, there is an exception: MOVBE and CRC32
+ // have mandatory 0xF2, and 0x66 is in fact a size changing prefix.
+ // For legacy instructions promoted to EVEX, in some cases, the compressed prefix pp has the same meaning
+ // as the legacy 0x66 prefix.
+ has66 = (Instrux->HasOpSize && (!Instrux->HasMandatory66 || (Instrux->Attributes & ND_FLAG_S66))) ||
+ ((Instrux->Exs.p == 1) && (Instrux->Attributes & ND_FLAG_SCALABLE));
+
+ // Fill in the effective operand size. Also validate instruction validity in given mode.
+ switch (Instrux->DefCode)
+ {
+ case ND_CODE_16:
+ if (Instrux->Attributes & ND_FLAG_O64)
+ {
+ return ND_STATUS_INVALID_ENCODING_IN_MODE;
+ }
+
+ Instrux->EfOpMode = has66 ? ND_OPSZ_32 : ND_OPSZ_16;
+ break;
+ case ND_CODE_32:
+ if (Instrux->Attributes & ND_FLAG_O64)
+ {
+ return ND_STATUS_INVALID_ENCODING_IN_MODE;
+ }
+
+ Instrux->EfOpMode = has66 ? ND_OPSZ_16 : ND_OPSZ_32;
+ break;
+ case ND_CODE_64:
+ // Make sure instruction valid in mode.
+ if (Instrux->Attributes & ND_FLAG_I64)
+ {
+ return ND_STATUS_INVALID_ENCODING_IN_MODE;
+ }
+
+ Instrux->EfOpMode = (w64 || f64 || (d64 && !has66)) ? ND_OPSZ_64 : (has66 ? ND_OPSZ_16 : ND_OPSZ_32);
+ Instrux->AddrMode = !!(Instrux->Attributes & ND_FLAG_I67) ? ND_ADDR_64 : Instrux->AddrMode;
+ break;
+ default:
+ return ND_STATUS_INVALID_INSTRUX;
+ }
+
+ // Fill in the default word length. It can't be more than 8 bytes.
+ Instrux->WordLength = szLut[Instrux->EfOpMode];
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdGetVectorLength
+//
+static NDSTATUS
+NdGetVectorLength(
+ INSTRUX *Instrux
+ )
+{
+ if (Instrux->HasEr || Instrux->HasSae || Instrux->HasIgnEr)
+ {
+ // Embedded rounding or SAE present, force the vector length to 512 or scalar.
+ if ((Instrux->TupleType == ND_TUPLE_T1S) ||
+ (Instrux->TupleType == ND_TUPLE_T1S8) ||
+ (Instrux->TupleType == ND_TUPLE_T1S16) ||
+ (Instrux->TupleType == ND_TUPLE_T1F))
+ {
+ // Scalar instruction, vector length is 128 bits.
+ Instrux->VecMode = Instrux->EfVecMode = ND_VECM_128;
+ }
+ else if (Instrux->Evex.u == 0)
+ {
+ // AVX 10 allows SAE/ER for 256-bit vector length, if EVEX.U is 0.
+ // It is unclear whether the EVEX.U bit is ignored or reserved for scalar instructions.
+ Instrux->VecMode = Instrux->EfVecMode = ND_VECM_256;
+ }
+ else
+ {
+ // Legacy or AVX 10 instruction with U bit set, vector length is 512 bits.
+ Instrux->VecMode = Instrux->EfVecMode = ND_VECM_512;
+ }
+
+ return ND_STATUS_SUCCESS;
+ }
+
+ // Decode EVEX vector length. Also take into consideration the "ignore L" flag.
+ switch (Instrux->Exs.l)
+ {
+ case 0:
+ Instrux->VecMode = ND_VECM_128;
+ Instrux->EfVecMode = ND_VECM_128;
+ break;
+ case 1:
+ Instrux->VecMode = ND_VECM_256;
+ Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_256;
+ break;
+ case 2:
+ Instrux->VecMode = ND_VECM_512;
+ Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_512;
+ break;
+ default:
+ return ND_STATUS_BAD_EVEX_LL;
+ }
+
+ // Some instructions don't support 128 bit vectors.
+ if ((ND_VECM_128 == Instrux->EfVecMode) && (0 != (Instrux->Attributes & ND_FLAG_NOL0)))
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdLegacyPrefixChecks
+//
+static NDSTATUS
+NdLegacyPrefixChecks(
+ INSTRUX *Instrux
+ )
+{
+ // These checks only apply to legacy encoded instructions.
+
+ // Check for LOCK. LOCK can be present only in two cases:
+ // 1. For certain RMW instructions, as long as the destination operand is memory
+ // 2. For MOV to/from CR0 in 32-bit mode on AMD CPUs, which allows access to CR8
+ // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix).
+ if (Instrux->HasLock)
+ {
+ if (0 != (Instrux->Attributes & ND_FLAG_LOCK_SPECIAL) && (ND_CODE_32 == Instrux->DefCode))
+ {
+ // Special case of LOCK being used by MOV cr to access CR8.
+ }
+ else if (Instrux->ValidPrefixes.Lock && (Instrux->Operands[0].Type == ND_OP_MEM))
+ {
+ Instrux->IsLockEnabled = 1;
+ }
+ else
+ {
+ return ND_STATUS_BAD_LOCK_PREFIX;
+ }
+ }
+
+ // Chec for REP prefixes. There are multiple uses:
+ // 1. REP/REPNZ/REPZ, for string/IO instructions
+ // 2. XACQUIRE/XRELEASE, for HLE-enabled instructions
+ // 3. BND prefix, for branches
+ // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix).
+ if (Instrux->Rep != 0)
+ {
+ if (Instrux->Attributes & ND_FLAG_NOREP)
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ Instrux->IsRepEnabled = Instrux->ValidPrefixes.Rep != 0;
+
+ Instrux->IsRepcEnabled = Instrux->ValidPrefixes.RepCond != 0;
+
+ // Bound enablement.
+ Instrux->IsBndEnabled = (Instrux->ValidPrefixes.Bnd != 0) && (Instrux->Rep == ND_PREFIX_G1_BND);
+
+ // Check if the instruction is REPed.
+ Instrux->IsRepeated = Instrux->IsRepEnabled || Instrux->IsRepcEnabled;
+
+ // Check if the instruction is XACQUIRE or XRELEASE enabled.
+ if ((Instrux->IsLockEnabled || Instrux->ValidPrefixes.HleNoLock) &&
+ (Instrux->Operands[0].Type == ND_OP_MEM))
+ {
+ if ((Instrux->ValidPrefixes.Xacquire || Instrux->ValidPrefixes.Hle) &&
+ (Instrux->Rep == ND_PREFIX_G1_XACQUIRE))
+ {
+ Instrux->IsXacquireEnabled = ND_TRUE;
+ }
+ else if ((Instrux->ValidPrefixes.Xrelease || Instrux->ValidPrefixes.Hle) &&
+ (Instrux->Rep == ND_PREFIX_G1_XRELEASE))
+ {
+ Instrux->IsXreleaseEnabled = ND_TRUE;
+ }
+ }
+ }
+
+ // Check for segment prefixes. Besides offering segment override when accessing memory:
+ // 1. Allow for branch hints to conditional branches
+ // 2. Allow for Do Not Track prefix for indirect branches, to inhibit CET-IBT tracking
+ // Segment prefixes are allowed with XOP/VEX/EVEX instructions, but they have the legacy meaning (no BHINT or DNT).
+ if (Instrux->Seg != 0)
+ {
+ // Branch hint enablement.
+ Instrux->IsBhintEnabled = Instrux->ValidPrefixes.Bhint && (
+ (Instrux->Seg == ND_PREFIX_G2_BR_TAKEN) ||
+ (Instrux->Seg == ND_PREFIX_G2_BR_NOT_TAKEN) ||
+ (Instrux->Seg == ND_PREFIX_G2_BR_ALT));
+
+ // Do-not-track hint enablement.
+ Instrux->IsDntEnabled = Instrux->ValidPrefixes.Dnt && (Instrux->Seg == ND_PREFIX_G2_NO_TRACK);
+ }
+
+ // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix).
+ if (Instrux->HasOpSize && (Instrux->Attributes & ND_FLAG_NO66))
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ // Address size override is allowed with all XOP/VEX/EVEX prefixes.
+ if (Instrux->HasAddrSize && (Instrux->Attributes & ND_FLAG_NO67))
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix).
+ if (Instrux->HasRex2 && (Instrux->Attributes & ND_FLAG_NOREX2))
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ // Check if the instruction is CET tracked. The do not track prefix (0x3E) works only for indirect near JMP and CALL
+ // instructions. It is always enabled for far JMP and CALL instructions.
+ Instrux->IsCetTracked = ND_HAS_CETT(Instrux) && !Instrux->IsDntEnabled;
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdGetEvexFields
+//
+static NDSTATUS
+NdGetEvexFields(
+ INSTRUX *Instrux
+ )
+{
+ // Validate the EVEX prefix, depending on the EVEX extension mode.
+ if (Instrux->EvexMode == ND_EVEXM_EVEX)
+ {
+ // EVEX.U field must be 1 if the Modrm.Mod is not reg-reg OR if EVEX.b is 0.
+ if (Instrux->Evex.u != 1 && (Instrux->ModRm.mod != 3 || Instrux->Exs.bm == 0))
+ {
+ return ND_STATUS_BAD_EVEX_U;
+ }
+
+ // Handle embedded broadcast/rounding-control.
+ if (Instrux->Exs.bm == 1)
+ {
+ if (Instrux->ModRm.mod == 3)
+ {
+ // reg form for the instruction, check for ER or SAE support.
+ if (Instrux->ValidDecorators.Er)
+ {
+ Instrux->HasEr = 1;
+ Instrux->HasSae = 1;
+ Instrux->RoundingMode = (ND_UINT8)Instrux->Exs.l;
+ }
+ else if (Instrux->ValidDecorators.Sae)
+ {
+ Instrux->HasSae = 1;
+ }
+ else if (!!(Instrux->Attributes & ND_FLAG_IER))
+ {
+ // The encoding behaves as if embedded rounding is enabled, but it is in fact ignored.
+ Instrux->HasIgnEr = 1;
+ }
+ else
+ {
+ return ND_STATUS_ER_SAE_NOT_SUPPORTED;
+ }
+ }
+ else
+ {
+ // mem form for the instruction, check for broadcast.
+ if (Instrux->ValidDecorators.Broadcast)
+ {
+ Instrux->HasBroadcast = 1;
+ }
+ else
+ {
+ return ND_STATUS_BROADCAST_NOT_SUPPORTED;
+ }
+ }
+ }
+
+ // Handle masking.
+ if (Instrux->Exs.k != 0)
+ {
+ if (Instrux->ValidDecorators.Mask)
+ {
+ Instrux->HasMask = 1;
+ }
+ else
+ {
+ return ND_STATUS_MASK_NOT_SUPPORTED;
+ }
+ }
+ else
+ {
+ if (!!(Instrux->Attributes & ND_FLAG_MMASK))
+ {
+ return ND_STATUS_MASK_REQUIRED;
+ }
+ }
+
+ // Handle zeroing.
+ if (Instrux->Exs.z != 0)
+ {
+ if (Instrux->ValidDecorators.Zero)
+ {
+ // Zeroing restrictions:
+ // - valid with register only;
+ // - valid only if masking is also used;
+ if (Instrux->HasMask)
+ {
+ Instrux->HasZero = 1;
+ }
+ else
+ {
+ return ND_STATUS_ZEROING_NO_MASK;
+ }
+ }
+ else
+ {
+ return ND_STATUS_ZEROING_NOT_SUPPORTED;
+ }
+ }
+
+ // EVEX instructions with 8 bit displacement use compressed displacement addressing, where the displacement
+ // is scaled according to the data type accessed by the instruction.
+ if (Instrux->HasDisp && Instrux->DispLength == 1)
+ {
+ Instrux->HasCompDisp = ND_TRUE;
+ }
+
+ // Legacy EVEX.
+ Instrux->Exs.nd = 0;
+ Instrux->Exs.nf = 0;
+ Instrux->Exs.sc = 0;
+ }
+ else
+ {
+ // EVEX extension for VEX/Legacy/Conditional instructions.
+ const ND_UINT8 b3mask[4] =
+ { // Bit 7 6 5 4 3 2 1 0
+ 0x00, // Regular form: | z | L | L | b | V4 | a | a | a |
+ 0xD3, // VEX form: | 0 | 0 | L | 0 | V4 | NF | 0 | 0 |
+ 0xE3, // Legacy form: | 0 | 0 | 0 | ND | V4 | NF | 0 | 0 |
+ 0xE0, // Cond form: | 0 | 0 | 0 | ND | SC3 | SC2 | SC1 | SC0 |
+ };
+
+ // EVEX flavors are only valid in APX mode. Outside APX, only legacy EVEX is valid.
+ if (0 == (Instrux->FeatMode & ND_FEAT_APX))
+ {
+ return ND_STATUS_INVALID_ENCODING;
+ }
+
+ // Apply EVEX payload byte 3 mask.
+ if (0 != (Instrux->Evex.Evex[3] & b3mask[Instrux->EvexMode]))
+ {
+ return ND_STATUS_INVALID_EVEX_BYTE3;
+ }
+
+ // EVEX.U field must be 1 if mod is reg-reg.
+ if (Instrux->Evex.u != 1 && Instrux->ModRm.mod == 3)
+ {
+ return ND_STATUS_BAD_EVEX_U;
+ }
+
+ if (Instrux->ValidDecorators.Nd)
+ {
+ Instrux->HasNd = (ND_BOOL)Instrux->Exs.nd;
+ }
+
+ if (Instrux->ValidDecorators.Nf)
+ {
+ Instrux->HasNf = (ND_BOOL)Instrux->Exs.nf;
+ }
+
+ if (Instrux->ValidDecorators.Zu)
+ {
+ Instrux->HasZu = (ND_BOOL)Instrux->Exs.nd;
+ }
+
+ Instrux->Exs.z = 0;
+ Instrux->Exs.l = 0;
+ Instrux->Exs.bm = 0;
+ Instrux->Exs.k = 0;
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdVexExceptionChecks
+//
+static NDSTATUS
+NdVexExceptionChecks(
+ INSTRUX *Instrux
+ )
+{
+ // These checks only apply to XOP/VEX/EVEX encoded instructions.
+
+ // Instructions that don't use VEX/XOP/EVEX vvvv field must set it to 1111b/0 logic, otherwise a #UD will
+ // be generated.
+ if ((Instrux->Attributes & ND_FLAG_NOV) && (0 != Instrux->Exs.v))
+ {
+ return ND_STATUS_VEX_VVVV_MUST_BE_ZERO;
+ }
+
+ // Instruction that don't use EVEX.V' field must set to to 1b/0 logic, otherwise a #UD will be generated.
+ if ((Instrux->Attributes & ND_FLAG_NOVP) && (0 != Instrux->Exs.vp))
+ {
+ return ND_STATUS_BAD_EVEX_V_PRIME;
+ }
+
+ // VSIB instructions have a restriction: the same vector register can't be used by more than one operand.
+ // The exception is SCATTER*, which can use the VSIB reg as two sources.
+ if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER)
+ {
+ ND_UINT8 usedVects[32] = { 0 };
+ ND_UINT32 i;
+
+ for (i = 0; i < Instrux->OperandsCount; i++)
+ {
+ if (Instrux->Operands[i].Type == ND_OP_REG && Instrux->Operands[i].Info.Register.Type == ND_REG_SSE)
+ {
+ if (++usedVects[Instrux->Operands[i].Info.Register.Reg] > 1)
+ {
+ return ND_STATUS_INVALID_VSIB_REGS;
+ }
+ }
+ else if (Instrux->Operands[i].Type == ND_OP_MEM)
+ {
+ if (++usedVects[Instrux->Operands[i].Info.Memory.Index] > 1)
+ {
+ return ND_STATUS_INVALID_VSIB_REGS;
+ }
+ }
+ }
+ }
+
+ // Handle AMX exception class.
+ if (Instrux->ExceptionType == ND_EXT_AMX_E4 ||
+ Instrux->ExceptionType == ND_EXT_AMX_E10)
+ {
+ // #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs.
+ if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg ||
+ Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg ||
+ Instrux->Operands[1].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg)
+ {
+ return ND_STATUS_INVALID_TILE_REGS;
+ }
+ }
+
+ // If E4* or E10* exception class is used (check out AVX512-FP16 instructions), an additional #UD case
+ // exists: if the destination register is equal to either of the source registers.
+ else if (Instrux->ExceptionType == ND_EXT_E4S || Instrux->ExceptionType == ND_EXT_E10S)
+ {
+ // Note that operand 0 is the destination, operand 1 is the mask, operand 2 is first source, operand
+ // 3 is the second source.
+ if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[2].Type == ND_OP_REG &&
+ Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg)
+ {
+ return ND_STATUS_INVALID_DEST_REGS;
+ }
+
+ if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[3].Type == ND_OP_REG &&
+ Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[3].Info.Register.Reg)
+ {
+ return ND_STATUS_INVALID_DEST_REGS;
+ }
+ }
+
+ // Handle PUSH2/POP2 exceptions, which have restrictions on the destination registers.
+ else if (Instrux->ExceptionType == ND_EXT_APX_EVEX_PP2)
+ {
+ // The registers cannot be RSP for either PUSH2 or POP2.
+ if (Instrux->Operands[0].Info.Register.Reg == NDR_RSP ||
+ Instrux->Operands[1].Info.Register.Reg == NDR_RSP)
+ {
+ return ND_STATUS_INVALID_DEST_REGS;
+ }
+
+ // The destination registers cannot be the same for POP2.
+ if (Instrux->Operands[0].Access.Write &&
+ Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg)
+ {
+ return ND_STATUS_INVALID_DEST_REGS;
+ }
+ }
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdCopyInstructionInfo
+//
+static NDSTATUS
+NdCopyInstructionInfo(
+ INSTRUX *Instrux,
+ ND_IDBE *Idbe
+ )
+{
+#ifndef BDDISASM_NO_MNEMONIC
+ Instrux->Mnemonic = gMnemonics[Idbe->Mnemonic];
+#endif // !BDDISASM_NO_MNEMONIC
+ Instrux->Attributes = Idbe->Attributes;
+ Instrux->Instruction = (ND_INS_CLASS)Idbe->Instruction;
+ Instrux->Category = (ND_INS_CATEGORY)Idbe->Category;
+ Instrux->IsaSet = (ND_INS_SET)Idbe->IsaSet;
+ Instrux->FlagsAccess.Undefined.Raw = Idbe->SetFlags & Idbe->ClearedFlags;
+ Instrux->FlagsAccess.Tested.Raw = Idbe->TestedFlags;
+ Instrux->FlagsAccess.Modified.Raw = Idbe->ModifiedFlags;
+ Instrux->FlagsAccess.Set.Raw = Idbe->SetFlags ^ Instrux->FlagsAccess.Undefined.Raw;
+ Instrux->FlagsAccess.Cleared.Raw = Idbe->ClearedFlags ^ Instrux->FlagsAccess.Undefined.Raw;
+ Instrux->CpuidFlag.Flag = Idbe->CpuidFlag;
+ Instrux->ValidModes.Raw = Idbe->ValidModes;
+ Instrux->ValidPrefixes.Raw = Idbe->ValidPrefixes;
+ Instrux->ValidDecorators.Raw = Idbe->ValidDecorators;
+ Instrux->FpuFlagsAccess.Raw = Idbe->FpuFlags;
+ Instrux->SimdExceptions.Raw = Idbe->SimdExc;
+ // Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used.
+ Instrux->ExceptionType = Idbe->ExcType;
+ Instrux->TupleType = Idbe->TupleType;
+ Instrux->EvexMode = Idbe->EvexMode;
+
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdDecodeEx2
+//
+NDSTATUS
+NdDecodeEx2(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_SIZET Size,
+ ND_UINT8 DefCode,
+ ND_UINT8 DefData,
+ ND_UINT8 DefStack,
+ ND_UINT8 Vendor
+ )
+{
+ ND_CONTEXT opt;
+
+ NdInitContext(&opt);
+
+ opt.DefCode = DefCode;
+ opt.DefData = DefData;
+ opt.DefStack = DefStack;
+ opt.VendMode = Vendor;
+ opt.FeatMode = ND_FEAT_ALL; // Optimistically decode everything, as if all features are enabled.
+
+ return NdDecodeWithContext(Instrux, Code, Size, &opt);
+}
+
+
+NDSTATUS
+NdDecodeWithContext(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_SIZET Size,
+ ND_CONTEXT *Context
+ )
+{
+ NDSTATUS status;
+ PND_IDBE pIns;
+ ND_UINT32 opIndex;
+
+ // pre-init
+ status = ND_STATUS_SUCCESS;
+ pIns = (PND_IDBE)ND_NULL;
+ opIndex = 0;
+
+ // validate
+ if (ND_NULL == Instrux)
+ {
+ return ND_STATUS_INVALID_PARAMETER;
+ }
+
+ if (ND_NULL == Code)
+ {
+ return ND_STATUS_INVALID_PARAMETER;
+ }
+
+ if (Size == 0)
+ {
+ return ND_STATUS_INVALID_PARAMETER;
+ }
+
+ if (ND_NULL == Context)
+ {
+ return ND_STATUS_INVALID_PARAMETER;
+ }
+
+ if (ND_CODE_64 < Context->DefCode)
+ {
+ return ND_STATUS_INVALID_PARAMETER;
+ }
+
+ if (ND_DATA_64 < Context->DefData)
+ {
+ return ND_STATUS_INVALID_PARAMETER;
+ }
+
+ if (ND_VEND_MAX < Context->VendMode)
+ {
+ return ND_STATUS_INVALID_PARAMETER;
+ }
+
+ if (0 == (Context->Options & ND_OPTION_SKIP_ZERO_INSTRUX))
+ {
+ // Initialize with zero.
+ nd_memzero(Instrux, sizeof(INSTRUX));
+ }
+
+ Instrux->DefCode = (ND_UINT8)Context->DefCode;
+ Instrux->DefData = (ND_UINT8)Context->DefData;
+ Instrux->DefStack = (ND_UINT8)Context->DefStack;
+ Instrux->VendMode = (ND_UINT8)Context->VendMode;
+ Instrux->FeatMode = (ND_UINT8)Context->FeatMode;
+ Instrux->EncMode = ND_ENCM_LEGACY; // Assume legacy encoding by default.
+
+ // Fetch the instruction bytes.
+ for (opIndex = 0;
+ opIndex < ((Size < ND_MAX_INSTRUCTION_LENGTH) ? Size : ND_MAX_INSTRUCTION_LENGTH);
+ opIndex++)
+ {
+ Instrux->InstructionBytes[opIndex] = Code[opIndex];
+ }
+
+ if (gPrefixesMap[Instrux->InstructionBytes[0]] != ND_PREF_CODE_NONE)
+ {
+ // Fetch prefixes. We peek at the first byte, to see if it's worth calling the prefix decoder.
+ status = NdFetchPrefixes(Instrux, Instrux->InstructionBytes, 0, Size);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+
+ // Get addressing mode & operand size.
+ status = NdGetAddrAndOpMode(Instrux);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // Start iterating the tables, in order to extract the instruction entry.
+ status = NdFindInstruction(Instrux, Instrux->InstructionBytes, Size, &pIns);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // Copy information inside the Instrux.
+ status = NdCopyInstructionInfo(Instrux, pIns);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ // Get effective operand mode.
+ status = NdGetEffectiveAddrAndOpMode(Instrux);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+
+ if (Instrux->HasEvex)
+ {
+ // Post-process EVEX encoded instructions. This does two thing:
+ // - check and fill in decorator info;
+ // - generate error for invalid broadcast/rounding, mask or zeroing bits;
+ // - generate error if any reserved bits are set.
+ status = NdGetEvexFields(Instrux);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+
+ if (ND_HAS_VECTOR(Instrux))
+ {
+ // Get vector length.
+ status = NdGetVectorLength(Instrux);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+
+ Instrux->ExpOperandsCount = ND_EXP_OPS_CNT(pIns->OpsCount);
+ Instrux->OperandsCount = Instrux->ExpOperandsCount;
+
+ if (!(Context->Options & ND_OPTION_ONLY_EXPLICIT_OPERANDS))
+ {
+ Instrux->OperandsCount += ND_IMP_OPS_CNT(pIns->OpsCount);
+ }
+
+ // And now decode each operand.
+ for (opIndex = 0; opIndex < Instrux->OperandsCount; ++opIndex)
+ {
+ status = NdParseOperand(Instrux, Instrux->InstructionBytes, Instrux->Length, Size,
+ opIndex, pIns->Operands[opIndex]);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+
+ if (ND_ENCM_LEGACY == Instrux->EncMode)
+ {
+ // Do legacy prefix checks. Only available for legacy instructions. For XOP/VEX/EVEX instructions:
+ // 1. LOCK, REP, 0x66, REX, REX2 cause #UD (checkd during XOP/VEX/EVEX fetch)
+ // 2. Segment prefixes do not have BHINT or DNT semantic
+ // 3. 0x67 can be used to override address mode
+ // This has to be done after operand parsing, since some #UD conditions depend on them.
+ status = NdLegacyPrefixChecks(Instrux);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+ else
+ {
+ // Do XOP/VEX/EVEX encoding checks. Additional #UD conditions, some dependent on encoded registers.
+ // This has to be done after operand parsing, since some #UD conditions depend on them.
+ status = NdVexExceptionChecks(Instrux);
+ if (!ND_SUCCESS(status))
+ {
+ return status;
+ }
+ }
+
+ // All done! Instruction successfully decoded!
+ return ND_STATUS_SUCCESS;
+}
+
+
+//
+// NdDecodeEx
+//
+NDSTATUS
+NdDecodeEx(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_SIZET Size,
+ ND_UINT8 DefCode,
+ ND_UINT8 DefData
+ )
+{
+ return NdDecodeEx2(Instrux, Code, Size, DefCode, DefData, DefCode, ND_VEND_ANY);
+}
+
+
+//
+// NdDecode
+//
+NDSTATUS
+NdDecode(
+ INSTRUX *Instrux,
+ const ND_UINT8 *Code,
+ ND_UINT8 DefCode,
+ ND_UINT8 DefData
+ )
+{
+ return NdDecodeEx2(Instrux, Code, ND_MAX_INSTRUCTION_LENGTH, DefCode, DefData, DefCode, ND_VEND_ANY);
+}
+
+
+//
+// NdInitContext
+//
+void
+NdInitContext(
+ ND_CONTEXT *Context
+ )
+{
+ nd_memzero(Context, sizeof(*Context));
+}
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bddisasm_crt.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bddisasm_crt.h
new file mode 100644
index 00000000000000..9f0035c16a6688
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bddisasm_crt.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ND_CRT_H
+#define ND_CRT_H
+
+#include "/home/bernhard/data/entwicklung/2024/llvm-mingw/2024-10-18/llvm-mingw/llvm-project/compiler-rt/lib/interception/bddisasm/inc/bddisasm_types.h"
+
+#ifndef UNREFERENCED_PARAMETER
+#define UNREFERENCED_PARAMETER(P) ((void)(P))
+#endif
+
+// By default, an integrator is expected to provide nd_vsnprintf_s and nd_strcat_s.
+// bddisasm needs both for NdToText, while bdshemu needs nd_vsnprintf_s for emulation tracing.
+// If BDDISASM_NO_FORMAT is defined at compile time these requirements are removed. Instruction formatting will no
+// longer be available in bddisasm and emulation tracing will no longer be available in bdshemu.
+#ifndef BDDISASM_NO_FORMAT
+#include <stdarg.h>
+
+extern int nd_vsnprintf_s(
+ char *buffer,
+ ND_SIZET sizeOfBuffer,
+ ND_SIZET count,
+ const char *format,
+ va_list argptr
+ );
+
+char *
+nd_strcat_s(
+ char *dst,
+ ND_SIZET dst_size,
+ const char *src
+ );
+#endif // !BDDISASM_NO_FORMAT
+
+// Declared here only. Expecting it to be defined in the integrator.
+extern void *nd_memset(void *s, int c, ND_SIZET n);
+
+#define nd_memzero(Dest, Size) nd_memset((Dest), 0, (Size))
+
+
+// Handy macros.
+#define RET_EQ(x, y, z) if ((x) == (y)) { return (z); }
+#define RET_GE(x, y, z) if ((x) >= (y)) { return (z); }
+#define RET_GT(x, y, z) if ((x) > (y)) { return (z); }
+
+
+#endif // ND_CRT_H
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_instructions.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_instructions.h
new file mode 100644
index 00000000000000..205fb9c34e35e5
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_instructions.h
@@ -0,0 +1,122121 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_INSTRUCTIONS_H
+#define BDX86_INSTRUCTIONS_H
+
+const ND_IDBE gInstructions[4206] =
+{
+ // Pos:0 Instruction:"AAA" Encoding:"0x37"/""
+ {
+ .Instruction = ND_INS_AAA,
+ .Category = ND_CAT_DECIMAL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 0,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_AF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I"
+ {
+ .Instruction = ND_INS_AAD,
+ .Category = ND_CAT_DECIMAL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2 Instruction:"AADD My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AADD,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 2,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_RAOINT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AADD,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_RAOINT,
+ .Mnemonic = 2,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RAOINT,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I"
+ {
+ .Instruction = ND_INS_AAM,
+ .Category = ND_CAT_DECIMAL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 3,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:5 Instruction:"AAND My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AAND,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 4,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_RAOINT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:6 Instruction:"AAND My,Gy" Encoding:"0x66 0x0F 0x38 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AAND,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_RAOINT,
+ .Mnemonic = 4,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RAOINT,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:7 Instruction:"AAS" Encoding:"0x3F"/""
+ {
+ .Instruction = ND_INS_AAS,
+ .Category = ND_CAT_DECIMAL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 5,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_AF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:8 Instruction:"ADC Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x10 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:9 Instruction:"ADC Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:10 Instruction:"ADC Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:11 Instruction:"ADC Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:12 Instruction:"ADC Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x13 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:13 Instruction:"ADC Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x13 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:14 Instruction:"ADC Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:15 Instruction:"ADC Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /2 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:16 Instruction:"ADC Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /2 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:17 Instruction:"ADC Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:18 Instruction:"ADC Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:19 Instruction:"ADC Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x10 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:20 Instruction:"ADC Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x11 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:21 Instruction:"ADC Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x11 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:22 Instruction:"ADC Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x12 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:23 Instruction:"ADC Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x13 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:24 Instruction:"ADC Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x13 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:25 Instruction:"ADC Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:26 Instruction:"ADC Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /2 iz"/"VMI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:27 Instruction:"ADC Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /2 iz"/"VMI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:28 Instruction:"ADC Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:29 Instruction:"ADC Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:30 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:31 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:32 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:33 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:34 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:35 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:36 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:37 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:38 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:39 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 6,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:40 Instruction:"ADCX Gy,Ey" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x66 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADCX,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 7,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:41 Instruction:"ADCX By,Gy,Ey" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x66 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADCX,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 7,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:42 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADCX,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_ADX,
+ .Mnemonic = 7,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_ADX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:43 Instruction:"ADD Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x00 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:44 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x01 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:45 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x01 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:46 Instruction:"ADD Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x02 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:47 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x03 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:48 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x03 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:49 Instruction:"ADD Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:50 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:51 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:52 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:53 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:54 Instruction:"ADD Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x00 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:55 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x01 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:56 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x01 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:57 Instruction:"ADD Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x02 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:58 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x03 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:59 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x03 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:60 Instruction:"ADD Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:61 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:62 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:63 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:64 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:65 Instruction:"ADD Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x00 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:66 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x01 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:67 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x01 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:68 Instruction:"ADD Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x02 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:69 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x03 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:70 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x03 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:71 Instruction:"ADD Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:72 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /0 iz"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:73 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /0 iz"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:74 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:75 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:76 Instruction:"ADD Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x00 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:77 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x01 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:78 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x01 /r"/"VMR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:79 Instruction:"ADD Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x02 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:80 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x03 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:81 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x03 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:82 Instruction:"ADD Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:83 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /0 iz"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:84 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /0 iz"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:85 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:86 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:87 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:88 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:89 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:90 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:91 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:92 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:93 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:94 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:95 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:96 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ADD,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 8,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:97 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADDPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 9,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:98 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADDPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 10,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:99 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADDSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 11,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:100 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADDSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 12,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:101 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADDSUBPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 13,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:102 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADDSUBPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 14,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:103 Instruction:"ADOX Gy,Ey" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0x66 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADOX,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 15,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:104 Instruction:"ADOX By,Gy,Ey" Encoding:"evex m:4 l:0 nd:1 nf:0 p:2 0x66 /r"/"VRM"
+ {
+ .Instruction = ND_INS_ADOX,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 15,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:105 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM"
+ {
+ .Instruction = ND_INS_ADOX,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_ADX,
+ .Mnemonic = 15,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_ADX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:106 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM"
+ {
+ .Instruction = ND_INS_AESDEC,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 16,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:107 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_AESDEC128KL,
+ .Category = ND_CAT_AESKL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 17,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:108 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_AESDEC256KL,
+ .Category = ND_CAT_AESKL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 18,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:109 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM"
+ {
+ .Instruction = ND_INS_AESDECLAST,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 19,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:110 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_AESDECWIDE128KL,
+ .Category = ND_CAT_WIDE_KL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 20,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:111 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_AESDECWIDE256KL,
+ .Category = ND_CAT_WIDE_KL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 21,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:112 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM"
+ {
+ .Instruction = ND_INS_AESENC,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 22,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:113 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_AESENC128KL,
+ .Category = ND_CAT_AESKL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 23,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:114 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_AESENC256KL,
+ .Category = ND_CAT_AESKL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 24,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:115 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM"
+ {
+ .Instruction = ND_INS_AESENCLAST,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 25,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:116 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_AESENCWIDE128KL,
+ .Category = ND_CAT_WIDE_KL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 26,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:117 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M"
+ {
+ .Instruction = ND_INS_AESENCWIDE256KL,
+ .Category = ND_CAT_WIDE_KL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 27,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:118 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM"
+ {
+ .Instruction = ND_INS_AESIMC,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 28,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:119 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_AESKEYGENASSIST,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 29,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:120 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x20 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:121 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x21 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:122 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x21 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:123 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x22 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:124 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:125 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:126 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:127 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /4 iz"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:128 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /4 iz"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:129 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:130 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:131 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x20 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:132 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x21 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:133 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x21 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:134 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x22 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:135 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:136 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:137 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:138 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /4 iz"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:139 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /4 iz"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:140 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:141 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:142 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x20 /r"/"VMR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:143 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x21 /r"/"VMR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:144 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x21 /r"/"VMR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:145 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x22 /r"/"VRM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:146 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x23 /r"/"VRM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:147 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x23 /r"/"VRM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:148 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:149 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /4 iz"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:150 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /4 iz"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:151 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:152 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:153 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x20 /r"/"VMR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:154 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x21 /r"/"VMR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:155 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x21 /r"/"VMR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:156 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x22 /r"/"VRM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:157 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x23 /r"/"VRM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:158 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x23 /r"/"VRM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:159 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:160 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /4 iz"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:161 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /4 iz"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:162 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:163 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:164 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:165 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:166 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:167 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:168 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:169 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:170 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:171 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:172 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:173 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_AND,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 30,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:174 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_ANDN,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 31,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:175 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_ANDN,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 31,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:176 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_ANDN,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_BMI1,
+ .Mnemonic = 31,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI1,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:177 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM"
+ {
+ .Instruction = ND_INS_ANDNPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 32,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:178 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM"
+ {
+ .Instruction = ND_INS_ANDNPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 33,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:179 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM"
+ {
+ .Instruction = ND_INS_ANDPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 34,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:180 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM"
+ {
+ .Instruction = ND_INS_ANDPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 35,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:181 Instruction:"AOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AOR,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 36,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_RAOINT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:182 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AOR,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_RAOINT,
+ .Mnemonic = 36,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RAOINT,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:183 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR"
+ {
+ .Instruction = ND_INS_ARPL,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 37,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:184 Instruction:"AXOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AXOR,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 38,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_RAOINT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:185 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_AXOR,
+ .Category = ND_CAT_RAOINT,
+ .IsaSet = ND_SET_RAOINT,
+ .Mnemonic = 38,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RAOINT,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:186 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_BEXTR,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 39,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:187 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_BEXTR,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 39,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:188 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_BEXTR,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_BMI1,
+ .Mnemonic = 39,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI1,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:189 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI"
+ {
+ .Instruction = ND_INS_BEXTR,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 39,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:190 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM"
+ {
+ .Instruction = ND_INS_BLCFILL,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 40,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:191 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM"
+ {
+ .Instruction = ND_INS_BLCI,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 41,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:192 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM"
+ {
+ .Instruction = ND_INS_BLCIC,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 42,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:193 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM"
+ {
+ .Instruction = ND_INS_BLCMSK,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 43,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:194 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM"
+ {
+ .Instruction = ND_INS_BLCS,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 44,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:195 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_BLENDPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 45,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:196 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_BLENDPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 46,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:197 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM"
+ {
+ .Instruction = ND_INS_BLENDVPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 47,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:198 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM"
+ {
+ .Instruction = ND_INS_BLENDVPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 48,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:199 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM"
+ {
+ .Instruction = ND_INS_BLSFILL,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 49,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:200 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /3"/"VM"
+ {
+ .Instruction = ND_INS_BLSI,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 50,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:201 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /3"/"VM"
+ {
+ .Instruction = ND_INS_BLSI,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 50,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:202 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM"
+ {
+ .Instruction = ND_INS_BLSI,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_BMI1,
+ .Mnemonic = 50,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI1,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:203 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM"
+ {
+ .Instruction = ND_INS_BLSIC,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 51,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:204 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /2"/"VM"
+ {
+ .Instruction = ND_INS_BLSMSK,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 52,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:205 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /2"/"VM"
+ {
+ .Instruction = ND_INS_BLSMSK,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 52,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:206 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM"
+ {
+ .Instruction = ND_INS_BLSMSK,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_BMI1,
+ .Mnemonic = 52,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI1,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:207 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /1"/"VM"
+ {
+ .Instruction = ND_INS_BLSR,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 53,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:208 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /1"/"VM"
+ {
+ .Instruction = ND_INS_BLSR,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 53,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:209 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM"
+ {
+ .Instruction = ND_INS_BLSR,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_BMI1,
+ .Mnemonic = 53,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI1,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:210 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM"
+ {
+ .Instruction = ND_INS_BNDCL,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 54,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:211 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM"
+ {
+ .Instruction = ND_INS_BNDCN,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 55,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:212 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM"
+ {
+ .Instruction = ND_INS_BNDCU,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 56,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:213 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx NP 0x0F 0x1A /r:mem mib"/"RM"
+ {
+ .Instruction = ND_INS_BNDLDX,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 57,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_MIB,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:214 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_BNDMK,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 58,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:215 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM"
+ {
+ .Instruction = ND_INS_BNDMOV,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 59,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:216 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR"
+ {
+ .Instruction = ND_INS_BNDMOV,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 59,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:217 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx NP 0x0F 0x1B /r:mem mib"/"MR"
+ {
+ .Instruction = ND_INS_BNDSTX,
+ .Category = ND_CAT_MPX,
+ .IsaSet = ND_SET_MPX,
+ .Mnemonic = 60,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_MIB,
+ .CpuidFlag = ND_CFF_MPX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:218 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_BOUND,
+ .Category = ND_CAT_INTERRUPT,
+ .IsaSet = ND_SET_I186,
+ .Mnemonic = 61,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_a, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:219 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM"
+ {
+ .Instruction = ND_INS_BSF,
+ .Category = ND_CAT_I386,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 62,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:220 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM"
+ {
+ .Instruction = ND_INS_BSR,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 63,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:221 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:222 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:223 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:224 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:225 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:226 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:227 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:228 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O"
+ {
+ .Instruction = ND_INS_BSWAP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 64,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:229 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR"
+ {
+ .Instruction = ND_INS_BT,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 65,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:230 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_BT,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 65,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:231 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_BTC,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 66,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:232 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR"
+ {
+ .Instruction = ND_INS_BTC,
+ .Category = ND_CAT_I386,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 66,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:233 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR"
+ {
+ .Instruction = ND_INS_BTR,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 67,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:234 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_BTR,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 67,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:235 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR"
+ {
+ .Instruction = ND_INS_BTS,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 68,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:236 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_BTS,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 68,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:237 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF5 /r"/"RMV"
+ {
+ .Instruction = ND_INS_BZHI,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 69,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:238 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF5 /r"/"RMV"
+ {
+ .Instruction = ND_INS_BZHI,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 69,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:239 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV"
+ {
+ .Instruction = ND_INS_BZHI,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 69,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:240 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D"
+ {
+ .Instruction = ND_INS_CALLNR,
+ .Category = ND_CAT_CALL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 70,
+ .ValidPrefixes = ND_PREF_BND,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:241 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M"
+ {
+ .Instruction = ND_INS_CALLNI,
+ .Category = ND_CAT_CALL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 70,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_DNT,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:242 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D"
+ {
+ .Instruction = ND_INS_CALLFD,
+ .Category = ND_CAT_CALL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 71,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:243 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M"
+ {
+ .Instruction = ND_INS_CALLFI,
+ .Category = ND_CAT_CALL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 71,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_CETT|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:244 Instruction:"CBW" Encoding:"ds16 0x98"/""
+ {
+ .Instruction = ND_INS_CBW,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 72,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:245 Instruction:"CCMPBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:246 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:247 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:248 Instruction:"CCMPBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:249 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:250 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:251 Instruction:"CCMPBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:252 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:253 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:254 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:255 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 73,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:256 Instruction:"CCMPC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:257 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:258 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:259 Instruction:"CCMPC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:260 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:261 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:262 Instruction:"CCMPC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:263 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:264 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:265 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:266 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 74,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:267 Instruction:"CCMPF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:268 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:269 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:270 Instruction:"CCMPF Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:271 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:272 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:273 Instruction:"CCMPF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:274 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:275 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:276 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:277 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 75,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:278 Instruction:"CCMPL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:279 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:280 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:281 Instruction:"CCMPL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:282 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:283 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:284 Instruction:"CCMPL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:285 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:286 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:287 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:288 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 76,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:289 Instruction:"CCMPLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:290 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:291 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:292 Instruction:"CCMPLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:293 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:294 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:295 Instruction:"CCMPLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:296 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:297 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:298 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:299 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 77,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:300 Instruction:"CCMPNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:301 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:302 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:303 Instruction:"CCMPNBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:304 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:305 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:306 Instruction:"CCMPNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:307 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:308 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:309 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:310 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 78,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:311 Instruction:"CCMPNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:312 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:313 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:314 Instruction:"CCMPNC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:315 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:316 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:317 Instruction:"CCMPNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:318 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:319 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:320 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:321 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 79,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:322 Instruction:"CCMPNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:323 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:324 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:325 Instruction:"CCMPNL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:326 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:327 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:328 Instruction:"CCMPNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:329 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:330 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:331 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:332 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 80,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:333 Instruction:"CCMPNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:334 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:335 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:336 Instruction:"CCMPNLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:337 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:338 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:339 Instruction:"CCMPNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:340 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:341 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:342 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:343 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 81,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:344 Instruction:"CCMPNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:345 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:346 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:347 Instruction:"CCMPNO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:348 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:349 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:350 Instruction:"CCMPNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:351 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:352 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:353 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:354 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 82,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:355 Instruction:"CCMPNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:356 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:357 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:358 Instruction:"CCMPNS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:359 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:360 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:361 Instruction:"CCMPNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:362 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:363 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:364 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:365 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 83,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:366 Instruction:"CCMPNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:367 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:368 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:369 Instruction:"CCMPNZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:370 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:371 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:372 Instruction:"CCMPNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:373 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:374 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:375 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:376 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 84,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:377 Instruction:"CCMPO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:378 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:379 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:380 Instruction:"CCMPO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:381 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:382 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:383 Instruction:"CCMPO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:384 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:385 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:386 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:387 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 85,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:388 Instruction:"CCMPS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:389 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:390 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:391 Instruction:"CCMPS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:392 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:393 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:394 Instruction:"CCMPS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:395 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:396 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:397 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:398 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 86,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:399 Instruction:"CCMPT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:400 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:401 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:402 Instruction:"CCMPT Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:403 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:404 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:405 Instruction:"CCMPT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:406 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:407 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:408 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:409 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 87,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:410 Instruction:"CCMPZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x38 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:411 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:412 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x39 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:413 Instruction:"CCMPZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3A /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:414 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:415 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x3B /r"/"RMV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:416 Instruction:"CCMPZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x80 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:417 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:418 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x81 /7 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:419 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:420 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x83 /7 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CCMP,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 88,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:421 Instruction:"CDQ" Encoding:"ds32 0x99"/""
+ {
+ .Instruction = ND_INS_CDQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 89,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:422 Instruction:"CDQE" Encoding:"ds64 0x98"/""
+ {
+ .Instruction = ND_INS_CDQE,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 90,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:423 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x46 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:424 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:425 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:426 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x46 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:427 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:428 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:429 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x46 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:430 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x46 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 91,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:431 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x42 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:432 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:433 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:434 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x42 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:435 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:436 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:437 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x42 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:438 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x42 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 92,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:439 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4C /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:440 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:441 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:442 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4C /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:443 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:444 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:445 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4C /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:446 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4C /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 93,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:447 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4E /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:448 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:449 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:450 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4E /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:451 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:452 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:453 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4E /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:454 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4E /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 94,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:455 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x47 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:456 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:457 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:458 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x47 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:459 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:460 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:461 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x47 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:462 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x47 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 95,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:463 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x43 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:464 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:465 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:466 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x43 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:467 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:468 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:469 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x43 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:470 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x43 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 96,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:471 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4D /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:472 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:473 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:474 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4D /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:475 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:476 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:477 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4D /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:478 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4D /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 97,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:479 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4F /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:480 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:481 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:482 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4F /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:483 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:484 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:485 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4F /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:486 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4F /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 98,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:487 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x41 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:488 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:489 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:490 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x41 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:491 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:492 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:493 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x41 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:494 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x41 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 99,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:495 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4B /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:496 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:497 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:498 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4B /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:499 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:500 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:501 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4B /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:502 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4B /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:503 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x49 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:504 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:505 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:506 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x49 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:507 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:508 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:509 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x49 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:510 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x49 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:511 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x45 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:512 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:513 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:514 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x45 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:515 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:516 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:517 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x45 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:518 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x45 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:519 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x40 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:520 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:521 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:522 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x40 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:523 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:524 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:525 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x40 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:526 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x40 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:527 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4A /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:528 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:529 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:530 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4A /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:531 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:532 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:533 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4A /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:534 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4A /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:535 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x48 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:536 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:537 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:538 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x48 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:539 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:540 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:541 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x48 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:542 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x48 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:543 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x44 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:544 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:545 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:546 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x44 /r"/"RM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:547 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:548 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:549 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x44 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:550 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x44 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CFCMOV,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CFCMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:551 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/""
+ {
+ .Instruction = ND_INS_CLAC,
+ .Category = ND_CAT_SMAP,
+ .IsaSet = ND_SET_SMAP,
+ .Mnemonic = 107,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_AC,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SMAP,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:552 Instruction:"CLC" Encoding:"0xF8"/""
+ {
+ .Instruction = ND_INS_CLC,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 108,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:553 Instruction:"CLD" Encoding:"0xFC"/""
+ {
+ .Instruction = ND_INS_CLD,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 109,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_DF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:554 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M"
+ {
+ .Instruction = ND_INS_CLDEMOTE,
+ .Category = ND_CAT_CLDEMOTE,
+ .IsaSet = ND_SET_CLDEMOTE,
+ .Mnemonic = 110,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CLDEMOTE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:555 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M"
+ {
+ .Instruction = ND_INS_CLEVICT0,
+ .Category = ND_CAT_UNKNOWN,
+ .IsaSet = ND_SET_UNKNOWN,
+ .Mnemonic = 111,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:556 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M"
+ {
+ .Instruction = ND_INS_CLEVICT1,
+ .Category = ND_CAT_UNKNOWN,
+ .IsaSet = ND_SET_UNKNOWN,
+ .Mnemonic = 112,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:557 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
+ {
+ .Instruction = ND_INS_CLFLUSH,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_CLFSH,
+ .Mnemonic = 113,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CLFSH,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:558 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
+ {
+ .Instruction = ND_INS_CLFLUSHOPT,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_CLFSHOPT,
+ .Mnemonic = 114,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CLFSHOPT,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:559 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/""
+ {
+ .Instruction = ND_INS_CLGI,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 115,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:560 Instruction:"CLI" Encoding:"0xFA"/""
+ {
+ .Instruction = ND_INS_CLI,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 116,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_IF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:561 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M"
+ {
+ .Instruction = ND_INS_CLRSSBSY,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 117,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:562 Instruction:"CLTS" Encoding:"0x0F 0x06"/""
+ {
+ .Instruction = ND_INS_CLTS,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 118,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:563 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/""
+ {
+ .Instruction = ND_INS_CLUI,
+ .Category = ND_CAT_UINTR,
+ .IsaSet = ND_SET_UINTR,
+ .Mnemonic = 119,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_UINTR,
+ .Operands =
+ {
+ OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:564 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
+ {
+ .Instruction = ND_INS_CLWB,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_CLWB,
+ .Mnemonic = 120,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CLWB,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:565 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/""
+ {
+ .Instruction = ND_INS_CLZERO,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_CLZERO,
+ .Mnemonic = 121,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:566 Instruction:"CMC" Encoding:"0xF5"/""
+ {
+ .Instruction = ND_INS_CMC,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 122,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:567 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x46 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 123,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:568 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x46 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 123,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:569 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 123,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:570 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x42 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 124,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:571 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x42 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 124,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:572 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 124,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:573 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4C /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 125,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:574 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4C /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 125,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:575 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 125,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:576 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4E /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 126,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:577 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4E /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 126,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:578 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 126,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:579 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x47 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 127,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:580 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x47 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 127,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:581 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 127,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:582 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x43 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 128,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:583 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x43 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 128,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:584 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 128,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:585 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4D /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 129,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:586 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4D /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 129,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:587 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 129,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:588 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4F /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 130,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:589 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4F /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 130,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:590 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 130,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:591 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x41 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 131,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:592 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x41 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 131,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:593 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 131,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:594 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4B /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 132,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:595 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4B /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 132,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:596 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 132,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:597 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x49 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 133,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:598 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x49 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 133,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:599 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 133,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:600 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x45 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 134,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:601 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x45 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 134,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:602 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 134,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:603 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x40 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 135,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:604 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x40 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 135,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:605 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 135,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:606 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4A /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 136,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:607 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4A /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 136,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:608 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 136,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:609 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x48 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 137,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:610 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x48 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 137,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:611 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 137,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:612 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x44 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 138,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:613 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x44 /r"/"VRM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 138,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:614 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM"
+ {
+ .Instruction = ND_INS_CMOVcc,
+ .Category = ND_CAT_CMOV,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 138,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMOV,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:615 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:616 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:617 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:618 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:619 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:620 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:621 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:622 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:623 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:624 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_CMP,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:625 Instruction:"CMPBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE6 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPBEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 140,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:626 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPBEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 140,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:627 Instruction:"CMPCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE2 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPCXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 141,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:628 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPCXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 141,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:629 Instruction:"CMPLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEE /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPLEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 142,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:630 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPLEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 142,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:631 Instruction:"CMPLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEC /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPLXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 143,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:632 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPLXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 143,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:633 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE7 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNBEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 144,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:634 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNBEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 144,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:635 Instruction:"CMPNCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE3 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNCXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 145,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:636 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNCXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 145,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:637 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEF /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNLEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 146,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:638 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNLEXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 146,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:639 Instruction:"CMPNLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xED /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNLXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 147,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:640 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNLXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 147,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:641 Instruction:"CMPNOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE1 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNOXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 148,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:642 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNOXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 148,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:643 Instruction:"CMPNPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEB /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNPXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 149,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:644 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNPXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 149,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:645 Instruction:"CMPNSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE9 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNSXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 150,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:646 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNSXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 150,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:647 Instruction:"CMPNZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE5 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNZXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 151,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:648 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPNZXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 151,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:649 Instruction:"CMPOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE0 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPOXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 152,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:650 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPOXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 152,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:651 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_CMPPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 153,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:652 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_CMPPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 154,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:653 Instruction:"CMPPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEA /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPPXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 155,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:654 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPPXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 155,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:655 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 156,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:656 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 156,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:657 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 157,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:658 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 157,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:659 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_CMPSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 157,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:660 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 158,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:661 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 158,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:662 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_CMPSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 159,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:663 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 160,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:664 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/""
+ {
+ .Instruction = ND_INS_CMPS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 160,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:665 Instruction:"CMPSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE8 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPSXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 161,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:666 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPSXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 161,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:667 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR"
+ {
+ .Instruction = ND_INS_CMPXCHG,
+ .Category = ND_CAT_SEMAPHORE,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 162,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:668 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR"
+ {
+ .Instruction = ND_INS_CMPXCHG,
+ .Category = ND_CAT_SEMAPHORE,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 162,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:669 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_CMPXCHG16B,
+ .Category = ND_CAT_SEMAPHORE,
+ .IsaSet = ND_SET_CMPXCHG16B,
+ .Mnemonic = 163,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CX8,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:670 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_CMPXCHG8B,
+ .Category = ND_CAT_SEMAPHORE,
+ .IsaSet = ND_SET_PENTIUMREAL,
+ .Mnemonic = 164,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CX8,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:671 Instruction:"CMPZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE4 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPZXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 165,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CMPCCXADD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:672 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV"
+ {
+ .Instruction = ND_INS_CMPZXADD,
+ .Category = ND_CAT_CMPCCXADD,
+ .IsaSet = ND_SET_CMPCCXADD,
+ .Mnemonic = 165,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_14,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CMPCCXADD,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:673 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_COMISD,
+ .Category = ND_CAT_SSE2,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 166,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:674 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_COMISS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 167,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:675 Instruction:"CPUID" Encoding:"0x0F 0xA2"/""
+ {
+ .Instruction = ND_INS_CPUID,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 168,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:676 Instruction:"CQO" Encoding:"ds64 0x99"/""
+ {
+ .Instruction = ND_INS_CQO,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 169,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:677 Instruction:"CRC32 Gy,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF0 /r"/"RM"
+ {
+ .Instruction = ND_INS_CRC32,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 170,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:678 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF1 /r"/"RM"
+ {
+ .Instruction = ND_INS_CRC32,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 170,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:679 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF1 /r"/"RM"
+ {
+ .Instruction = ND_INS_CRC32,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 170,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:680 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM"
+ {
+ .Instruction = ND_INS_CRC32,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE42,
+ .Mnemonic = 170,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE42,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:681 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM"
+ {
+ .Instruction = ND_INS_CRC32,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE42,
+ .Mnemonic = 170,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE42,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:682 Instruction:"CTESTBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:683 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:684 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:685 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:686 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:687 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:688 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:689 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:690 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:691 Instruction:"CTESTC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:692 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:693 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:694 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:695 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:696 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:697 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:698 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:699 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:700 Instruction:"CTESTF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:701 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:702 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:703 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:704 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:705 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:706 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:707 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:708 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:709 Instruction:"CTESTL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:710 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:711 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:712 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:713 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:714 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:715 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:716 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:717 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:718 Instruction:"CTESTLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:719 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:720 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:721 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:722 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:723 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:724 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:725 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:726 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:727 Instruction:"CTESTNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:728 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:729 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:730 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:731 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:732 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:733 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:734 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:735 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:736 Instruction:"CTESTNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:737 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:738 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:739 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:740 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:741 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:742 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:743 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:744 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:745 Instruction:"CTESTNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:746 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:747 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:748 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:749 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:750 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:751 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:752 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:753 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:754 Instruction:"CTESTNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:755 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:756 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:757 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:758 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:759 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:760 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:761 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:762 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:763 Instruction:"CTESTNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:764 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:765 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:766 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:767 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:768 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:769 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:770 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:771 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:772 Instruction:"CTESTNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:773 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:774 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:775 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:776 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:777 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:778 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:779 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:780 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:781 Instruction:"CTESTNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:782 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:783 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:784 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:785 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:786 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:787 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:788 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:789 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:790 Instruction:"CTESTO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:791 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:792 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:793 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:794 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:795 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:796 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:797 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:798 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:799 Instruction:"CTESTS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:800 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:801 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:802 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:803 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:804 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:805 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:806 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:807 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:808 Instruction:"CTESTT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:809 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:810 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:811 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:812 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:813 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:814 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:815 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:816 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:817 Instruction:"CTESTZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x84 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:818 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:819 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x85 /r"/"MRV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:820 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /0 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:821 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /1 ib"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:822 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:823 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /0 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:824 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:825 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /1 iz"/"MIV"
+ {
+ .Instruction = ND_INS_CTEST,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_CCMP,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_COND,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:826 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTDQ2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 187,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:827 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTDQ2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 188,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:828 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPD2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 189,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:829 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPD2PI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 190,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:830 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPD2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 191,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:831 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPI2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 192,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:832 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPI2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 193,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:833 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPS2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 194,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:834 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPS2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 195,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:835 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTPS2PI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 196,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:836 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTSD2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 197,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:837 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTSD2SS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 198,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:838 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTSI2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 199,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:839 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTSI2SS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 200,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:840 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTSS2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 201,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:841 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTSS2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 202,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:842 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTTPD2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 203,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:843 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTTPD2PI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 204,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:844 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTTPS2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 205,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:845 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTTPS2PI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 206,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:846 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTTSD2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 207,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:847 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_CVTTSS2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 208,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:848 Instruction:"CWD" Encoding:"ds16 0x99"/""
+ {
+ .Instruction = ND_INS_CWD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 209,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:849 Instruction:"CWDE" Encoding:"ds32 0x98"/""
+ {
+ .Instruction = ND_INS_CWDE,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 210,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:850 Instruction:"DAA" Encoding:"0x27"/""
+ {
+ .Instruction = ND_INS_DAA,
+ .Category = ND_CAT_DECIMAL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 211,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:851 Instruction:"DAS" Encoding:"0x2F"/""
+ {
+ .Instruction = ND_INS_DAS,
+ .Category = ND_CAT_DECIMAL,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 212,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:852 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:853 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:854 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:855 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:856 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:857 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:858 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /1"/"VM"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:859 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /1"/"VM"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:860 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /1"/"VM"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:861 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /1"/"VM"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:862 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /1"/"VM"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:863 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /1"/"VM"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:864 Instruction:"DEC Zv" Encoding:"0x48"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:865 Instruction:"DEC Zv" Encoding:"0x49"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:866 Instruction:"DEC Zv" Encoding:"0x4A"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:867 Instruction:"DEC Zv" Encoding:"0x4B"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:868 Instruction:"DEC Zv" Encoding:"0x4C"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:869 Instruction:"DEC Zv" Encoding:"0x4D"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:870 Instruction:"DEC Zv" Encoding:"0x4E"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:871 Instruction:"DEC Zv" Encoding:"0x4F"/"O"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:872 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:873 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M"
+ {
+ .Instruction = ND_INS_DEC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 213,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:874 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M"
+ {
+ .Instruction = ND_INS_DELAY,
+ .Category = ND_CAT_UNKNOWN,
+ .IsaSet = ND_SET_UNKNOWN,
+ .Mnemonic = 214,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:875 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:876 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:877 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:878 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:879 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:880 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:881 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:882 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M"
+ {
+ .Instruction = ND_INS_DIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:883 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM"
+ {
+ .Instruction = ND_INS_DIVPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 216,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:884 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM"
+ {
+ .Instruction = ND_INS_DIVPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 217,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:885 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM"
+ {
+ .Instruction = ND_INS_DIVSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 218,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:886 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM"
+ {
+ .Instruction = ND_INS_DIVSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 219,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:887 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_DPPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 220,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:888 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_DPPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 221,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:889 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/""
+ {
+ .Instruction = ND_INS_EMMS,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 222,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:890 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/""
+ {
+ .Instruction = ND_INS_ENCLS,
+ .Category = ND_CAT_SGX,
+ .IsaSet = ND_SET_SGX,
+ .Mnemonic = 223,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SGX,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ },
+ },
+
+ // Pos:891 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/""
+ {
+ .Instruction = ND_INS_ENCLU,
+ .Category = ND_CAT_SGX,
+ .IsaSet = ND_SET_SGX,
+ .Mnemonic = 224,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SGX,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ },
+ },
+
+ // Pos:892 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/""
+ {
+ .Instruction = ND_INS_ENCLV,
+ .Category = ND_CAT_SGX,
+ .IsaSet = ND_SET_SGX,
+ .Mnemonic = 225,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SGX,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0),
+ },
+ },
+
+ // Pos:893 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_ENCODEKEY128,
+ .Category = ND_CAT_AESKL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 226,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3),
+ OP(ND_OPT_XMM4, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:894 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_ENCODEKEY256,
+ .Category = ND_CAT_AESKL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 227,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 2),
+ OP(ND_OPT_XMM2, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 5),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:895 Instruction:"ENDBR32" Encoding:"cet repz 0x0F 0x1E /0xFB"/""
+ {
+ .Instruction = ND_INS_ENDBR,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_IBT,
+ .Mnemonic = 228,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_IBT,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:896 Instruction:"ENDBR64" Encoding:"cet repz 0x0F 0x1E /0xFA"/""
+ {
+ .Instruction = ND_INS_ENDBR,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_IBT,
+ .Mnemonic = 229,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_IBT,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:897 Instruction:"ENQCMD rM?,Moq" Encoding:"evex m:4 l:0 p:3 nd:0 nf:0 0xF8 /r:mem"/"M"
+ {
+ .Instruction = ND_INS_ENQCMD,
+ .Category = ND_CAT_ENQCMD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 230,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_ENQCMD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:898 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M"
+ {
+ .Instruction = ND_INS_ENQCMD,
+ .Category = ND_CAT_ENQCMD,
+ .IsaSet = ND_SET_ENQCMD,
+ .Mnemonic = 230,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_ENQCMD,
+ .Operands =
+ {
+ OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:899 Instruction:"ENQCMDS rM?,Moq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF8 /r:mem"/"M"
+ {
+ .Instruction = ND_INS_ENQCMDS,
+ .Category = ND_CAT_ENQCMD,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 231,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_ENQCMD,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:900 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M"
+ {
+ .Instruction = ND_INS_ENQCMDS,
+ .Category = ND_CAT_ENQCMD,
+ .IsaSet = ND_SET_ENQCMD,
+ .Mnemonic = 231,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_ENQCMD,
+ .Operands =
+ {
+ OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:901 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II"
+ {
+ .Instruction = ND_INS_ENTER,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_I186,
+ .Mnemonic = 232,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rBP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_pBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:902 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/""
+ {
+ .Instruction = ND_INS_ERETS,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_FRED,
+ .Mnemonic = 233,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_FRED,
+ .Operands =
+ {
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v5, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ },
+ },
+
+ // Pos:903 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/""
+ {
+ .Instruction = ND_INS_ERETU,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_FRED,
+ .Mnemonic = 234,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 9),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_FRED,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v5, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:904 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_EXTRACTPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 235,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:905 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 ib ib"/"MII"
+ {
+ .Instruction = ND_INS_EXTRQ,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_SSE4A,
+ .Mnemonic = 236,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4A,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:906 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_EXTRQ,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_SSE4A,
+ .Mnemonic = 236,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4A,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:907 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/""
+ {
+ .Instruction = ND_INS_F2XM1,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 237,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:908 Instruction:"FABS" Encoding:"0xD9 /0xE1"/""
+ {
+ .Instruction = ND_INS_FABS,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 238,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:909 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FADD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 239,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:910 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FADD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 239,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:911 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FADD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 239,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:912 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FADD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 239,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:913 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FADDP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 240,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:914 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M"
+ {
+ .Instruction = ND_INS_FBLD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 241,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:915 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M"
+ {
+ .Instruction = ND_INS_FBSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 242,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:916 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/""
+ {
+ .Instruction = ND_INS_FCHS,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 243,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:917 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 244,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:918 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVBE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 245,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:919 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 246,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:920 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVNB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 247,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:921 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVNBE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 248,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:922 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVNE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 249,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:923 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVNU,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 250,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:924 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M"
+ {
+ .Instruction = ND_INS_FCMOVU,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 251,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:925 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FCOM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 252,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:926 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M"
+ {
+ .Instruction = ND_INS_FCOM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 252,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:927 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FCOM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 252,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:928 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M"
+ {
+ .Instruction = ND_INS_FCOM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 252,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:929 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M"
+ {
+ .Instruction = ND_INS_FCOMI,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 253,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:930 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M"
+ {
+ .Instruction = ND_INS_FCOMIP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 254,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:931 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FCOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 255,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:932 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M"
+ {
+ .Instruction = ND_INS_FCOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 255,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:933 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FCOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 255,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:934 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M"
+ {
+ .Instruction = ND_INS_FCOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 255,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:935 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M"
+ {
+ .Instruction = ND_INS_FCOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 255,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:936 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/""
+ {
+ .Instruction = ND_INS_FCOMPP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 256,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:937 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/""
+ {
+ .Instruction = ND_INS_FCOS,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 257,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xeb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:938 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/""
+ {
+ .Instruction = ND_INS_FDECSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 258,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:939 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_FDIV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 259,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:940 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M"
+ {
+ .Instruction = ND_INS_FDIV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 259,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:941 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M"
+ {
+ .Instruction = ND_INS_FDIV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 259,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:942 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M"
+ {
+ .Instruction = ND_INS_FDIV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 259,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:943 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M"
+ {
+ .Instruction = ND_INS_FDIVP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 260,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:944 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FDIVR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 261,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:945 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M"
+ {
+ .Instruction = ND_INS_FDIVR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 261,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:946 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FDIVR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 261,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:947 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M"
+ {
+ .Instruction = ND_INS_FDIVR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 261,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:948 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M"
+ {
+ .Instruction = ND_INS_FDIVRP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 262,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:949 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/""
+ {
+ .Instruction = ND_INS_FEMMS,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 263,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:950 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FFREE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 264,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:951 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FFREEP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 265,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:952 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FIADD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 266,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:953 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FIADD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 266,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:954 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FICOM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 267,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:955 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FICOM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 267,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:956 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FICOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 268,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:957 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FICOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 268,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:958 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M"
+ {
+ .Instruction = ND_INS_FIDIV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 269,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:959 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M"
+ {
+ .Instruction = ND_INS_FIDIV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 269,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:960 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FIDIVR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 270,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:961 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FIDIVR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 270,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:962 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FILD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 271,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:963 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FILD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 271,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:964 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M"
+ {
+ .Instruction = ND_INS_FILD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 271,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:965 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FIMUL,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 272,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:966 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FIMUL,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 272,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:967 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/""
+ {
+ .Instruction = ND_INS_FINCSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 273,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:968 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FIST,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 274,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:969 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FIST,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 274,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:970 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FISTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 275,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:971 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FISTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 275,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:972 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FISTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 275,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:973 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FISTTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 276,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:974 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FISTTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 276,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:975 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FISTTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 276,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:976 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M"
+ {
+ .Instruction = ND_INS_FISUB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 277,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:977 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M"
+ {
+ .Instruction = ND_INS_FISUB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 277,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:978 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M"
+ {
+ .Instruction = ND_INS_FISUBR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 278,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:979 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M"
+ {
+ .Instruction = ND_INS_FISUBR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 278,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:980 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FLD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 279,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:981 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M"
+ {
+ .Instruction = ND_INS_FLD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 279,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:982 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M"
+ {
+ .Instruction = ND_INS_FLD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 279,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:983 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FLD,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 279,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:984 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/""
+ {
+ .Instruction = ND_INS_FLD1,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 280,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:985 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M"
+ {
+ .Instruction = ND_INS_FLDCW,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 281,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:986 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M"
+ {
+ .Instruction = ND_INS_FLDENV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 282,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:987 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/""
+ {
+ .Instruction = ND_INS_FLDL2E,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 283,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:988 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/""
+ {
+ .Instruction = ND_INS_FLDL2T,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 284,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:989 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/""
+ {
+ .Instruction = ND_INS_FLDLG2,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 285,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:990 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/""
+ {
+ .Instruction = ND_INS_FLDLN2,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 286,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:991 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/""
+ {
+ .Instruction = ND_INS_FLDPI,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 287,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:992 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/""
+ {
+ .Instruction = ND_INS_FLDZ,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 288,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:993 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FMUL,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 289,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:994 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FMUL,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 289,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:995 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FMUL,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 289,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:996 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FMUL,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 289,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:997 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FMULP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 290,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:998 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/""
+ {
+ .Instruction = ND_INS_FNCLEX,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 291,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:999 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/""
+ {
+ .Instruction = ND_INS_FNDISI,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 292,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1000 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/""
+ {
+ .Instruction = ND_INS_FNINIT,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 293,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0x00,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1001 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/""
+ {
+ .Instruction = ND_INS_FNOP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 294,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1002 Instruction:"FNOP" Encoding:"0xDB /0xE0"/""
+ {
+ .Instruction = ND_INS_FNOP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 294,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1003 Instruction:"FNOP" Encoding:"0xDB /0xE4"/""
+ {
+ .Instruction = ND_INS_FNOP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 294,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1004 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M"
+ {
+ .Instruction = ND_INS_FNSAVE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 295,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0x00,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1005 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FNSTCW,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 296,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1006 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_FNSTENV,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 297,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1007 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FNSTSW,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 298,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1008 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/""
+ {
+ .Instruction = ND_INS_FNSTSW,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 298,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1009 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/""
+ {
+ .Instruction = ND_INS_FPATAN,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 299,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1010 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/""
+ {
+ .Instruction = ND_INS_FPREM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 300,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1011 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/""
+ {
+ .Instruction = ND_INS_FPREM1,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 301,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1012 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/""
+ {
+ .Instruction = ND_INS_FPTAN,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 302,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xeb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1013 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/""
+ {
+ .Instruction = ND_INS_FRINEAR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 303,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1014 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/""
+ {
+ .Instruction = ND_INS_FRNDINT,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 304,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1015 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M"
+ {
+ .Instruction = ND_INS_FRSTOR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 305,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1016 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/""
+ {
+ .Instruction = ND_INS_FSCALE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 306,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1017 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/""
+ {
+ .Instruction = ND_INS_FSIN,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 307,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xeb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1018 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/""
+ {
+ .Instruction = ND_INS_FSINCOS,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 308,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xeb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1019 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/""
+ {
+ .Instruction = ND_INS_FSQRT,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 309,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1020 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FST,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 310,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1021 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M"
+ {
+ .Instruction = ND_INS_FST,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 310,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1022 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M"
+ {
+ .Instruction = ND_INS_FST,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 310,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1023 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/""
+ {
+ .Instruction = ND_INS_FSTDW,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 311,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1024 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 312,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1025 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M"
+ {
+ .Instruction = ND_INS_FSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 312,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1026 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M"
+ {
+ .Instruction = ND_INS_FSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 312,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1027 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M"
+ {
+ .Instruction = ND_INS_FSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 312,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1028 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M"
+ {
+ .Instruction = ND_INS_FSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 312,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1029 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M"
+ {
+ .Instruction = ND_INS_FSTP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 312,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1030 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M"
+ {
+ .Instruction = ND_INS_FSTPNCE,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 313,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1031 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/""
+ {
+ .Instruction = ND_INS_FSTSG,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 314,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1032 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M"
+ {
+ .Instruction = ND_INS_FSUB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 315,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1033 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M"
+ {
+ .Instruction = ND_INS_FSUB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 315,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1034 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M"
+ {
+ .Instruction = ND_INS_FSUB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 315,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1035 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M"
+ {
+ .Instruction = ND_INS_FSUB,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 315,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1036 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M"
+ {
+ .Instruction = ND_INS_FSUBP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 316,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1037 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M"
+ {
+ .Instruction = ND_INS_FSUBR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 317,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1038 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M"
+ {
+ .Instruction = ND_INS_FSUBR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 317,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1039 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M"
+ {
+ .Instruction = ND_INS_FSUBR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 317,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1040 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M"
+ {
+ .Instruction = ND_INS_FSUBR,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 317,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1041 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M"
+ {
+ .Instruction = ND_INS_FSUBRP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 318,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1042 Instruction:"FTST" Encoding:"0xD9 /0xE4"/""
+ {
+ .Instruction = ND_INS_FTST,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 319,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1043 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M"
+ {
+ .Instruction = ND_INS_FUCOM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 320,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1044 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M"
+ {
+ .Instruction = ND_INS_FUCOMI,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 321,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1045 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M"
+ {
+ .Instruction = ND_INS_FUCOMIP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 322,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xa2,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1046 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M"
+ {
+ .Instruction = ND_INS_FUCOMP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 323,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1047 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/""
+ {
+ .Instruction = ND_INS_FUCOMPP,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 324,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1048 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/""
+ {
+ .Instruction = ND_INS_FXAM,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 325,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xaa,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1049 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FXCH,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 326,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1050 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FXCH,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 326,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1051 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M"
+ {
+ .Instruction = ND_INS_FXCH,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 326,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xf3,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1052 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FXRSTOR,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_FXSAVE,
+ .Mnemonic = 327,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_FXSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1053 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M"
+ {
+ .Instruction = ND_INS_FXRSTOR64,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_FXSAVE,
+ .Mnemonic = 328,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_FXSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1054 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FXSAVE,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_FXSAVE,
+ .Mnemonic = 329,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_FXSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1055 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M"
+ {
+ .Instruction = ND_INS_FXSAVE64,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_FXSAVE,
+ .Mnemonic = 330,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_FXSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1056 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
+ {
+ .Instruction = ND_INS_FXTRACT,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 331,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1057 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
+ {
+ .Instruction = ND_INS_FYL2X,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 332,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1058 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
+ {
+ .Instruction = ND_INS_FYL2XP1,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 333,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xfb,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1059 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
+ {
+ .Instruction = ND_INS_GETSEC,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SMX,
+ .Mnemonic = 334,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = ND_CFF_SMX,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1060 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_GF2P8AFFINEINVQB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 335,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1061 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_GF2P8AFFINEQB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 336,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1062 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
+ {
+ .Instruction = ND_INS_GF2P8MULB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 337,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1063 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
+ {
+ .Instruction = ND_INS_HADDPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 338,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1064 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
+ {
+ .Instruction = ND_INS_HADDPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 339,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1065 Instruction:"HLT" Encoding:"0xF4"/""
+ {
+ .Instruction = ND_INS_HLT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 340,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1066 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I"
+ {
+ .Instruction = ND_INS_HRESET,
+ .Category = ND_CAT_HRESET,
+ .IsaSet = ND_SET_HRESET,
+ .Mnemonic = 341,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_HRESET,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1067 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
+ {
+ .Instruction = ND_INS_HSUBPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 342,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1068 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
+ {
+ .Instruction = ND_INS_HSUBPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 343,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1069 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1070 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1071 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1072 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1073 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1074 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1075 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1076 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
+ {
+ .Instruction = ND_INS_IDIV,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1077 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1078 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1079 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1080 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1081 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1082 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1083 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1084 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1085 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1086 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1087 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1088 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1089 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1090 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1091 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1092 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF|ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1093 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAF /r"/"RM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1094 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAF /r"/"RM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1095 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1096 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1097 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1098 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAF /r"/"RM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1099 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAF /r"/"RM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1100 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1101 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1102 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1103 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAF /r"/"VRM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1104 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAF /r"/"VRM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1105 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAF /r"/"VRM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1106 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAF /r"/"VRM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1107 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1108 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1109 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1110 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1111 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
+ {
+ .Instruction = ND_INS_IMUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1112 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
+ {
+ .Instruction = ND_INS_IN,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 346,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1113 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
+ {
+ .Instruction = ND_INS_IN,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 346,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1114 Instruction:"IN AL,DX" Encoding:"0xEC"/""
+ {
+ .Instruction = ND_INS_IN,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 346,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1115 Instruction:"IN eAX,DX" Encoding:"0xED"/""
+ {
+ .Instruction = ND_INS_IN,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 346,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1116 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1117 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1118 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1119 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1120 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1121 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1122 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /0"/"VM"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1123 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /0"/"VM"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1124 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /0"/"VM"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1125 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /0"/"VM"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1126 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /0"/"VM"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1127 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /0"/"VM"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1128 Instruction:"INC Zv" Encoding:"0x40"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1129 Instruction:"INC Zv" Encoding:"0x41"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1130 Instruction:"INC Zv" Encoding:"0x42"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1131 Instruction:"INC Zv" Encoding:"0x43"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1132 Instruction:"INC Zv" Encoding:"0x44"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1133 Instruction:"INC Zv" Encoding:"0x45"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1134 Instruction:"INC Zv" Encoding:"0x46"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1135 Instruction:"INC Zv" Encoding:"0x47"/"O"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1136 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1137 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
+ {
+ .Instruction = ND_INS_INC,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 347,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1138 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
+ {
+ .Instruction = ND_INS_INCSSP,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 348,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SHS, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1139 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
+ {
+ .Instruction = ND_INS_INCSSP,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 349,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SHS, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1140 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
+ {
+ .Instruction = ND_INS_INS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 350,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1141 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
+ {
+ .Instruction = ND_INS_INS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 350,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1142 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
+ {
+ .Instruction = ND_INS_INS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 351,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1143 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
+ {
+ .Instruction = ND_INS_INS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 351,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1144 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
+ {
+ .Instruction = ND_INS_INSERTPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 352,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1145 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_INSERTPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 352,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1146 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
+ {
+ .Instruction = ND_INS_INSERTQ,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_SSE4A,
+ .Mnemonic = 353,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4A,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1147 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_INSERTQ,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_SSE4A,
+ .Mnemonic = 353,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4A,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1148 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
+ {
+ .Instruction = ND_INS_INS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 354,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1149 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
+ {
+ .Instruction = ND_INS_INS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 354,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1150 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
+ {
+ .Instruction = ND_INS_INT,
+ .Category = ND_CAT_INTERRUPT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 355,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_VM,
+ .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_CETT,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1151 Instruction:"INT1" Encoding:"0xF1"/""
+ {
+ .Instruction = ND_INS_INT1,
+ .Category = ND_CAT_INTERRUPT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 356,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_VM,
+ .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1152 Instruction:"INT3" Encoding:"0xCC"/""
+ {
+ .Instruction = ND_INS_INT3,
+ .Category = ND_CAT_INTERRUPT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 357,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_VM,
+ .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_CETT,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1153 Instruction:"INTO" Encoding:"0xCE"/""
+ {
+ .Instruction = ND_INS_INTO,
+ .Category = ND_CAT_INTERRUPT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 358,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_VM,
+ .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_CETT|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1154 Instruction:"INVD" Encoding:"0x0F 0x08"/""
+ {
+ .Instruction = ND_INS_INVD,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 359,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1155 Instruction:"INVEPT Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_INVEPT,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 360,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INVEPT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1156 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_INVEPT,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 360,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1157 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
+ {
+ .Instruction = ND_INS_INVLPG,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 361,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_AG|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1158 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
+ {
+ .Instruction = ND_INS_INVLPGA,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 362,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1159 Instruction:"INVLPGB" Encoding:"NP 0x0F 0x01 /0xFE"/""
+ {
+ .Instruction = ND_INS_INVLPGB,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_INVLPGB,
+ .Mnemonic = 363,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_INVLPGB,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1160 Instruction:"INVPCID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF2 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_INVPCID,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 364,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INVPCID,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1161 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_INVPCID,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_INVPCID,
+ .Mnemonic = 364,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_INVPCID,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1162 Instruction:"INVVPID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF1 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_INVVPID,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 365,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INVVPID,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1163 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_INVVPID,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 365,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1164 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
+ {
+ .Instruction = ND_INS_IRET,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 366,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1165 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
+ {
+ .Instruction = ND_INS_IRET,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 367,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1166 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
+ {
+ .Instruction = ND_INS_IRET,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 368,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1167 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 369,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1168 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 369,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1169 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 370,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1170 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 370,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1171 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
+ {
+ .Instruction = ND_INS_JrCXZ,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 371,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ },
+ },
+
+ // Pos:1172 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
+ {
+ .Instruction = ND_INS_JrCXZ,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 372,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ },
+ },
+
+ // Pos:1173 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 373,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1174 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 373,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1175 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 374,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1176 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 374,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1177 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
+ {
+ .Instruction = ND_INS_JMPNR,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 375,
+ .ValidPrefixes = ND_PREF_BND,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1178 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
+ {
+ .Instruction = ND_INS_JMPNR,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 375,
+ .ValidPrefixes = ND_PREF_BND,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1179 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
+ {
+ .Instruction = ND_INS_JMPNI,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 375,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_DNT,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1180 Instruction:"JMPABS Aq" Encoding:"rex2 w:0 0xA1 cq"/"D"
+ {
+ .Instruction = ND_INS_JMPABS,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 376,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NO66|ND_FLAG_NO67|ND_FLAG_NOREP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_A, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1181 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M"
+ {
+ .Instruction = ND_INS_JMPE,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I64,
+ .Mnemonic = 377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1182 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
+ {
+ .Instruction = ND_INS_JMPE,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_I64,
+ .Mnemonic = 377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1183 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
+ {
+ .Instruction = ND_INS_JMPFD,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 378,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1184 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
+ {
+ .Instruction = ND_INS_JMPFI,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 378,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_CETT|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1185 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 379,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1186 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 379,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1187 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 380,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1188 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 380,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1189 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 381,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1190 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 381,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1191 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 382,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1192 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 382,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1193 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 383,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1194 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 383,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1195 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 384,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1196 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 384,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1197 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 385,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1198 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 385,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1199 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 386,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1200 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 386,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1201 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 387,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1202 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 387,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1203 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 388,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1204 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 388,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1205 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
+ {
+ .Instruction = ND_INS_JrCXZ,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 389,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ },
+ },
+
+ // Pos:1206 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 390,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1207 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 390,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1208 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 391,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1209 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
+ {
+ .Instruction = ND_INS_Jcc,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 391,
+ .ValidPrefixes = ND_PREF_BND|ND_PREF_BH,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1210 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KADD,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 392,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1211 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KADD,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 393,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1212 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KADD,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 394,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1213 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KADD,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 395,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1214 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KAND,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 396,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1215 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KAND,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 397,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1216 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KANDN,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 398,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1217 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KANDN,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 399,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1218 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KANDN,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 400,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1219 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KANDN,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 401,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1220 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KAND,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 402,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1221 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KAND,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 403,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1222 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMERGE2L1H,
+ .Category = ND_CAT_UNKNOWN,
+ .IsaSet = ND_SET_UNKNOWN,
+ .Mnemonic = 404,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1223 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMERGE2L1L,
+ .Category = ND_CAT_UNKNOWN,
+ .IsaSet = ND_SET_UNKNOWN,
+ .Mnemonic = 405,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1224 Instruction:"KMOVB rKb,Mb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1225 Instruction:"KMOVB rKb,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1226 Instruction:"KMOVB Mb,rKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1227 Instruction:"KMOVB rKb,Ry" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1228 Instruction:"KMOVB Gy,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1229 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1230 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1231 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1232 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1233 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1234 Instruction:"KMOVD rKd,Md" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1235 Instruction:"KMOVD rKd,mKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1236 Instruction:"KMOVD Md,rKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1237 Instruction:"KMOVD rKd,Ry" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1238 Instruction:"KMOVD Gy,mKd" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1239 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1240 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1241 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1242 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1243 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1244 Instruction:"KMOVQ rKq,Mq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1245 Instruction:"KMOVQ rKq,mKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1246 Instruction:"KMOVQ Mq,rKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1247 Instruction:"KMOVQ rKq,Ry" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1248 Instruction:"KMOVQ Gy,mKq" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1249 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1250 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1251 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1252 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1253 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1254 Instruction:"KMOVW rKw,Mw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1255 Instruction:"KMOVW rKw,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1256 Instruction:"KMOVW Mw,rKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1257 Instruction:"KMOVW rKw,Ry" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1258 Instruction:"KMOVW Gy,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_KMOV,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1259 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1260 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1261 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K21,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1262 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1263 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KMOV,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1264 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KNOT,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 410,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1265 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KNOT,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 411,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1266 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KNOT,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 412,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1267 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KNOT,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 413,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1268 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 414,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1269 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 415,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1270 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 416,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1271 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KORTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 417,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1272 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KORTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 418,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1273 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KORTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 419,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1274 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KORTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 420,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1275 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 421,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1276 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTL,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 422,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1277 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTL,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 423,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1278 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTL,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 424,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1279 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTL,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 425,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1280 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 426,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1281 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 427,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1282 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 428,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1283 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_KSHIFTR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 429,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1284 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 430,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1285 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 431,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1286 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 432,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1287 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_KTEST,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 433,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1288 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KUNPCKBW,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 434,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1289 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KUNPCKDQ,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 435,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1290 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KUNPCKWD,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 436,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1291 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXNOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 437,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1292 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXNOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 438,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1293 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXNOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 439,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1294 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXNOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 440,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1295 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 441,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1296 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 442,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1297 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 443,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1298 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_KXOR,
+ .Category = ND_CAT_KMASK,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 444,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_K20,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1299 Instruction:"LAHF" Encoding:"0x9F"/""
+ {
+ .Instruction = ND_INS_LAHF,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 445,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1300 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LAR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 446,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1301 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_LAR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 446,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1302 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LDDQU,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 447,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1303 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
+ {
+ .Instruction = ND_INS_LDMXCSR,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 448,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1304 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LDS,
+ .Category = ND_CAT_SEGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 449,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_DS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1305 Instruction:"LDTILECFG Moq" Encoding:"evex m:2 p:0 l:0 nf:0 w:0 0x49 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_LDTILECFG,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 450,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E1,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1306 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_LDTILECFG,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTILE,
+ .Mnemonic = 450,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTILE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1307 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LEA,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 451,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_AG|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_0, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1308 Instruction:"LEAVE" Encoding:"0xC9"/""
+ {
+ .Instruction = ND_INS_LEAVE,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_I186,
+ .Mnemonic = 452,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rBP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1309 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LES,
+ .Category = ND_CAT_SEGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 453,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_ES, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1310 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
+ {
+ .Instruction = ND_INS_LFENCE,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 454,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1311 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LFS,
+ .Category = ND_CAT_SEGOP,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 455,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_FS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1312 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
+ {
+ .Instruction = ND_INS_LGDT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 456,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_GDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1313 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LGS,
+ .Category = ND_CAT_SEGOP,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 457,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_GS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1314 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_LIDT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 458,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_IDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1315 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_LKGS,
+ .Category = ND_CAT_LKGS,
+ .IsaSet = ND_SET_LKGS,
+ .Mnemonic = 459,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_LKGS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1316 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M"
+ {
+ .Instruction = ND_INS_LKGS,
+ .Category = ND_CAT_LKGS,
+ .IsaSet = ND_SET_LKGS,
+ .Mnemonic = 459,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_LKGS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1317 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
+ {
+ .Instruction = ND_INS_LLDT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 460,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1318 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
+ {
+ .Instruction = ND_INS_LLWPCB,
+ .Category = ND_CAT_LWP,
+ .IsaSet = ND_SET_LWP,
+ .Mnemonic = 461,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_LWP,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1319 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
+ {
+ .Instruction = ND_INS_LMSW,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 462,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1320 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_LOADIWKEY,
+ .Category = ND_CAT_KL,
+ .IsaSet = ND_SET_KL,
+ .Mnemonic = 463,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_KL,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1321 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 464,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1322 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 464,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1323 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 465,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1324 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 465,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1325 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 466,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1326 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 466,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1327 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 467,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1328 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/""
+ {
+ .Instruction = ND_INS_LODS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 467,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1329 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D"
+ {
+ .Instruction = ND_INS_LOOP,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 468,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1330 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D"
+ {
+ .Instruction = ND_INS_LOOPNZ,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 469,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1331 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D"
+ {
+ .Instruction = ND_INS_LOOPZ,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 470,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1332 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LSL,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 471,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1333 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_LSL,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 471,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1334 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_LSS,
+ .Category = ND_CAT_SEGOP,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 472,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1335 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M"
+ {
+ .Instruction = ND_INS_LTR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 473,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1336 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI"
+ {
+ .Instruction = ND_INS_LWPINS,
+ .Category = ND_CAT_LWP,
+ .IsaSet = ND_SET_LWP,
+ .Mnemonic = 474,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_LWP,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1337 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI"
+ {
+ .Instruction = ND_INS_LWPVAL,
+ .Category = ND_CAT_LWP,
+ .IsaSet = ND_SET_LWP,
+ .Mnemonic = 475,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_LWP,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1338 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF5 /r"/"RM"
+ {
+ .Instruction = ND_INS_LZCNT,
+ .Category = ND_CAT_LZCNT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 476,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1339 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF5 /r"/"RM"
+ {
+ .Instruction = ND_INS_LZCNT,
+ .Category = ND_CAT_LZCNT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 476,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1340 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF5 /r"/"RM"
+ {
+ .Instruction = ND_INS_LZCNT,
+ .Category = ND_CAT_LZCNT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 476,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1341 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF5 /r"/"RM"
+ {
+ .Instruction = ND_INS_LZCNT,
+ .Category = ND_CAT_LZCNT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 476,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1342 Instruction:"LZCNT Gv,Ev" Encoding:"repz 0x0F 0xBD /r"/"RM"
+ {
+ .Instruction = ND_INS_LZCNT,
+ .Category = ND_CAT_LZCNT,
+ .IsaSet = ND_SET_LZCNT,
+ .Mnemonic = 476,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_LZCNT,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1343 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MASKMOVDQU,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 477,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_pDI, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1344 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MASKMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 478,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_pDI, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1345 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM"
+ {
+ .Instruction = ND_INS_MAXPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 479,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1346 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM"
+ {
+ .Instruction = ND_INS_MAXPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 480,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1347 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM"
+ {
+ .Instruction = ND_INS_MAXSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 481,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1348 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM"
+ {
+ .Instruction = ND_INS_MAXSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 482,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1349 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/""
+ {
+ .Instruction = ND_INS_MCOMMIT,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_MCOMMIT,
+ .Mnemonic = 483,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MCOMMIT,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1350 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/""
+ {
+ .Instruction = ND_INS_MFENCE,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 484,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1351 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM"
+ {
+ .Instruction = ND_INS_MINPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 485,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1352 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM"
+ {
+ .Instruction = ND_INS_MINPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 486,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1353 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM"
+ {
+ .Instruction = ND_INS_MINSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 487,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1354 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM"
+ {
+ .Instruction = ND_INS_MINSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 488,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1355 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/""
+ {
+ .Instruction = ND_INS_MONITOR,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 489,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MONITOR,
+ .Operands =
+ {
+ OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1356 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/""
+ {
+ .Instruction = ND_INS_MONITORX,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MWAITT,
+ .Mnemonic = 490,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1357 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1358 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1359 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1360 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1361 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1362 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1363 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1364 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1365 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1366 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1367 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1368 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1369 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1370 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1371 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1372 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1373 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1374 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1375 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1376 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1377 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1378 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1379 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1380 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1381 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1382 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1383 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1384 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1385 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1386 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_MOV,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1387 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOV_CR,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LOCKSP|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1388 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOV_DR,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1389 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOV_CR,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LOCKSP|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1390 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOV_DR,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1391 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOV_TR,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1392 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOV_TR,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1393 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVAPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 492,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1394 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVAPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 492,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1395 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVAPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 493,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1396 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVAPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 493,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1397 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x60 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1398 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x60 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1399 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x61 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1400 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x61 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1401 Instruction:"MOVBE Gv,Mv" Encoding:"NP 0x0F 0x38 0xF0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVBE,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVBE,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1402 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVBE,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_S66|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVBE,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1403 Instruction:"MOVBE Mv,Gv" Encoding:"NP 0x0F 0x38 0xF1 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVBE,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVBE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1404 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVBE,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVBE,
+ .Mnemonic = 494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_S66|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVBE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1405 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 495,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1406 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 495,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1407 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 495,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_P, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1408 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 495,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1409 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVDDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 496,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1410 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF8 /r:mem"/"M"
+ {
+ .Instruction = ND_INS_MOVDIR64B,
+ .Category = ND_CAT_MOVDIR64B,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 497,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1411 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M"
+ {
+ .Instruction = ND_INS_MOVDIR64B,
+ .Category = ND_CAT_MOVDIR64B,
+ .IsaSet = ND_SET_MOVDIR64B,
+ .Mnemonic = 497,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVDIR64B,
+ .Operands =
+ {
+ OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1412 Instruction:"MOVDIRI My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF9 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVDIRI,
+ .Category = ND_CAT_MOVDIRI,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 498,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1413 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVDIRI,
+ .Category = ND_CAT_MOVDIRI,
+ .IsaSet = ND_SET_MOVDIRI,
+ .Mnemonic = 498,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVDIRI,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1414 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MOVDQ2Q,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 499,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1415 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVDQA,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 500,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1416 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVDQA,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 500,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1417 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVDQU,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 501,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1418 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVDQU,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 501,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1419 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVHLPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 502,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1420 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVHPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 503,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1421 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVHPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 503,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1422 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 504,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1423 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 504,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1424 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MOVLHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 505,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1425 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVLPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 506,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1426 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVLPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 506,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1427 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVLPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 507,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1428 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MOVMSKPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 508,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1429 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MOVMSKPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 509,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1430 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVNTDQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 510,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1431 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVNTDQA,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 511,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1432 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVNTI,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 512,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1433 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVNTPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 513,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1434 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVNTPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 514,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1435 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVNTQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 515,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1436 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVNTSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE4A,
+ .Mnemonic = 516,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4A,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1437 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_MOVNTSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE4A,
+ .Mnemonic = 517,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4A,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1438 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1439 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1440 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1441 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1442 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1443 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1444 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1445 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1446 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_MOVQ2DQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 519,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1447 Instruction:"MOVRS Gb,Mb" Encoding:"0x0F 0x38 0x8A /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVRS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 520,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREP|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1448 Instruction:"MOVRS Gv,Mv" Encoding:"0x0F 0x38 0x8B /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_MOVRS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 520,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREP|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1449 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 521,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1450 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 521,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1451 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 522,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1452 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 522,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1453 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 522,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1454 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 522,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1455 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVSHDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 523,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1456 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVSLDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 524,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1457 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 525,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1458 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 525,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1459 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 526,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1460 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 526,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1461 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 527,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1462 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/""
+ {
+ .Instruction = ND_INS_MOVS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 527,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1463 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVSX,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 528,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1464 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVSX,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 528,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1465 Instruction:"MOVSXD Gv,Ez" Encoding:"mo64 0x63 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVSXD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_LONGMODE,
+ .Mnemonic = 529,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1466 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVUPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 530,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1467 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVUPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 530,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1468 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVUPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 531,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1469 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_MOVUPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 531,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1470 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVZX,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 532,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1471 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM"
+ {
+ .Instruction = ND_INS_MOVZX,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 532,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1472 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_MPSADBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 533,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1473 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1474 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1475 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1476 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1477 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1478 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1479 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1480 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M"
+ {
+ .Instruction = ND_INS_MUL,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1481 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM"
+ {
+ .Instruction = ND_INS_MULPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 535,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1482 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM"
+ {
+ .Instruction = ND_INS_MULPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 536,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1483 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM"
+ {
+ .Instruction = ND_INS_MULSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 537,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1484 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM"
+ {
+ .Instruction = ND_INS_MULSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 538,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1485 Instruction:"MULX Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_MULX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 539,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1486 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_MULX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 539,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1487 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/""
+ {
+ .Instruction = ND_INS_MWAIT,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_SSE3,
+ .Mnemonic = 540,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MONITOR,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1488 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/""
+ {
+ .Instruction = ND_INS_MWAITX,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MWAITT,
+ .Mnemonic = 541,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1489 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1490 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1491 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1492 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1493 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1494 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1495 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3"/"VM"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1496 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3"/"VM"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1497 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3"/"VM"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1498 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3"/"VM"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1499 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3"/"VM"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1500 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3"/"VM"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1501 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 542,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1502 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M"
+ {
+ .Instruction = ND_INS_NEG,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 542,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1503 Instruction:"NOP" Encoding:"0x90"/""
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1504 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1505 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1506 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1507 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1508 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1509 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1510 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1511 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_NOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1512 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1513 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1514 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1515 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1516 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1517 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1518 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1519 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1520 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1521 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1522 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1523 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1524 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1525 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1526 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1527 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1528 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1529 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1530 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1531 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1532 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1533 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1534 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1535 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1536 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1537 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1A /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1538 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1B /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1539 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1540 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1541 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1542 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1543 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1544 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1545 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1546 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1547 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1548 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1549 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1550 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1551 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /0:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1552 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1553 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /1:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1554 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1555 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /2:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1556 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1557 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /3:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1558 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1559 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /4:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1560 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1561 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /5:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1562 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1563 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /6:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1564 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1565 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /7:mem"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1566 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1567 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1568 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1569 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1570 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1571 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1572 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1573 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR"
+ {
+ .Instruction = ND_INS_NOP,
+ .Category = ND_CAT_WIDENOP,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1574 Instruction:"NOT Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2"/"M"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 544,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1575 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2"/"M"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 544,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1576 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2"/"M"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 544,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1577 Instruction:"NOT Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2"/"VM"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 544,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1578 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2"/"VM"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 544,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1579 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2"/"VM"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 544,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1580 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 544,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1581 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M"
+ {
+ .Instruction = ND_INS_NOT,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 544,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1582 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1583 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1584 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1585 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1586 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1587 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1588 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1589 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1590 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1591 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1592 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1593 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1594 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1595 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1596 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1597 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1598 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1599 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1600 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1601 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1602 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1603 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1604 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r"/"VMR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1605 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r"/"VMR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1606 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r"/"VMR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1607 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r"/"VRM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1608 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r"/"VRM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1609 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r"/"VRM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1610 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1611 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1612 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1613 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1614 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1615 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r"/"VMR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1616 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r"/"VMR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1617 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r"/"VMR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1618 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r"/"VRM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1619 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r"/"VRM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1620 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r"/"VRM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1621 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1622 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1623 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1624 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1625 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1626 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1627 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1628 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1629 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1630 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1631 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1632 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1633 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1634 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1635 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_OR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 545,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1636 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM"
+ {
+ .Instruction = ND_INS_ORPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 546,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1637 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM"
+ {
+ .Instruction = ND_INS_ORPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 547,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1638 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I"
+ {
+ .Instruction = ND_INS_OUT,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 548,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1639 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I"
+ {
+ .Instruction = ND_INS_OUT,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 548,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1640 Instruction:"OUT DX,AL" Encoding:"0xEE"/""
+ {
+ .Instruction = ND_INS_OUT,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 548,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1641 Instruction:"OUT DX,eAX" Encoding:"0xEF"/""
+ {
+ .Instruction = ND_INS_OUT,
+ .Category = ND_CAT_IO,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 548,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1642 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/""
+ {
+ .Instruction = ND_INS_OUTS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 549,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1643 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/""
+ {
+ .Instruction = ND_INS_OUTS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 549,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1644 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/""
+ {
+ .Instruction = ND_INS_OUTS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 550,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1645 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/""
+ {
+ .Instruction = ND_INS_OUTS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 550,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1646 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/""
+ {
+ .Instruction = ND_INS_OUTS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 551,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1647 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/""
+ {
+ .Instruction = ND_INS_OUTS,
+ .Category = ND_CAT_IOSTRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 551,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1648 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM"
+ {
+ .Instruction = ND_INS_PABSB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 552,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1649 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM"
+ {
+ .Instruction = ND_INS_PABSB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 552,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1650 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM"
+ {
+ .Instruction = ND_INS_PABSD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 553,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1651 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM"
+ {
+ .Instruction = ND_INS_PABSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 553,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1652 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM"
+ {
+ .Instruction = ND_INS_PABSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 554,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1653 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM"
+ {
+ .Instruction = ND_INS_PABSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 554,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1654 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM"
+ {
+ .Instruction = ND_INS_PACKSSDW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 555,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1655 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM"
+ {
+ .Instruction = ND_INS_PACKSSDW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 555,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1656 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM"
+ {
+ .Instruction = ND_INS_PACKSSWB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 556,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1657 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM"
+ {
+ .Instruction = ND_INS_PACKSSWB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 556,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1658 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM"
+ {
+ .Instruction = ND_INS_PACKUSDW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 557,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1659 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM"
+ {
+ .Instruction = ND_INS_PACKUSWB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 558,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1660 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM"
+ {
+ .Instruction = ND_INS_PACKUSWB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 558,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1661 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 559,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1662 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 559,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1663 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 560,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1664 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 560,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1665 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 561,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1666 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 561,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1667 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDSB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 562,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1668 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDSB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 562,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1669 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 563,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1670 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 563,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1671 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDUSB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 564,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1672 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDUSB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 564,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1673 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDUSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 565,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1674 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDUSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 565,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1675 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 566,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1676 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM"
+ {
+ .Instruction = ND_INS_PADDW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 566,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1677 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PALIGNR,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 567,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1678 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PALIGNR,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 567,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1679 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM"
+ {
+ .Instruction = ND_INS_PAND,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 568,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1680 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM"
+ {
+ .Instruction = ND_INS_PAND,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 568,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1681 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM"
+ {
+ .Instruction = ND_INS_PANDN,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 569,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1682 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM"
+ {
+ .Instruction = ND_INS_PANDN,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 569,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1683 Instruction:"PAUSE" Encoding:"repz 0x90"/""
+ {
+ .Instruction = ND_INS_PAUSE,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_PAUSE,
+ .Mnemonic = 570,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:1684 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM"
+ {
+ .Instruction = ND_INS_PAVGB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 571,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1685 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM"
+ {
+ .Instruction = ND_INS_PAVGB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 571,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1686 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM"
+ {
+ .Instruction = ND_INS_PAVGUSB,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 572,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1687 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM"
+ {
+ .Instruction = ND_INS_PAVGW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 573,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1688 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM"
+ {
+ .Instruction = ND_INS_PAVGW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 573,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1689 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM"
+ {
+ .Instruction = ND_INS_PBLENDVB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 574,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1690 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PBLENDW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 575,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1691 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/""
+ {
+ .Instruction = ND_INS_PBNDKB,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_TSE,
+ .Mnemonic = 576,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_TSE,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1692 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PCLMULQDQ,
+ .Category = ND_CAT_PCLMULQDQ,
+ .IsaSet = ND_SET_PCLMULQDQ,
+ .Mnemonic = 577,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_PCLMULQDQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1693 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPEQB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 578,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1694 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPEQB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 578,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1695 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPEQD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 579,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1696 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPEQD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 579,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1697 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPEQQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 580,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1698 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPEQW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 581,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1699 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPEQW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 581,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1700 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PCMPESTRI,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE42,
+ .Mnemonic = 582,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 4),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE42,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1701 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PCMPESTRM,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE42,
+ .Mnemonic = 583,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 4),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE42,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1702 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPGTB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 584,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1703 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPGTB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 584,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1704 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPGTD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 585,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1705 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPGTD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 585,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1706 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPGTQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE42,
+ .Mnemonic = 586,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE42,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1707 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPGTW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 587,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1708 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
+ {
+ .Instruction = ND_INS_PCMPGTW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 587,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1709 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PCMPISTRI,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE42,
+ .Mnemonic = 588,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE42,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1710 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PCMPISTRM,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE42,
+ .Mnemonic = 589,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE42,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1711 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
+ {
+ .Instruction = ND_INS_PCONFIG,
+ .Category = ND_CAT_PCONFIG,
+ .IsaSet = ND_SET_PCONFIG,
+ .Mnemonic = 590,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_PCONFIG,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1712 Instruction:"PDEP Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_PDEP,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 591,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1713 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_PDEP,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 591,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1714 Instruction:"PEXT Gy,By,Ey" Encoding:"evex m:2 p:2 l:0 nf:0 0xF5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_PEXT,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 592,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1715 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_PEXT,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 592,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1716 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 593,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1717 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 593,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1718 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 594,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1719 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 594,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1720 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 595,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1721 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 595,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1722 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_PEXTRW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 596,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1723 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_PEXTRW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 596,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1724 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 596,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1725 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_PEXTRW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 596,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1726 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
+ {
+ .Instruction = ND_INS_PF2ID,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 597,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1727 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
+ {
+ .Instruction = ND_INS_PF2IW,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 598,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1728 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
+ {
+ .Instruction = ND_INS_PFACC,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 599,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1729 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
+ {
+ .Instruction = ND_INS_PFADD,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 600,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1730 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
+ {
+ .Instruction = ND_INS_PFCMPEQ,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 601,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1731 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
+ {
+ .Instruction = ND_INS_PFCMPGE,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 602,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1732 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
+ {
+ .Instruction = ND_INS_PFCMPGT,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 603,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1733 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
+ {
+ .Instruction = ND_INS_PFMAX,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 604,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1734 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
+ {
+ .Instruction = ND_INS_PFMIN,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 605,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1735 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
+ {
+ .Instruction = ND_INS_PFMUL,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 606,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1736 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
+ {
+ .Instruction = ND_INS_PFNACC,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 607,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1737 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
+ {
+ .Instruction = ND_INS_PFPNACC,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 608,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1738 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
+ {
+ .Instruction = ND_INS_PFRCP,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 609,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1739 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
+ {
+ .Instruction = ND_INS_PFRCPIT1,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 610,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1740 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
+ {
+ .Instruction = ND_INS_PFRCPIT2,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 611,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1741 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
+ {
+ .Instruction = ND_INS_PFRCPV,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 612,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1742 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
+ {
+ .Instruction = ND_INS_PFRSQIT1,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 613,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1743 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
+ {
+ .Instruction = ND_INS_PFRSQRT,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 614,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1744 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
+ {
+ .Instruction = ND_INS_PFRSQRTV,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 615,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1745 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
+ {
+ .Instruction = ND_INS_PFSUB,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 616,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1746 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
+ {
+ .Instruction = ND_INS_PFSUBR,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 617,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1747 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHADDD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 618,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1748 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHADDD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 618,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1749 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHADDSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 619,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1750 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHADDSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 619,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1751 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHADDW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 620,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1752 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHADDW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 620,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1753 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHMINPOSUW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 621,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1754 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHSUBD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 622,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1755 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHSUBD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 622,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1756 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHSUBSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 623,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1757 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHSUBSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 623,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1758 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHSUBW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 624,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1759 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
+ {
+ .Instruction = ND_INS_PHSUBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 624,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1760 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
+ {
+ .Instruction = ND_INS_PI2FD,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 625,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1761 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
+ {
+ .Instruction = ND_INS_PI2FW,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 626,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1762 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 627,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1763 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 627,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1764 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 628,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1765 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 629,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1766 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 630,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1767 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 630,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1768 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 630,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1769 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
+ {
+ .Instruction = ND_INS_PINSRW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 630,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1770 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMADDUBSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 631,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1771 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMADDUBSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 631,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1772 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMADDWD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 632,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1773 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMADDWD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 632,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1774 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXSB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 633,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1775 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 634,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1776 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 635,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1777 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 635,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1778 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXUB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 636,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1779 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXUB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 636,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1780 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXUD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 637,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1781 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
+ {
+ .Instruction = ND_INS_PMAXUW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 638,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1782 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINSB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 639,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1783 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 640,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1784 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 641,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1785 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 641,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1786 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINUB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 642,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1787 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINUB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 642,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1788 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINUD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 643,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1789 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
+ {
+ .Instruction = ND_INS_PMINUW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 644,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1790 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_PMOVMSKB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 645,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1791 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_PMOVMSKB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 645,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1792 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVSXBD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 646,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1793 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVSXBQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 647,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1794 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVSXBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 648,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1795 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVSXDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 649,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1796 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVSXWD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 650,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1797 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVSXWQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 651,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1798 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVZXBD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 652,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1799 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVZXBQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 653,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1800 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVZXBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 654,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1801 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVZXDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 655,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1802 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVZXWD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 656,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1803 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMOVZXWQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 657,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1804 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 658,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1805 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULHRSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 659,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1806 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULHRSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 659,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1807 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
+ {
+ .Instruction = ND_INS_PMULHRW,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 660,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1808 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULHUW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 661,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1809 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULHUW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 661,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1810 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULHW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 662,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1811 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULHW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 662,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1812 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULLD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 663,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1813 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULLW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 664,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1814 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULLW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 664,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1815 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULUDQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 665,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1816 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
+ {
+ .Instruction = ND_INS_PMULUDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 665,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1817 Instruction:"POP ES" Encoding:"0x07"/""
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ES, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1818 Instruction:"POP SS" Encoding:"0x17"/""
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_SS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1819 Instruction:"POP DS" Encoding:"0x1F"/""
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_DS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1820 Instruction:"POP Zv" Encoding:"0x58"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1821 Instruction:"POP Zv" Encoding:"0x59"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1822 Instruction:"POP Zv" Encoding:"0x5A"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1823 Instruction:"POP Zv" Encoding:"0x5B"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1824 Instruction:"POP Zv" Encoding:"0x5C"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1825 Instruction:"POP Zv" Encoding:"0x5D"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1826 Instruction:"POP Zv" Encoding:"0x5E"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1827 Instruction:"POP Zv" Encoding:"0x5F"/"O"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1828 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1829 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_FS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1830 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
+ {
+ .Instruction = ND_INS_POP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_GS, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1831 Instruction:"POP2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg"/"VM"
+ {
+ .Instruction = ND_INS_POP2,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 667,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_PP2,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1832 Instruction:"POP2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg"/"VM"
+ {
+ .Instruction = ND_INS_POP2P,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 668,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_PP2,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1833 Instruction:"POPA" Encoding:"ds16 0x61"/""
+ {
+ .Instruction = ND_INS_POPA,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 669,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1834 Instruction:"POPAD" Encoding:"ds32 0x61"/""
+ {
+ .Instruction = ND_INS_POPAD,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 670,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1835 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r"/"RM"
+ {
+ .Instruction = ND_INS_POPCNT,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 671,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1836 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r"/"RM"
+ {
+ .Instruction = ND_INS_POPCNT,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 671,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1837 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r"/"RM"
+ {
+ .Instruction = ND_INS_POPCNT,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 671,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1838 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r"/"RM"
+ {
+ .Instruction = ND_INS_POPCNT,
+ .Category = ND_CAT_APX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 671,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1839 Instruction:"POPCNT Gv,Ev" Encoding:"repz 0x0F 0xB8 /r"/"RM"
+ {
+ .Instruction = ND_INS_POPCNT,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_POPCNT,
+ .Mnemonic = 671,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_POPCNT,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1840 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
+ {
+ .Instruction = ND_INS_POPF,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 672,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1841 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
+ {
+ .Instruction = ND_INS_POPF,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 673,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1842 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
+ {
+ .Instruction = ND_INS_POPF,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 674,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1843 Instruction:"POPP Zv" Encoding:"rex2w 0x58"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1844 Instruction:"POPP Zv" Encoding:"rex2w 0x59"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1845 Instruction:"POPP Zv" Encoding:"rex2w 0x5A"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1846 Instruction:"POPP Zv" Encoding:"rex2w 0x5B"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1847 Instruction:"POPP Zv" Encoding:"rex2w 0x5C"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1848 Instruction:"POPP Zv" Encoding:"rex2w 0x5D"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1849 Instruction:"POPP Zv" Encoding:"rex2w 0x5E"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1850 Instruction:"POPP Zv" Encoding:"rex2w 0x5F"/"O"
+ {
+ .Instruction = ND_INS_POPP,
+ .Category = ND_CAT_POP,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1851 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
+ {
+ .Instruction = ND_INS_POR,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 676,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1852 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
+ {
+ .Instruction = ND_INS_POR,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 676,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1853 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCH,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 677,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1854 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCH,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 677,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1855 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCH,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 677,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1856 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCH,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 677,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1857 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHE,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 678,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1858 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHIT0,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCHITI,
+ .Mnemonic = 679,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_PREFETCHITI,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1859 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHIT1,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCHITI,
+ .Mnemonic = 680,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_PREFETCHITI,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0),
+ },
+ },
+
+ // Pos:1860 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHM,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 681,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1861 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHNTA,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 682,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1862 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHNTA,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 682,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1863 Instruction:"PREFETCHRST2 Mb" Encoding:"0x0F 0x18 /4:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHRST2,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 683,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1864 Instruction:"PREFETCHRST2 Mb" Encoding:"piti 0x0F 0x18 /4:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHRST2,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 683,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1865 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHT0,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 684,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1866 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHT0,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 684,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1867 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHT1,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 685,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1868 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHT1,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 685,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1869 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHT2,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 686,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1870 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHT2,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 686,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1871 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHW,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 687,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1872 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
+ {
+ .Instruction = ND_INS_PREFETCHWT1,
+ .Category = ND_CAT_PREFETCH,
+ .IsaSet = ND_SET_PREFETCH_NOP,
+ .Mnemonic = 688,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0),
+ },
+ },
+
+ // Pos:1873 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSADBW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 689,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1874 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSADBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 689,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1875 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSHUFB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 690,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1876 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSHUFB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 690,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1877 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PSHUFD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 691,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1878 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PSHUFHW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 692,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1879 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PSHUFLW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 693,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1880 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_PSHUFW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 694,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1881 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSIGNB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 695,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1882 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSIGNB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 695,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1883 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
+ {
+ .Instruction = ND_INS_PSIGND,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 696,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1884 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
+ {
+ .Instruction = ND_INS_PSIGND,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 696,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1885 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSIGNW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 697,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1886 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSIGNW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSSE3,
+ .Mnemonic = 697,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSSE3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1887 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSLLD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 698,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1888 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSLLD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 698,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1889 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSLLD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 698,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1890 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSLLD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 698,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1891 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSLLDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 699,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1892 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSLLQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 700,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1893 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSLLQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 700,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1894 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSLLQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 700,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1895 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSLLQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 700,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1896 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSLLW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 701,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1897 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSLLW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 701,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1898 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSLLW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 701,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1899 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSLLW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 701,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1900 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
+ {
+ .Instruction = ND_INS_PSMASH,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SNP,
+ .Mnemonic = 702,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_SNP,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1901 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRAD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 703,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1902 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRAD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 703,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1903 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRAD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 703,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1904 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRAD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 703,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1905 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRAW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1906 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRAW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1907 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRAW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1908 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRAW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1909 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRLD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 705,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1910 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRLD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 705,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1911 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRLD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 705,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1912 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRLD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 705,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1913 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRLDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 706,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1914 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRLQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 707,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1915 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRLQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 707,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1916 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRLQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 707,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1917 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRLQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 707,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1918 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRLW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1919 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
+ {
+ .Instruction = ND_INS_PSRLW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1920 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRLW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1921 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSRLW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1922 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 709,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1923 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 709,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1924 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 710,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1925 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 710,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1926 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 711,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1927 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 711,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1928 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBSB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 712,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1929 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBSB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 712,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1930 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 713,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1931 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 713,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1932 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBUSB,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 714,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1933 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBUSB,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 714,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1934 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBUSW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 715,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1935 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBUSW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 715,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1936 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 716,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1937 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
+ {
+ .Instruction = ND_INS_PSUBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 716,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1938 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
+ {
+ .Instruction = ND_INS_PSWAPD,
+ .Category = ND_CAT_3DNOW,
+ .IsaSet = ND_SET_3DNOW,
+ .Mnemonic = 717,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_3DNOW,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1939 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
+ {
+ .Instruction = ND_INS_PTEST,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 718,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1940 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
+ {
+ .Instruction = ND_INS_PTWRITE,
+ .Category = ND_CAT_PTWRITE,
+ .IsaSet = ND_SET_PTWRITE,
+ .Mnemonic = 719,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NO66|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_PTWRITE,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1941 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKHBW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 720,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1942 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKHBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 720,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1943 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKHDQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 721,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1944 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKHDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 721,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1945 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKHQDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 722,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1946 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKHWD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 723,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1947 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKHWD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 723,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1948 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKLBW,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 724,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1949 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKLBW,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 724,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1950 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKLDQ,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 725,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1951 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKLDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 725,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1952 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKLQDQ,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 726,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1953 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKLWD,
+ .Category = ND_CAT_MMX,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 727,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1954 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
+ {
+ .Instruction = ND_INS_PUNPCKLWD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 727,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1955 Instruction:"PUSH ES" Encoding:"0x06"/""
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_ES, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1956 Instruction:"PUSH CS" Encoding:"0x0E"/""
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1957 Instruction:"PUSH SS" Encoding:"0x16"/""
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_SS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1958 Instruction:"PUSH DS" Encoding:"0x1E"/""
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_DS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1959 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1960 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1961 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1962 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1963 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1964 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1965 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1966 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1967 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXDW, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1968 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXDW, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1969 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1970 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_FS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1971 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
+ {
+ .Instruction = ND_INS_PUSH,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_GS, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1972 Instruction:"PUSH2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg"/"VM"
+ {
+ .Instruction = ND_INS_PUSH2,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 729,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_PP2,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1973 Instruction:"PUSH2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg"/"VM"
+ {
+ .Instruction = ND_INS_PUSH2P,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 730,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_PP2,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1974 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
+ {
+ .Instruction = ND_INS_PUSHA,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 731,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1975 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
+ {
+ .Instruction = ND_INS_PUSHAD,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 732,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1976 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
+ {
+ .Instruction = ND_INS_PUSHF,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 733,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1977 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
+ {
+ .Instruction = ND_INS_PUSHF,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 734,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1978 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
+ {
+ .Instruction = ND_INS_PUSHF,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 735,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1979 Instruction:"PUSHP Zv" Encoding:"rex2w 0x50"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1980 Instruction:"PUSHP Zv" Encoding:"rex2w 0x51"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1981 Instruction:"PUSHP Zv" Encoding:"rex2w 0x52"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1982 Instruction:"PUSHP Zv" Encoding:"rex2w 0x53"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1983 Instruction:"PUSHP Zv" Encoding:"rex2w 0x54"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1984 Instruction:"PUSHP Zv" Encoding:"rex2w 0x55"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1985 Instruction:"PUSHP Zv" Encoding:"rex2w 0x56"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1986 Instruction:"PUSHP Zv" Encoding:"rex2w 0x57"/"O"
+ {
+ .Instruction = ND_INS_PUSHP,
+ .Category = ND_CAT_PUSH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1987 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
+ {
+ .Instruction = ND_INS_PVALIDATE,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SNP,
+ .Mnemonic = 737,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SNP,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:1988 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
+ {
+ .Instruction = ND_INS_PXOR,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_MMX,
+ .Mnemonic = 738,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_MMX,
+ .Operands =
+ {
+ OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1989 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
+ {
+ .Instruction = ND_INS_PXOR,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 738,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:1990 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1991 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1992 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1993 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1994 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1995 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1996 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1997 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1998 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:1999 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2000 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2001 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2002 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2003 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2004 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2005 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2006 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2007 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2008 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2009 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2010 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2011 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2"/"VM1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2012 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2"/"VM1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2013 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2"/"VM1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2014 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2"/"VMC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2015 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2"/"VMC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2016 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2"/"VMC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2017 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2018 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2019 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2020 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2"/"VM1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2021 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2"/"VM1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2022 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2"/"VM1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2023 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2"/"VMC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2024 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2"/"VMC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2025 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2"/"VMC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2026 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2027 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2028 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2029 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2030 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2031 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
+ {
+ .Instruction = ND_INS_RCL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2032 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
+ {
+ .Instruction = ND_INS_RCPPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 740,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2033 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
+ {
+ .Instruction = ND_INS_RCPSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 741,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2034 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2035 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2036 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2037 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2038 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2039 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2040 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2041 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2042 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2043 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2044 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2045 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2046 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2047 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2048 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2049 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2050 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2051 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2052 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2053 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2054 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2055 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3"/"VM1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2056 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3"/"VM1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2057 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3"/"VM1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2058 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3"/"VMC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2059 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3"/"VMC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2060 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3"/"VMC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2061 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2062 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2063 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2064 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3"/"VM1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2065 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3"/"VM1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2066 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3"/"VM1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2067 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3"/"VMC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2068 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3"/"VMC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2069 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3"/"VMC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2070 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2071 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2072 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2073 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2074 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2075 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
+ {
+ .Instruction = ND_INS_RCR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2076 Instruction:"RDFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /0:reg"/"M"
+ {
+ .Instruction = ND_INS_RDFSBASE,
+ .Category = ND_CAT_RDWRFSGS,
+ .IsaSet = ND_SET_RDWRFSGS,
+ .Mnemonic = 743,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_RDWRFSGS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_FSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2077 Instruction:"RDGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /1:reg"/"M"
+ {
+ .Instruction = ND_INS_RDGSBASE,
+ .Category = ND_CAT_RDWRFSGS,
+ .IsaSet = ND_SET_RDWRFSGS,
+ .Mnemonic = 744,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_RDWRFSGS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2078 Instruction:"RDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF6 /0:reg id"/"MI"
+ {
+ .Instruction = ND_INS_RDMSR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MSR_IMM,
+ .Mnemonic = 745,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MSR_IMM,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2079 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
+ {
+ .Instruction = ND_INS_RDMSR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_PENTIUMREAL,
+ .Mnemonic = 745,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = ND_CFF_MSR,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2080 Instruction:"RDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF6 /0:reg id"/"MI"
+ {
+ .Instruction = ND_INS_RDMSR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MSR_IMM,
+ .Mnemonic = 745,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MSR_IMM,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2081 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/""
+ {
+ .Instruction = ND_INS_RDMSRLIST,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MSRLIST,
+ .Mnemonic = 746,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MSRLIST,
+ .Operands =
+ {
+ OP(ND_OPT_SMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_DMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2082 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
+ {
+ .Instruction = ND_INS_RDPID,
+ .Category = ND_CAT_RDPID,
+ .IsaSet = ND_SET_RDPID,
+ .Mnemonic = 747,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RDPID,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_yf, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_TSCAUX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2083 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
+ {
+ .Instruction = ND_INS_RDPKRU,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_PKU,
+ .Mnemonic = 748,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_PKU,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2084 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
+ {
+ .Instruction = ND_INS_RDPMC,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_RDPMC,
+ .Mnemonic = 749,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2085 Instruction:"RDPRU" Encoding:"NP 0x0F 0x01 /0xFD"/""
+ {
+ .Instruction = ND_INS_RDPRU,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_RDPRU,
+ .Mnemonic = 750,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RDPRU,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2086 Instruction:"RDRAND Rv" Encoding:"NP 0x0F 0xC7 /6:reg"/"M"
+ {
+ .Instruction = ND_INS_RDRAND,
+ .Category = ND_CAT_RDRAND,
+ .IsaSet = ND_SET_RDRAND,
+ .Mnemonic = 751,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RDRAND,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2087 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
+ {
+ .Instruction = ND_INS_RDRAND,
+ .Category = ND_CAT_RDRAND,
+ .IsaSet = ND_SET_RDRAND,
+ .Mnemonic = 751,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_S66|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RDRAND,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2088 Instruction:"RDSEED Rv" Encoding:"NP 0x0F 0xC7 /7:reg"/"M"
+ {
+ .Instruction = ND_INS_RDSEED,
+ .Category = ND_CAT_RDSEED,
+ .IsaSet = ND_SET_RDSEED,
+ .Mnemonic = 752,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RDSEED,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2089 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
+ {
+ .Instruction = ND_INS_RDSEED,
+ .Category = ND_CAT_RDSEED,
+ .IsaSet = ND_SET_RDSEED,
+ .Mnemonic = 752,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_S66|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RDSEED,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2090 Instruction:"RDSSPD Rd" Encoding:"cet repz 0x0F 0x1E /1:reg"/"M"
+ {
+ .Instruction = ND_INS_RSSSP,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 753,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2091 Instruction:"RDSSPQ Rq" Encoding:"cet repz rexw 0x0F 0x1E /1:reg"/"M"
+ {
+ .Instruction = ND_INS_RSSSP,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 754,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2092 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
+ {
+ .Instruction = ND_INS_RDTSC,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_PENTIUMREAL,
+ .Mnemonic = 755,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_TSC, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2093 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
+ {
+ .Instruction = ND_INS_RDTSCP,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_RDTSCP,
+ .Mnemonic = 756,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RDTSCP,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_TSC, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_TSCAUX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2094 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
+ {
+ .Instruction = ND_INS_RETF,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 757,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2095 Instruction:"RETF" Encoding:"0xCB"/""
+ {
+ .Instruction = ND_INS_RETF,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 757,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2096 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
+ {
+ .Instruction = ND_INS_RETN,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 758,
+ .ValidPrefixes = ND_PREF_BND,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2097 Instruction:"RETN" Encoding:"0xC3"/""
+ {
+ .Instruction = ND_INS_RETN,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 758,
+ .ValidPrefixes = ND_PREF_BND,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2098 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
+ {
+ .Instruction = ND_INS_RMPADJUST,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SNP,
+ .Mnemonic = 759,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_SNP,
+ .Operands =
+ {
+ OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2099 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/""
+ {
+ .Instruction = ND_INS_RMPQUERY,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SNP,
+ .Mnemonic = 760,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_RMPQUERY,
+ .Operands =
+ {
+ OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2100 Instruction:"RMPREAD" Encoding:"0xF2 0x0F 0x01 /0xFD"/""
+ {
+ .Instruction = ND_INS_RMPREAD,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SNP,
+ .Mnemonic = 761,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_RMPREAD,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_pCX, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2101 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
+ {
+ .Instruction = ND_INS_RMPUPDATE,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SNP,
+ .Mnemonic = 762,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_SNP,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_pCX, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2102 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2103 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2104 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2105 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2106 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2107 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2108 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2109 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2110 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2111 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2112 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2113 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2114 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2115 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2116 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2117 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2118 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2119 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2120 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2121 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2122 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2123 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0"/"VM1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2124 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0"/"VM1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2125 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0"/"VM1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2126 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0"/"VMC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2127 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0"/"VMC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2128 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0"/"VMC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2129 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2130 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2131 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2132 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0"/"VM1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2133 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0"/"VM1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2134 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0"/"VM1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2135 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0"/"VMC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2136 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0"/"VMC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2137 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0"/"VMC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2138 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2139 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2140 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2141 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2142 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2143 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
+ {
+ .Instruction = ND_INS_ROL,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2144 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2145 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2146 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2147 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2148 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2149 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2150 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2151 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2152 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2153 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2154 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2155 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2156 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2157 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2158 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2159 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2160 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2161 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2162 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2163 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2164 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2165 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1"/"VM1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2166 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1"/"VM1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2167 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1"/"VM1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2168 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1"/"VMC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2169 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1"/"VMC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2170 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1"/"VMC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2171 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2172 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2173 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib"/"VMI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2174 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1"/"VM1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2175 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1"/"VM1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2176 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1"/"VM1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2177 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1"/"VMC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2178 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1"/"VMC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2179 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1"/"VMC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2180 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2181 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2182 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2183 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2184 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2185 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
+ {
+ .Instruction = ND_INS_ROR,
+ .Category = ND_CAT_ROTATE,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2186 Instruction:"RORX Gy,Ey,Ib" Encoding:"evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_RORX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 765,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2187 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_RORX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 765,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2188 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_ROUNDPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 766,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2189 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_ROUNDPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 767,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2190 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_ROUNDSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 768,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2191 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_ROUNDSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE4,
+ .Mnemonic = 769,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2192 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
+ {
+ .Instruction = ND_INS_RSM,
+ .Category = ND_CAT_SYSRET,
+ .IsaSet = ND_SET_I486,
+ .Mnemonic = 770,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2193 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
+ {
+ .Instruction = ND_INS_RSQRTPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 771,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2194 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
+ {
+ .Instruction = ND_INS_RSQRTSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 772,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2195 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
+ {
+ .Instruction = ND_INS_RSTORSSP,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 773,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2196 Instruction:"SAHF" Encoding:"0x9E"/""
+ {
+ .Instruction = ND_INS_SAHF,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 774,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2197 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2198 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2199 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2200 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2201 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2202 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2203 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2204 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2205 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2206 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2207 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2208 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2209 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2210 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2211 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2212 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2213 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2214 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2215 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2216 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2217 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2218 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6"/"VM1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2219 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6"/"VM1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2220 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6"/"VM1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2221 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6"/"VMC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2222 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6"/"VMC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2223 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6"/"VMC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2224 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2225 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2226 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2227 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6"/"VM1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2228 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6"/"VM1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2229 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6"/"VM1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2230 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6"/"VMC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2231 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6"/"VMC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2232 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6"/"VMC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2233 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2234 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2235 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2236 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2237 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2238 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
+ {
+ .Instruction = ND_INS_SAL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2239 Instruction:"SALC" Encoding:"0xD6"/""
+ {
+ .Instruction = ND_INS_SALC,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 776,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2240 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2241 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2242 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2243 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2244 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2245 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2246 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2247 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2248 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2249 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2250 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2251 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2252 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2253 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2254 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2255 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2256 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2257 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2258 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2259 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2260 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2261 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7"/"VM1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2262 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7"/"VM1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2263 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7"/"VM1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2264 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7"/"VMC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2265 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7"/"VMC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2266 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7"/"VMC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2267 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2268 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2269 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2270 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7"/"VM1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2271 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7"/"VM1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2272 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7"/"VM1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2273 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7"/"VMC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2274 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7"/"VMC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2275 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7"/"VMC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2276 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2277 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2278 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2279 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2280 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2281 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
+ {
+ .Instruction = ND_INS_SAR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2282 Instruction:"SARX Gy,Ey,By" Encoding:"evex m:2 p:2 l:0 nf:0 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_SARX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 778,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2283 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_SARX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 778,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2284 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
+ {
+ .Instruction = ND_INS_SAVEPREVSSP,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 779,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_SHS, ND_OPS_12, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2285 Instruction:"SBB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r"/"MR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2286 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r"/"MR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2287 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r"/"MR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2288 Instruction:"SBB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r"/"RM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2289 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r"/"RM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2290 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r"/"RM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2291 Instruction:"SBB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2292 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2293 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2294 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2295 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2296 Instruction:"SBB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2297 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2298 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2299 Instruction:"SBB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r"/"VRM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2300 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r"/"VRM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2301 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r"/"VRM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2302 Instruction:"SBB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2303 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz"/"VMI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2304 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz"/"VMI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2305 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2306 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2307 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2308 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2309 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2310 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2311 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2312 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2313 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2314 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2315 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2316 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
+ {
+ .Instruction = ND_INS_SBB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 780,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2317 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 781,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2318 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 781,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2319 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 782,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2320 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 782,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2321 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 783,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2322 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 783,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2323 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 784,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2324 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
+ {
+ .Instruction = ND_INS_SCAS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 784,
+ .ValidPrefixes = ND_PREF_REPC,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2325 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
+ {
+ .Instruction = ND_INS_SEAMCALL,
+ .Category = ND_CAT_TDX,
+ .IsaSet = ND_SET_TDX,
+ .Mnemonic = 785,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2326 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
+ {
+ .Instruction = ND_INS_SEAMOPS,
+ .Category = ND_CAT_TDX,
+ .IsaSet = ND_SET_TDX,
+ .Mnemonic = 786,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 5),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rR8, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rR9, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2327 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
+ {
+ .Instruction = ND_INS_SEAMRET,
+ .Category = ND_CAT_TDX,
+ .IsaSet = ND_SET_TDX,
+ .Mnemonic = 787,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2328 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M"
+ {
+ .Instruction = ND_INS_SENDUIPI,
+ .Category = ND_CAT_UINTR,
+ .IsaSet = ND_SET_UINTR,
+ .Mnemonic = 788,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_UINTR,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2329 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
+ {
+ .Instruction = ND_INS_SERIALIZE,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_SERIALIZE,
+ .Mnemonic = 789,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SERIALIZE,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2330 Instruction:"SETBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x46 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 790,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2331 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 790,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2332 Instruction:"SETC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x42 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 791,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2333 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 791,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2334 Instruction:"SETL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4C /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 792,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2335 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 792,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2336 Instruction:"SETLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4E /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 793,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2337 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 793,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2338 Instruction:"SETNBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x47 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 794,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2339 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 794,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2340 Instruction:"SETNC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x43 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 795,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2341 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 795,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_CF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2342 Instruction:"SETNL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4D /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 796,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2343 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 796,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2344 Instruction:"SETNLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4F /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 797,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2345 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 797,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2346 Instruction:"SETNO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x41 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 798,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2347 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 798,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2348 Instruction:"SETNP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4B /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 799,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2349 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 799,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2350 Instruction:"SETNS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x49 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 800,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2351 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 800,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2352 Instruction:"SETNZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x45 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 801,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2353 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 801,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2354 Instruction:"SETO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x40 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 802,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2355 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 802,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_OF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2356 Instruction:"SETP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4A /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 803,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2357 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 803,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_PF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2358 Instruction:"SETS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x48 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 804,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2359 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 804,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_SF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2360 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
+ {
+ .Instruction = ND_INS_SETSSBSY,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 805,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_SHS0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2361 Instruction:"SETZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x44 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 806,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ZU,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2362 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
+ {
+ .Instruction = ND_INS_SETcc,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 806,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_ZF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_COND|ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2363 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
+ {
+ .Instruction = ND_INS_SFENCE,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 807,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2364 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_SGDT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 808,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_GDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2365 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
+ {
+ .Instruction = ND_INS_SHA1MSG1,
+ .Category = ND_CAT_SHA,
+ .IsaSet = ND_SET_SHA,
+ .Mnemonic = 809,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2366 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
+ {
+ .Instruction = ND_INS_SHA1MSG2,
+ .Category = ND_CAT_SHA,
+ .IsaSet = ND_SET_SHA,
+ .Mnemonic = 810,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2367 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
+ {
+ .Instruction = ND_INS_SHA1NEXTE,
+ .Category = ND_CAT_SHA,
+ .IsaSet = ND_SET_SHA,
+ .Mnemonic = 811,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2368 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_SHA1RNDS4,
+ .Category = ND_CAT_SHA,
+ .IsaSet = ND_SET_SHA,
+ .Mnemonic = 812,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2369 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
+ {
+ .Instruction = ND_INS_SHA256MSG1,
+ .Category = ND_CAT_SHA,
+ .IsaSet = ND_SET_SHA,
+ .Mnemonic = 813,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2370 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
+ {
+ .Instruction = ND_INS_SHA256MSG2,
+ .Category = ND_CAT_SHA,
+ .IsaSet = ND_SET_SHA,
+ .Mnemonic = 814,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2371 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
+ {
+ .Instruction = ND_INS_SHA256RNDS2,
+ .Category = ND_CAT_SHA,
+ .IsaSet = ND_SET_SHA,
+ .Mnemonic = 815,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2372 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2373 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2374 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2375 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2376 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2377 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2378 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2379 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2380 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2381 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2382 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2383 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2384 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2385 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2386 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2387 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2388 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2389 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2390 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2391 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2392 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2393 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4"/"VM1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2394 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4"/"VM1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2395 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4"/"VM1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2396 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4"/"VMC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2397 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4"/"VMC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2398 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4"/"VMC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2399 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2400 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2401 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2402 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4"/"VM1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2403 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4"/"VM1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2404 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4"/"VM1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2405 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4"/"VMC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2406 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4"/"VMC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2407 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4"/"VMC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2408 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2409 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2410 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2411 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2412 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2413 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
+ {
+ .Instruction = ND_INS_SHL,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2414 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2415 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2416 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2417 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2418 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2419 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2420 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2421 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2422 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2423 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2424 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2425 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2426 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2427 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2428 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2429 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2430 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2431 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHLD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2432 Instruction:"SHLX Gy,Ey,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_SHLX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 818,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2433 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_SHLX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 818,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2434 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2435 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2436 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2437 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2438 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2439 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2440 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2441 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2442 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2443 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2444 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2445 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2446 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2447 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2448 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2449 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2450 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2451 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2452 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2453 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2454 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2455 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5"/"VM1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2456 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5"/"VM1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2457 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5"/"VM1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2458 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5"/"VMC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2459 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5"/"VMC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2460 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5"/"VMC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2461 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2462 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2463 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2464 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5"/"VM1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2465 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5"/"VM1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2466 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5"/"VM1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2467 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5"/"VMC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2468 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5"/"VMC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2469 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5"/"VMC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2470 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2471 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2472 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2473 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2474 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2475 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
+ {
+ .Instruction = ND_INS_SHR,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2476 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2477 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2478 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2479 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2480 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2481 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2482 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2483 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2484 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2485 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2486 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2487 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(4, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2488 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2489 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2490 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib"/"VMRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2491 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r"/"VMRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2492 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2493 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
+ {
+ .Instruction = ND_INS_SHRD,
+ .Category = ND_CAT_SHIFT,
+ .IsaSet = ND_SET_I386,
+ .Mnemonic = 820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2494 Instruction:"SHRX Gy,Ey,By" Encoding:"evex m:2 p:3 l:0 nf:0 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_SHRX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 821,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_BMI,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2495 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
+ {
+ .Instruction = ND_INS_SHRX,
+ .Category = ND_CAT_BMI2,
+ .IsaSet = ND_SET_BMI2,
+ .Mnemonic = 821,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_13,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI2,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2496 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_SHUFPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 822,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2497 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_SHUFPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 823,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2498 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_SIDT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 824,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_IDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2499 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
+ {
+ .Instruction = ND_INS_SKINIT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 825,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2500 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_SLDT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 826,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2501 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
+ {
+ .Instruction = ND_INS_SLDT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 826,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2502 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
+ {
+ .Instruction = ND_INS_SLWPCB,
+ .Category = ND_CAT_LWP,
+ .IsaSet = ND_SET_LWP,
+ .Mnemonic = 827,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_LWP,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2503 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
+ {
+ .Instruction = ND_INS_SMSW,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 828,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2504 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
+ {
+ .Instruction = ND_INS_SMSW,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286REAL,
+ .Mnemonic = 828,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2505 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
+ {
+ .Instruction = ND_INS_SPFLT,
+ .Category = ND_CAT_UNKNOWN,
+ .IsaSet = ND_SET_UNKNOWN,
+ .Mnemonic = 829,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2506 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
+ {
+ .Instruction = ND_INS_SQRTPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 830,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2507 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
+ {
+ .Instruction = ND_INS_SQRTPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 831,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2508 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
+ {
+ .Instruction = ND_INS_SQRTSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 832,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2509 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
+ {
+ .Instruction = ND_INS_SQRTSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 833,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2510 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
+ {
+ .Instruction = ND_INS_STAC,
+ .Category = ND_CAT_SMAP,
+ .IsaSet = ND_SET_SMAP,
+ .Mnemonic = 834,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_AC,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SMAP,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2511 Instruction:"STC" Encoding:"0xF9"/""
+ {
+ .Instruction = ND_INS_STC,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 835,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_CF,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2512 Instruction:"STD" Encoding:"0xFD"/""
+ {
+ .Instruction = ND_INS_STD,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 836,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_DF,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2513 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
+ {
+ .Instruction = ND_INS_STGI,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 837,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2514 Instruction:"STI" Encoding:"0xFB"/""
+ {
+ .Instruction = ND_INS_STI,
+ .Category = ND_CAT_FLAGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 838,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0|NDR_RFLAG_IF,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2515 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
+ {
+ .Instruction = ND_INS_STMXCSR,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 839,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2516 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 840,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2517 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 840,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2518 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 841,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2519 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 841,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2520 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 842,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2521 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 842,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2522 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 843,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2523 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
+ {
+ .Instruction = ND_INS_STOS,
+ .Category = ND_CAT_STRINGOP,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 843,
+ .ValidPrefixes = ND_PREF_REP,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0|NDR_RFLAG_DF,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2524 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
+ {
+ .Instruction = ND_INS_STR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 844,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2525 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
+ {
+ .Instruction = ND_INS_STR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 844,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2526 Instruction:"STTILECFG Moq" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_STTILECFG,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 845,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E2,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2527 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
+ {
+ .Instruction = ND_INS_STTILECFG,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTILE,
+ .Mnemonic = 845,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTILE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2528 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/""
+ {
+ .Instruction = ND_INS_STUI,
+ .Category = ND_CAT_UINTR,
+ .IsaSet = ND_SET_UINTR,
+ .Mnemonic = 846,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_UINTR,
+ .Operands =
+ {
+ OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2529 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2530 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2531 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2532 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2533 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2534 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2535 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2536 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2537 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2538 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2539 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2540 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2541 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2542 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2543 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2544 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2545 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2546 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2547 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2548 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2549 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2550 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2551 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2552 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2553 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2554 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r"/"VRM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2555 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r"/"VRM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2556 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r"/"VRM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2557 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2558 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2559 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2560 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2561 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2562 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2563 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2564 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r"/"VMR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2565 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r"/"VRM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2566 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r"/"VRM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2567 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r"/"VRM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2568 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2569 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2570 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2571 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2572 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib"/"VMI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2573 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2574 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2575 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2576 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2577 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2578 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2579 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2580 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2581 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2582 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
+ {
+ .Instruction = ND_INS_SUB,
+ .Category = ND_CAT_ARITH,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 847,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2583 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
+ {
+ .Instruction = ND_INS_SUBPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 848,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2584 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
+ {
+ .Instruction = ND_INS_SUBPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 849,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2585 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
+ {
+ .Instruction = ND_INS_SUBSD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 850,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2586 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
+ {
+ .Instruction = ND_INS_SUBSS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 851,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2587 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
+ {
+ .Instruction = ND_INS_SWAPGS,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_LONGMODE,
+ .Mnemonic = 852,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2588 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
+ {
+ .Instruction = ND_INS_SYSCALL,
+ .Category = ND_CAT_SYSCALL,
+ .IsaSet = ND_SET_AMD,
+ .Mnemonic = 853,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 10),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_CETT,
+ .CpuidFlag = ND_CFF_FSC,
+ .Operands =
+ {
+ OP(ND_OPT_STAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_LSTAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_FMASK, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rR11, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2589 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
+ {
+ .Instruction = ND_INS_SYSENTER,
+ .Category = ND_CAT_SYSCALL,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 854,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 9),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_IF,
+ .Attributes = ND_FLAG_CETT|ND_FLAG_NOREX2,
+ .CpuidFlag = ND_CFF_SEP,
+ .Operands =
+ {
+ OP(ND_OPT_SCS, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SESP, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SEIP, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:2590 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
+ {
+ .Instruction = ND_INS_SYSEXIT,
+ .Category = ND_CAT_SYSRET,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 855,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 8),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2,
+ .CpuidFlag = ND_CFF_SEP,
+ .Operands =
+ {
+ OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SCS, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2591 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
+ {
+ .Instruction = ND_INS_SYSRET,
+ .Category = ND_CAT_SYSRET,
+ .IsaSet = ND_SET_AMD,
+ .Mnemonic = 856,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 8),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = ND_CFF_FSC,
+ .Operands =
+ {
+ OP(ND_OPT_STAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rR11, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2592 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
+ {
+ .Instruction = ND_INS_T1MSKC,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 857,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2593 Instruction:"T2RPNTLVWZ0 rTt+1,Mt" Encoding:"vex m:2 p:0 l:0 w:0 0x6E /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ0,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 858,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2594 Instruction:"T2RPNTLVWZ0RS rTt+1,Mt" Encoding:"vex m:5 p:0 l:0 w:0 0xF8 /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ0RS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 859,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2595 Instruction:"T2RPNTLVWZ0RST1 rTt+1,Mt" Encoding:"vex m:5 p:0 l:0 w:0 0xF9 /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ0RST1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 860,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2596 Instruction:"T2RPNTLVWZ0T1 rTt+1,Mt" Encoding:"vex m:2 p:0 l:0 w:0 0x6F /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ0T1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 861,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2597 Instruction:"T2RPNTLVWZ1 rTt+1,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x6E /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 862,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2598 Instruction:"T2RPNTLVWZ1RS rTt+1,Mt" Encoding:"vex m:5 p:1 l:0 w:0 0xF8 /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ1RS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 863,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2599 Instruction:"T2RPNTLVWZ1RST1 rTt+1,Mt" Encoding:"vex m:5 p:1 l:0 w:0 0xF9 /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ1RST1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 864,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2600 Instruction:"T2RPNTLVWZ1T1 rTt+1,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x6F /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_T2RPNTLVWZ1T1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 865,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2601 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/""
+ {
+ .Instruction = ND_INS_TCMMIMFP16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXCOMPLEX,
+ .Mnemonic = 866,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXCOMPLEX,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2602 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/""
+ {
+ .Instruction = ND_INS_TCMMRLFP16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXCOMPLEX,
+ .Mnemonic = 867,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXCOMPLEX,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2603 Instruction:"TCONJTCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6B /r:reg"/""
+ {
+ .Instruction = ND_INS_TCONJTCMMIMFP16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 868,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2604 Instruction:"TCONJTFP16 rTt,mTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6B /r:reg"/""
+ {
+ .Instruction = ND_INS_TCONJTFP16,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 869,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E9,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2605 Instruction:"TCVTROWD2PS Voq,mTt,Bd" Encoding:"evex m:2 p:2 l:2 w:0 0x4A /r:reg"/"RV"
+ {
+ .Instruction = ND_INS_TCVTROWD2PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 870,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2606 Instruction:"TCVTROWD2PS Voq,mTt,Ib" Encoding:"evex m:3 p:2 l:2 w:0 0x07 /r:reg ib"/"RI"
+ {
+ .Instruction = ND_INS_TCVTROWD2PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 870,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2607 Instruction:"TCVTROWPS2PBF16H Voq,mTt,Bd" Encoding:"evex m:2 p:3 l:2 w:0 0x6D /r:reg"/"RV"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PBF16H,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 871,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2608 Instruction:"TCVTROWPS2PBF16H Voq,mTt,Ib" Encoding:"evex m:3 p:3 l:2 w:0 0x07 /r:reg ib"/"RI"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PBF16H,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 871,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2609 Instruction:"TCVTROWPS2PBF16L Voq,mTt,Bd" Encoding:"evex m:2 p:2 l:2 w:0 0x6D /r:reg"/"RV"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PBF16L,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 872,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2610 Instruction:"TCVTROWPS2PBF16L Voq,mTt,Ib" Encoding:"evex m:3 p:2 l:2 w:0 0x77 /r:reg ib"/"RI"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PBF16L,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 872,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2611 Instruction:"TCVTROWPS2PHH Voq,mTt,Bd" Encoding:"evex m:2 p:0 l:2 w:0 0x6D /r:reg"/"RV"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PHH,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 873,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2612 Instruction:"TCVTROWPS2PHH Voq,mTt,Ib" Encoding:"evex m:3 p:0 l:2 w:0 0x07 /r:reg ib"/"RI"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PHH,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 873,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2613 Instruction:"TCVTROWPS2PHL Voq,mTt,Bd" Encoding:"evex m:2 p:1 l:2 w:0 0x6D /r:reg"/"RV"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PHL,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 874,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2614 Instruction:"TCVTROWPS2PHL Voq,mTt,Ib" Encoding:"evex m:3 p:3 l:2 w:0 0x77 /r:reg ib"/"RI"
+ {
+ .Instruction = ND_INS_TCVTROWPS2PHL,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 874,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2615 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
+ {
+ .Instruction = ND_INS_TDCALL,
+ .Category = ND_CAT_TDX,
+ .IsaSet = ND_SET_TDX,
+ .Mnemonic = 875,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2616 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPBF16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXBF16,
+ .Mnemonic = 876,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXBF16,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2617 Instruction:"TDPBF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:0 l:0 w:0 0xFD /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPBF8PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXFP8,
+ .Mnemonic = 877,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXFP8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2618 Instruction:"TDPBHF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:3 l:0 w:0 0xFD /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPBHF8PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXFP8,
+ .Mnemonic = 878,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXFP8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2619 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPBSSD,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXINT8,
+ .Mnemonic = 879,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXINT8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2620 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPBSUD,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXINT8,
+ .Mnemonic = 880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXINT8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2621 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPBUSD,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXINT8,
+ .Mnemonic = 881,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXINT8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2622 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPBUUD,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXINT8,
+ .Mnemonic = 882,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXINT8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2623 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPFP16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXFP16,
+ .Mnemonic = 883,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXFP16,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2624 Instruction:"TDPHBF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:2 l:0 w:0 0xFD /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPHBF8PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXFP8,
+ .Mnemonic = 884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXFP8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2625 Instruction:"TDPHF8PS rTt,mTt,vTt" Encoding:"vex m:5 p:1 l:0 w:0 0xFD /r:reg"/""
+ {
+ .Instruction = ND_INS_TDPHF8PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXFP8,
+ .Mnemonic = 885,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXFP8,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2626 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2627 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2628 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2629 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_NOREX2,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2630 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2631 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2632 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2633 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
+ {
+ .Instruction = ND_INS_TEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2634 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/""
+ {
+ .Instruction = ND_INS_TESTUI,
+ .Category = ND_CAT_UINTR,
+ .IsaSet = ND_SET_UINTR,
+ .Mnemonic = 887,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_UINTR,
+ .Operands =
+ {
+ OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2635 Instruction:"TILELOADD rTt,Mt" Encoding:"evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILELOADD,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 888,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E3,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2636 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILELOADD,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTILE,
+ .Mnemonic = 888,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTILE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2637 Instruction:"TILELOADDRS rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4A /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILELOADDRS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXMOVRS,
+ .Mnemonic = 889,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXMOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2638 Instruction:"TILELOADDRST1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4A /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILELOADDRST1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXMOVRS,
+ .Mnemonic = 890,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXMOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2639 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILELOADDT1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 891,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E3,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2640 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILELOADDT1,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTILE,
+ .Mnemonic = 891,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTILE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2641 Instruction:"TILEMOVROW Voq,mTt,Bd" Encoding:"evex m:2 p:1 l:2 w:0 0x4A /r:reg"/"RV"
+ {
+ .Instruction = ND_INS_TILEMOVROW,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 892,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_B, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2642 Instruction:"TILEMOVROW Voq,mTt,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x07 /r:reg ib"/"RI"
+ {
+ .Instruction = ND_INS_TILEMOVROW,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXAVX512,
+ .Mnemonic = 892,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AMXAVX512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2643 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
+ {
+ .Instruction = ND_INS_TILERELEASE,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTILE,
+ .Mnemonic = 893,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTILE,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2644 Instruction:"TILESTORED Mt,rTt" Encoding:"evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILESTORED,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 894,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_EVEX_E3,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2645 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
+ {
+ .Instruction = ND_INS_TILESTORED,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTILE,
+ .Mnemonic = 894,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTILE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2646 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
+ {
+ .Instruction = ND_INS_TILEZERO,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTILE,
+ .Mnemonic = 895,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTILE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2647 Instruction:"TLBSYNC" Encoding:"NP 0x0F 0x01 /0xFF"/""
+ {
+ .Instruction = ND_INS_TLBSYNC,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_INVLPGB,
+ .Mnemonic = 896,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_INVLPGB,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2648 Instruction:"TMMULTF32PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x48 /r:reg"/""
+ {
+ .Instruction = ND_INS_TMMULTF32PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTF32,
+ .Mnemonic = 897,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTF32,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2649 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
+ {
+ .Instruction = ND_INS_TPAUSE,
+ .Category = ND_CAT_WAITPKG,
+ .IsaSet = ND_SET_WAITPKG,
+ .Mnemonic = 898,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_WAITPKG,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2650 Instruction:"TTCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x6B /r:reg"/""
+ {
+ .Instruction = ND_INS_TTCMMIMFP16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 899,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2651 Instruction:"TTCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x6B /r:reg"/""
+ {
+ .Instruction = ND_INS_TTCMMRLFP16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 900,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2652 Instruction:"TTDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x6C /r:reg"/""
+ {
+ .Instruction = ND_INS_TTDPBF16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 901,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2653 Instruction:"TTDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x6C /r:reg"/""
+ {
+ .Instruction = ND_INS_TTDPFP16PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 902,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2654 Instruction:"TTMMULTF32PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x48 /r:reg"/""
+ {
+ .Instruction = ND_INS_TTMMULTF32PS,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 903,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2655 Instruction:"TTRANSPOSED rTt,mTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5F /r:reg"/""
+ {
+ .Instruction = ND_INS_TTRANSPOSED,
+ .Category = ND_CAT_AMX,
+ .IsaSet = ND_SET_AMXTRANSPOSE,
+ .Mnemonic = 904,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_AMX_E9,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_AMXTRANSPOSE,
+ .Operands =
+ {
+ OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2656 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r"/"RM"
+ {
+ .Instruction = ND_INS_TZCNT,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 905,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2657 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r"/"RM"
+ {
+ .Instruction = ND_INS_TZCNT,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 905,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2658 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r"/"RM"
+ {
+ .Instruction = ND_INS_TZCNT,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 905,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2659 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r"/"RM"
+ {
+ .Instruction = ND_INS_TZCNT,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 905,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2660 Instruction:"TZCNT Gv,Ev" Encoding:"repz 0x0F 0xBC /r"/"RM"
+ {
+ .Instruction = ND_INS_TZCNT,
+ .Category = ND_CAT_BMI1,
+ .IsaSet = ND_SET_BMI1,
+ .Mnemonic = 905,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_BMI1,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2661 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
+ {
+ .Instruction = ND_INS_TZMSK,
+ .Category = ND_CAT_BITBYTE,
+ .IsaSet = ND_SET_TBM,
+ .Mnemonic = 906,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TBM,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2662 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_UCOMISD,
+ .Category = ND_CAT_SSE2,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 907,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2663 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_UCOMISS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 908,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2664 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
+ {
+ .Instruction = ND_INS_UD0,
+ .Category = ND_CAT_UD,
+ .IsaSet = ND_SET_UD,
+ .Mnemonic = 909,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2665 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
+ {
+ .Instruction = ND_INS_UD1,
+ .Category = ND_CAT_UD,
+ .IsaSet = ND_SET_UD,
+ .Mnemonic = 910,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2666 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
+ {
+ .Instruction = ND_INS_UD2,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_PPRO,
+ .Mnemonic = 911,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:2667 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/""
+ {
+ .Instruction = ND_INS_UIRET,
+ .Category = ND_CAT_RET,
+ .IsaSet = ND_SET_UINTR,
+ .Mnemonic = 912,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 6),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_UINTR,
+ .Operands =
+ {
+ OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2668 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
+ {
+ .Instruction = ND_INS_UMONITOR,
+ .Category = ND_CAT_WAITPKG,
+ .IsaSet = ND_SET_WAITPKG,
+ .Mnemonic = 913,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_WAITPKG,
+ .Operands =
+ {
+ OP(ND_OPT_mM, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2669 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
+ {
+ .Instruction = ND_INS_UMWAIT,
+ .Category = ND_CAT_WAITPKG,
+ .IsaSet = ND_SET_WAITPKG,
+ .Mnemonic = 914,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_WAITPKG,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2670 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
+ {
+ .Instruction = ND_INS_UNPCKHPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 915,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2671 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
+ {
+ .Instruction = ND_INS_UNPCKHPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 916,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2672 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
+ {
+ .Instruction = ND_INS_UNPCKLPD,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 917,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2673 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
+ {
+ .Instruction = ND_INS_UNPCKLPS,
+ .Category = ND_CAT_SSE,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 918,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2674 Instruction:"URDMSR Eq,Gq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_URDMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 919,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_USER_MSR,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2675 Instruction:"URDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id"/"MI"
+ {
+ .Instruction = ND_INS_URDMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 919,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2676 Instruction:"URDMSR Rq,Gq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_URDMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_USER_MSR,
+ .Mnemonic = 919,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_USER_MSR,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2677 Instruction:"URDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF8 /0:reg id"/"MI"
+ {
+ .Instruction = ND_INS_URDMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_USER_MSR,
+ .Mnemonic = 919,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_USER_MSR,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2678 Instruction:"UWRMSR Gq,Eq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_UWRMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 920,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_USER_MSR,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2679 Instruction:"UWRMSR Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id"/"IM"
+ {
+ .Instruction = ND_INS_UWRMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 920,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2680 Instruction:"UWRMSR Gq,Rq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_UWRMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_USER_MSR,
+ .Mnemonic = 920,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_USER_MSR,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2681 Instruction:"UWRMSR Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF8 /0:reg id"/"IM"
+ {
+ .Instruction = ND_INS_UWRMSR,
+ .Category = ND_CAT_USER_MSR,
+ .IsaSet = ND_SET_USER_MSR,
+ .Mnemonic = 920,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_USER_MSR,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2682 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
+ {
+ .Instruction = ND_INS_V4FMADDPS,
+ .Category = ND_CAT_VFMAPS,
+ .IsaSet = ND_SET_AVX5124FMAPS,
+ .Mnemonic = 921,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1_4X,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX5124FMAPS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2683 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
+ {
+ .Instruction = ND_INS_V4FMADDSS,
+ .Category = ND_CAT_VFMAPS,
+ .IsaSet = ND_SET_AVX5124FMAPS,
+ .Mnemonic = 922,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1_4X,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX5124FMAPS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2684 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
+ {
+ .Instruction = ND_INS_V4FNMADDPS,
+ .Category = ND_CAT_VFMAPS,
+ .IsaSet = ND_SET_AVX5124FMAPS,
+ .Mnemonic = 923,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1_4X,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX5124FMAPS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2685 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
+ {
+ .Instruction = ND_INS_V4FNMADDSS,
+ .Category = ND_CAT_VFMAPS,
+ .IsaSet = ND_SET_AVX5124FMAPS,
+ .Mnemonic = 924,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1_4X,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX5124FMAPS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2686 Instruction:"VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x58 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VADDNEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 925,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2687 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VADDPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 926,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2688 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VADDPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 926,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2689 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VADDPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 927,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2690 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VADDPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 928,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2691 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VADDPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 928,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2692 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VADDSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 929,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2693 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VADDSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 929,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2694 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VADDSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 930,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2695 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VADDSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 931,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2696 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VADDSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 931,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2697 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VADDSUBPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 932,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2698 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VADDSUBPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 933,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2699 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESDEC,
+ .Category = ND_CAT_VAES,
+ .IsaSet = ND_SET_VAES,
+ .Mnemonic = 934,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_VAES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2700 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESDEC,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 934,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2701 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESDECLAST,
+ .Category = ND_CAT_VAES,
+ .IsaSet = ND_SET_VAES,
+ .Mnemonic = 935,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_VAES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2702 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESDECLAST,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 935,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2703 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESENC,
+ .Category = ND_CAT_VAES,
+ .IsaSet = ND_SET_VAES,
+ .Mnemonic = 936,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_VAES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2704 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESENC,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 936,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2705 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESENCLAST,
+ .Category = ND_CAT_VAES,
+ .IsaSet = ND_SET_VAES,
+ .Mnemonic = 937,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_VAES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2706 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VAESENCLAST,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 937,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2707 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
+ {
+ .Instruction = ND_INS_VAESIMC,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 938,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2708 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VAESKEYGENASSIST,
+ .Category = ND_CAT_AES,
+ .IsaSet = ND_SET_AES,
+ .Mnemonic = 939,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AES,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2709 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VALIGND,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 940,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2710 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VALIGNQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 941,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2711 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VANDNPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 942,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2712 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VANDNPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 942,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2713 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VANDNPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 943,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2714 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VANDNPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 943,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2715 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VANDPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 944,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2716 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VANDPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 944,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2717 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VANDPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 945,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2718 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VANDPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 945,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2719 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VBCSTNEBF162PS,
+ .Category = ND_CAT_AVXNECONVERT,
+ .IsaSet = ND_SET_AVXNECONVERT,
+ .Mnemonic = 946,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVXNECONVERT,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2720 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VBCSTNESH2PS,
+ .Category = ND_CAT_AVXNECONVERT,
+ .IsaSet = ND_SET_AVXNECONVERT,
+ .Mnemonic = 947,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVXNECONVERT,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2721 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VBLENDMPD,
+ .Category = ND_CAT_BLEND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 948,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2722 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VBLENDMPS,
+ .Category = ND_CAT_BLEND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 949,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2723 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VBLENDPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 950,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2724 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VBLENDPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 951,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2725 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VBLENDVPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 952,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2726 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VBLENDVPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 953,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2727 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VBROADCASTF128,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 954,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2728 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTF32X2,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 955,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2729 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTF32X4,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 956,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2730 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTF32X8,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 957,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T8,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2731 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTF64X2,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 958,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2732 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTF64X4,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 959,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2733 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VBROADCASTI128,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 960,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2734 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTI32X2,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 961,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2735 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTI32X4,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 962,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2736 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTI32X8,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 963,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T8,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2737 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTI64X2,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 964,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2738 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTI64X4,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 965,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2739 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTSD,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 966,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2740 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
+ {
+ .Instruction = ND_INS_VBROADCASTSD,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 966,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2741 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VBROADCASTSS,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 967,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2742 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
+ {
+ .Instruction = ND_INS_VBROADCASTSS,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 967,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2743 Instruction:"VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0xC2 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VCMPPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 968,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2744 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VCMPPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 969,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2745 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VCMPPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 969,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2746 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VCMPPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 970,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2747 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VCMPPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 971,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2748 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VCMPPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 971,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2749 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VCMPSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 972,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2750 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VCMPSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 972,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2751 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VCMPSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 973,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2752 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VCMPSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 974,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2753 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VCMPSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 974,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2754 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMISD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 975,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2755 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMISD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 975,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2756 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMISH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 976,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2757 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMISS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 977,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2758 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMISS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 977,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2759 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
+ {
+ .Instruction = ND_INS_VCOMPRESSPD,
+ .Category = ND_CAT_COMPRESS,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 978,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2760 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
+ {
+ .Instruction = ND_INS_VCOMPRESSPS,
+ .Category = ND_CAT_COMPRESS,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 979,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2761 Instruction:"VCOMSBF16 Vdq,Wsh" Encoding:"evex m:5 p:1 l:i w:0 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMSBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 980,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E10NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2762 Instruction:"VCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMXSD,
+ .Category = ND_CAT_AVX10CMPSFP,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 981,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2763 Instruction:"VCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMXSH,
+ .Category = ND_CAT_AVX10CMPSFP,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 982,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2764 Instruction:"VCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x2F /r"/"RM"
+ {
+ .Instruction = ND_INS_VCOMXSS,
+ .Category = ND_CAT_AVX10CMPSFP,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 983,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2765 Instruction:"VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x67 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVT2PS2PHX,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 984,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2766 Instruction:"VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:2 p:0 l:x w:0 0x74 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTBIASPH2BF8,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 985,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2767 Instruction:"VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x74 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTBIASPH2BF8S,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 986,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2768 Instruction:"VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x18 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTBIASPH2HF8,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 987,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2769 Instruction:"VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x1B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTBIASPH2HF8S,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 988,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2770 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTDQ2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 989,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2771 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTDQ2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 989,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2772 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTDQ2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 989,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2773 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTDQ2PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 990,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2774 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTDQ2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 991,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2775 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTDQ2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 991,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2776 Instruction:"VCVTHF82PH Vfv{K}{z},aKq,Whv" Encoding:"evex m:5 p:3 l:x w:0 0x1E /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTHF82PH,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 992,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2777 Instruction:"VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:2 p:3 l:x w:0 0x74 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTNE2PH2BF8,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 993,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2778 Instruction:"VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x74 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTNE2PH2BF8S,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 994,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2779 Instruction:"VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x18 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTNE2PH2HF8,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 995,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2780 Instruction:"VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x1B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTNE2PH2HF8S,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 996,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2781 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTNE2PS2BF16,
+ .Category = ND_CAT_AVX512BF16,
+ .IsaSet = ND_SET_AVX512BF16,
+ .Mnemonic = 997,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BF16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2782 Instruction:"VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x69 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTNEBF162IBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 998,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2783 Instruction:"VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTNEBF162IUBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 999,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2784 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VCVTNEEBF162PS,
+ .Category = ND_CAT_AVXNECONVERT,
+ .IsaSet = ND_SET_AVXNECONVERT,
+ .Mnemonic = 1000,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVXNECONVERT,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2785 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VCVTNEEPH2PS,
+ .Category = ND_CAT_AVXNECONVERT,
+ .IsaSet = ND_SET_AVXNECONVERT,
+ .Mnemonic = 1001,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVXNECONVERT,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2786 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VCVTNEOBF162PS,
+ .Category = ND_CAT_AVXNECONVERT,
+ .IsaSet = ND_SET_AVXNECONVERT,
+ .Mnemonic = 1002,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVXNECONVERT,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2787 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VCVTNEOPH2PS,
+ .Category = ND_CAT_AVXNECONVERT,
+ .IsaSet = ND_SET_AVXNECONVERT,
+ .Mnemonic = 1003,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVXNECONVERT,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2788 Instruction:"VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:2 p:2 l:x w:0 0x74 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTNEPH2BF8,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1004,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2789 Instruction:"VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x74 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTNEPH2BF8S,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1005,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2790 Instruction:"VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x18 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTNEPH2HF8,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1006,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2791 Instruction:"VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x1B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTNEPH2HF8S,
+ .Category = ND_CAT_AVX10CONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1007,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2792 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTNEPS2BF16,
+ .Category = ND_CAT_AVX512BF16,
+ .IsaSet = ND_SET_AVX512BF16,
+ .Mnemonic = 1008,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BF16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2793 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTNEPS2BF16,
+ .Category = ND_CAT_AVXNECONVERT,
+ .IsaSet = ND_SET_AVXNECONVERT,
+ .Mnemonic = 1008,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVXNECONVERT,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2794 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPD2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1009,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2795 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPD2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1009,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2796 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPD2PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1010,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2797 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPD2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1011,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2798 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPD2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1011,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2799 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPD2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1011,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2800 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPD2QQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1012,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2801 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPD2UDQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1013,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2802 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPD2UQQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1014,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2803 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2DQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1015,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2804 Instruction:"VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x69 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2IBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1016,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2805 Instruction:"VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x6B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2IUBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1017,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2806 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2PD,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1018,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2807 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1019,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2808 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPH2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_F16C,
+ .Mnemonic = 1019,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_F16C,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2809 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPH2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_F16C,
+ .Mnemonic = 1019,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_F16C,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2810 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2PSX,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1020,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2811 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2QQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1021,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2812 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2UDQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1022,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2813 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2UQQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1023,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2814 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2UW,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1024,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2815 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPH2W,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1025,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2816 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1026,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2817 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPS2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1026,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2818 Instruction:"VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x69 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2IBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1027,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2819 Instruction:"VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x6B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2IUBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1028,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2820 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1029,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2821 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPS2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1029,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2822 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTPS2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1029,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2823 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VCVTPS2PH,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1030,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2824 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_VCVTPS2PH,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_F16C,
+ .Mnemonic = 1030,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_F16C,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2825 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_VCVTPS2PH,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_F16C,
+ .Mnemonic = 1030,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_11,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_F16C,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2826 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2PHX,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1031,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2827 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2QQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1032,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2828 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2UDQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1033,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2829 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTPS2UQQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1034,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2830 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTQQ2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1035,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2831 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTQQ2PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1036,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2832 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTQQ2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1037,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2833 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTSD2SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1038,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2834 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSD2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1039,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2835 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSD2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1039,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2836 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTSD2SS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1040,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2837 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSD2SS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1040,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2838 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSD2USI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1041,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2839 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTSH2SD,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1042,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2840 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSH2SI,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1043,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2841 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTSH2SS,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1044,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2842 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSH2USI,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1045,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2843 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSI2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1046,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2844 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSI2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1046,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2845 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSI2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1046,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2846 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSI2SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1047,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_OE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2847 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSI2SS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1048,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2848 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSI2SS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1048,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2849 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTSS2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1049,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2850 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTSS2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1049,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2851 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VCVTSS2SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1050,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2852 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSS2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1051,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2853 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSS2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1051,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2854 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTSS2USI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1052,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2855 Instruction:"VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x68 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTNEBF162IBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1053,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2856 Instruction:"VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTNEBF162IUBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1054,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2857 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1055,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2858 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTPD2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1055,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2859 Instruction:"VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2DQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1056,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2860 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2QQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1057,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2861 Instruction:"VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2QQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1058,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2862 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2UDQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1059,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2863 Instruction:"VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2UDQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1060,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2864 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2UQQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1061,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2865 Instruction:"VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPD2UQQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1062,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2866 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2DQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1063,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2867 Instruction:"VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x68 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2IBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1064,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2868 Instruction:"VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2IUBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1065,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2869 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2QQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1066,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2870 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2UDQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1067,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2871 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2UQQ,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1068,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2872 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2UW,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1069,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2873 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPH2W,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1070,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2874 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1071,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2875 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTPS2DQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1071,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2876 Instruction:"VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2DQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1072,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2877 Instruction:"VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x68 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2IBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1073,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2878 Instruction:"VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2IUBS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1074,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2879 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2QQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1075,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2880 Instruction:"VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2QQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1076,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2881 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2UDQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1077,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2882 Instruction:"VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2UDQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1078,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2883 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2UQQ,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1079,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2884 Instruction:"VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTTPS2UQQS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1080,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2885 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSD2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1081,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2886 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSD2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1081,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2887 Instruction:"VCVTTSD2SIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6D /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSD2SIS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1082,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2888 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSD2USI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1083,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2889 Instruction:"VCVTTSD2USIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6C /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSD2USIS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1084,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2890 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSH2SI,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1085,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2891 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSH2USI,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1086,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2892 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSS2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1087,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2893 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSS2SI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1087,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2894 Instruction:"VCVTTSS2SIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6D /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSS2SIS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1088,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2895 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSS2USI,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1089,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1F,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2896 Instruction:"VCVTTSS2USIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6C /r"/"RM"
+ {
+ .Instruction = ND_INS_VCVTTSS2USIS,
+ .Category = ND_CAT_AVX10SCONVERT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1090,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:2897 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTUDQ2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1091,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HV,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2898 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTUDQ2PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1092,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2899 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTUDQ2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1093,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2900 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTUQQ2PD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1094,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2901 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTUQQ2PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1095,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2902 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTUQQ2PS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1096,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2903 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTUSI2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1097,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2904 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTUSI2SD,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1097,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2905 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTUSI2SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1098,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2906 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VCVTUSI2SS,
+ .Category = ND_CAT_CONVERT,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1099,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2907 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTUW2PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1100,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE|ND_SIMD_EXC_OE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2908 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VCVTW2PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1101,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2909 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VDBPSADBW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1102,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2910 Instruction:"VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDIVNEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1103,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2911 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDIVPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2912 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
+ {
+ .Instruction = ND_INS_VDIVPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1104,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2913 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDIVPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1105,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2914 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDIVPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2915 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
+ {
+ .Instruction = ND_INS_VDIVPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1106,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2916 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDIVSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1107,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2917 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
+ {
+ .Instruction = ND_INS_VDIVSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1107,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2918 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDIVSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1108,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2919 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDIVSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1109,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2920 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
+ {
+ .Instruction = ND_INS_VDIVSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1109,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2921 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDPBF16PS,
+ .Category = ND_CAT_AVX512BF16,
+ .IsaSet = ND_SET_AVX512BF16,
+ .Mnemonic = 1110,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BF16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2922 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VDPPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1111,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2923 Instruction:"VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x52 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VDPPHPS,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1112,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2924 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VDPPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1113,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2925 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
+ {
+ .Instruction = ND_INS_VERR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 1114,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2926 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
+ {
+ .Instruction = ND_INS_VERW,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I286PROT,
+ .Mnemonic = 1115,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:2927 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VEXP2PD,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1116,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2928 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VEXP2PS,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1117,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2929 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VEXPANDPD,
+ .Category = ND_CAT_EXPAND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1118,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2930 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VEXPANDPS,
+ .Category = ND_CAT_EXPAND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1119,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2931 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_VEXTRACTF128,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1120,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2932 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTF32X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1121,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2933 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTF32X8,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1122,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T8,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2934 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTF64X2,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1123,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2935 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTF64X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1124,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2936 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
+ {
+ .Instruction = ND_INS_VEXTRACTI128,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1125,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2937 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTI32X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1126,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2938 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTI32X8,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1127,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T8,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2939 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTI64X2,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1128,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2940 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
+ {
+ .Instruction = ND_INS_VEXTRACTI64X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1129,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2941 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VEXTRACTPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1130,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2942 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VEXTRACTPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1130,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2943 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VEXTRACTPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1130,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2944 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VEXTRACTPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1130,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2945 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFCMADDCPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1131,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2946 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFCMADDCSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1132,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2947 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFCMULCPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1133,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2948 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFCMULCSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1134,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2949 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VFIXUPIMMPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1135,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2950 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VFIXUPIMMPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1136,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2951 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VFIXUPIMMSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1137,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2952 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VFIXUPIMMSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1138,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2953 Instruction:"VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x98 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD132NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1139,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2954 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1140,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2955 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1140,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2956 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD132PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1141,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2957 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1142,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2958 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1142,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2959 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1143,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2960 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1143,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2961 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD132SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1144,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2962 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1145,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2963 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1145,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2964 Instruction:"VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xA8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD213NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1146,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2965 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1147,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2966 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1147,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2967 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD213PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1148,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2968 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1149,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2969 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1149,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2970 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1150,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2971 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1150,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2972 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD213SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1151,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2973 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1152,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2974 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1152,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2975 Instruction:"VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xB8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD231NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1153,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2976 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1154,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2977 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1154,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2978 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD231PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1155,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2979 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1156,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2980 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1156,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2981 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1157,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2982 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1157,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2983 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD231SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1158,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2984 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADD231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1159,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2985 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADD231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1159,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2986 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDCPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1160,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:2987 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDCSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1161,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:2988 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMADDPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1162,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2989 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMADDPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1162,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2990 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMADDPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1163,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2991 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMADDPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1163,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2992 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMADDSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1164,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2993 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMADDSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1164,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2994 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMADDSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1165,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2995 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMADDSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1165,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2996 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1166,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:2997 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1166,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:2998 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB132PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1167,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:2999 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1168,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3000 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1168,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3001 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1169,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3002 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1169,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3003 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB213PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1170,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3004 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3005 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1171,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3006 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3007 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1172,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3008 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB231PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1173,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3009 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3010 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMADDSUB231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1174,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3011 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMADDSUBPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3012 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMADDSUBPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1175,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3013 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMADDSUBPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3014 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMADDSUBPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1176,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3015 Instruction:"VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB132NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1177,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3016 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3017 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1178,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3018 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB132PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1179,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3019 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3020 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1180,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3021 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3022 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1181,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3023 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB132SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1182,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3024 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3025 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1183,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3026 Instruction:"VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB213NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1184,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3027 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3028 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1185,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3029 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB213PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1186,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3030 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1187,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3031 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1187,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3032 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1188,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3033 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1188,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3034 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB213SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1189,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3035 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1190,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3036 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1190,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3037 Instruction:"VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB231NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1191,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3038 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1192,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3039 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1192,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3040 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB231PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1193,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3041 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1194,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3042 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1194,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3043 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1195,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3044 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1195,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3045 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB231SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1196,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3046 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUB231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1197,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3047 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUB231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1197,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3048 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1198,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3049 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1198,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3050 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD132PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1199,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3051 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1200,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3052 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1200,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3053 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1201,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3054 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1201,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3055 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD213PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1202,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3056 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1203,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3057 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1203,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3058 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1204,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3059 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1204,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3060 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD231PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1205,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3061 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1206,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3062 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFMSUBADD231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1206,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3063 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMSUBADDPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1207,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3064 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMSUBADDPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1207,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3065 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMSUBADDPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1208,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3066 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMSUBADDPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1208,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3067 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMSUBPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1209,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3068 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMSUBPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1209,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3069 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMSUBPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1210,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3070 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMSUBPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1210,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3071 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMSUBSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1211,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3072 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMSUBSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1211,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3073 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFMSUBSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1212,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3074 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFMSUBSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1212,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3075 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMULCPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1213,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3076 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFMULCSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1214,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10S,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3077 Instruction:"VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD132NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1215,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3078 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1216,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3079 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1216,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3080 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD132PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1217,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3081 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1218,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3082 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1218,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3083 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1219,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3084 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1219,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3085 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD132SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1220,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3086 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1221,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3087 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1221,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3088 Instruction:"VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD213NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1222,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3089 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1223,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3090 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1223,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3091 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD213PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1224,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3092 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1225,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3093 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1225,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3094 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1226,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3095 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1226,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3096 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD213SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1227,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3097 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1228,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3098 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1228,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3099 Instruction:"VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD231NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1229,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3100 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1230,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3101 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1230,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3102 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD231PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1231,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3103 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1232,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3104 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1232,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3105 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1233,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3106 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1233,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3107 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD231SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1234,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3108 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMADD231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1235,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3109 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMADD231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1235,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3110 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMADDPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1236,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3111 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMADDPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1236,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3112 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMADDPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1237,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3113 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMADDPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1237,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3114 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMADDSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1238,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3115 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMADDSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1238,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3116 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMADDSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1239,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3117 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMADDSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1239,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3118 Instruction:"VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1240,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3119 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1241,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3120 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1241,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3121 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1242,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3122 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1243,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3123 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1243,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3124 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1244,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3125 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1244,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3126 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1245,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3127 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1246,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3128 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB132SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1246,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3129 Instruction:"VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1247,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3130 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1248,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3131 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1248,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3132 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1249,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3133 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1250,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3134 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1250,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3135 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1251,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3136 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1251,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3137 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1252,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3138 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1253,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3139 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB213SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1253,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3140 Instruction:"VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231NEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1254,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3141 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1255,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3142 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231PD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1255,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3143 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231PH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1256,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3144 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1257,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3145 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231PS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1257,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3146 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1258,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3147 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231SD,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1258,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3148 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231SH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1259,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3149 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1260,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3150 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VFNMSUB231SS,
+ .Category = ND_CAT_VFMA,
+ .IsaSet = ND_SET_FMA,
+ .Mnemonic = 1260,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3151 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMSUBPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1261,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3152 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMSUBPD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1261,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3153 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMSUBPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1262,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3154 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMSUBPS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1262,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3155 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMSUBSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1263,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3156 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMSUBSD,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1263,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3157 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VFNMSUBSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1264,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3158 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VFNMSUBSS,
+ .Category = ND_CAT_FMA4,
+ .IsaSet = ND_SET_FMA4,
+ .Mnemonic = 1264,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_FMA4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3159 Instruction:"VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x66 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VFPCLASSPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1265,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3160 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VFPCLASSPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1266,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3161 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VFPCLASSPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1267,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3162 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VFPCLASSPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1268,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3163 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VFPCLASSSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1269,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3164 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VFPCLASSSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1270,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3165 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VFPCLASSSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1271,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3166 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
+ {
+ .Instruction = ND_INS_VFRCZPD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1272,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3167 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
+ {
+ .Instruction = ND_INS_VFRCZPS,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1273,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3168 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
+ {
+ .Instruction = ND_INS_VFRCZSD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1274,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3169 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
+ {
+ .Instruction = ND_INS_VFRCZSS,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1275,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3170 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VGATHERDPD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1276,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3171 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VGATHERDPD,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1276,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3172 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VGATHERDPS,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1277,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3173 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VGATHERDPS,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1277,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3174 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF0DPD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1278,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3175 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF0DPS,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1279,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3176 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF0QPD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1280,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3177 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF0QPS,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1281,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3178 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF1DPD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1282,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3179 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF1DPS,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1283,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3180 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF1QPD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1284,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3181 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VGATHERPF1QPS,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1285,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3182 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VGATHERQPD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1286,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3183 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VGATHERQPD,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1286,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3184 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VGATHERQPS,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1287,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3185 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VGATHERQPS,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1287,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3186 Instruction:"VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x42 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VGETEXPPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1288,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3187 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VGETEXPPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1289,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3188 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VGETEXPPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1290,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3189 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VGETEXPPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1291,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3190 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VGETEXPSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1292,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3191 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VGETEXPSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1293,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3192 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VGETEXPSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1294,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3193 Instruction:"VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x26 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VGETMANTPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1295,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3194 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VGETMANTPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1296,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3195 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VGETMANTPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1297,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3196 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VGETMANTPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1298,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3197 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VGETMANTSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1299,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3198 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VGETMANTSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1300,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3199 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VGETMANTSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1301,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3200 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VGF2P8AFFINEINVQB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 1302,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3201 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VGF2P8AFFINEINVQB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 1302,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3202 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VGF2P8AFFINEQB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 1303,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3203 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VGF2P8AFFINEQB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 1303,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3204 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VGF2P8MULB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 1304,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3205 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VGF2P8MULB,
+ .Category = ND_CAT_GFNI,
+ .IsaSet = ND_SET_GFNI,
+ .Mnemonic = 1304,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_GFNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3206 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VHADDPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1305,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3207 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VHADDPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1306,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3208 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VHSUBPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1307,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3209 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VHSUBPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1308,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3210 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VINSERTF128,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1309,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3211 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTF32X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1310,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3212 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTF32X8,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1311,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T8,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3213 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTF64X2,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1312,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3214 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTF64X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1313,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3215 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VINSERTI128,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1314,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3216 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTI32X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1315,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3217 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTI32X8,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1316,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T8,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3218 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTI64X2,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1317,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3219 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VINSERTI64X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1318,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T4,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3220 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VINSERTPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1319,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3221 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VINSERTPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1319,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3222 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VINSERTPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1319,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3223 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VINSERTPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1319,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3224 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VLDDQU,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1320,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3225 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
+ {
+ .Instruction = ND_INS_VLDMXCSR,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1321,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3226 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VMASKMOVDQU,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1322,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_pDI, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3227 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMASKMOVPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1323,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3228 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
+ {
+ .Instruction = ND_INS_VMASKMOVPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1323,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3229 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMASKMOVPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1324,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3230 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
+ {
+ .Instruction = ND_INS_VMASKMOVPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1324,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3231 Instruction:"VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMAXPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1325,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3232 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMAXPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1326,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3233 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMAXPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1326,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3234 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMAXPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1327,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3235 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMAXPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1328,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3236 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMAXPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1328,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3237 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMAXSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1329,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3238 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMAXSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1329,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3239 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMAXSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1330,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3240 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMAXSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1331,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3241 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMAXSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1331,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3242 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/""
+ {
+ .Instruction = ND_INS_VMCALL,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1332,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:3243 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_VMCLEAR,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1333,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3244 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
+ {
+ .Instruction = ND_INS_VMFUNC,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1334,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:3245 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
+ {
+ .Instruction = ND_INS_VMGEXIT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 1335,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:3246 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
+ {
+ .Instruction = ND_INS_VMGEXIT,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 1335,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:3247 Instruction:"VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x52 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMINMAXNEPBF16,
+ .Category = ND_CAT_AVX10MINMAX,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1336,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3248 Instruction:"VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x52 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMINMAXPD,
+ .Category = ND_CAT_AVX10MINMAX,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1337,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3249 Instruction:"VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x52 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMINMAXPH,
+ .Category = ND_CAT_AVX10MINMAX,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1338,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3250 Instruction:"VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x52 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMINMAXPS,
+ .Category = ND_CAT_AVX10MINMAX,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1339,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3251 Instruction:"VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x53 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMINMAXSD,
+ .Category = ND_CAT_AVX10MINMAX,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1340,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3252 Instruction:"VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x53 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMINMAXSH,
+ .Category = ND_CAT_AVX10MINMAX,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1341,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3253 Instruction:"VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x53 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMINMAXSS,
+ .Category = ND_CAT_AVX10MINMAX,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1342,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3254 Instruction:"VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMINPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1343,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3255 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMINPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3256 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMINPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1344,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3257 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMINPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1345,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3258 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMINPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1346,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3259 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMINPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1346,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3260 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMINSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3261 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMINSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1347,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3262 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMINSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1348,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3263 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMINSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1349,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3264 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMINSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1349,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3265 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/""
+ {
+ .Instruction = ND_INS_VMLAUNCH,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1350,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3266 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
+ {
+ .Instruction = ND_INS_VMLOAD,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 1351,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3267 Instruction:"VMMCALL" Encoding:"NP 0x0F 0x01 /0xD9"/""
+ {
+ .Instruction = ND_INS_VMMCALL,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 1352,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:3268 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
+ {
+ .Instruction = ND_INS_VMMCALL,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 1352,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:3269 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVAPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1353,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3270 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVAPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1353,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3271 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVAPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1353,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3272 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVAPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1353,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3273 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVAPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1354,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3274 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVAPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1354,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3275 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVAPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1354,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3276 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVAPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1354,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3277 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1355,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3278 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1355,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3279 Instruction:"VMOVD Vdq,Wd" Encoding:"evex m:1 p:2 l:0 w:0 0x7E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVD,
+ .Category = ND_CAT_AVX10PARTCOPY,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1355,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3280 Instruction:"VMOVD Wd,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0xD6 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVD,
+ .Category = ND_CAT_AVX10PARTCOPY,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1355,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3281 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1355,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3282 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1355,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3283 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1356,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_DUP,
+ .ExcType = ND_EXT_E5NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3284 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1356,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_DUP,
+ .ExcType = ND_EXT_E5NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3285 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1356,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_DUP,
+ .ExcType = ND_EXT_E5NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3286 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVDDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1356,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3287 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVDDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1356,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3288 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVDQA,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1357,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3289 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVDQA,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1357,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3290 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDQA32,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1358,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3291 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVDQA32,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1358,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3292 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDQA64,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1359,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3293 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVDQA64,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1359,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3294 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVDQU,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1360,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3295 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVDQU,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1360,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3296 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDQU16,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1361,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3297 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVDQU16,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1361,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3298 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDQU32,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1362,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3299 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVDQU32,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1362,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3300 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDQU64,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1363,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3301 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVDQU64,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1363,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3302 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVDQU8,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1364,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3303 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVDQU8,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1364,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3304 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVHLPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1365,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3305 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVHLPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1365,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3306 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVHPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1366,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3307 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVHPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1366,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3308 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVHPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1366,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3309 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVHPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1366,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3310 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1367,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3311 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1367,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3312 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1367,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3313 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1367,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3314 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVLHPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1368,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3315 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVLHPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1368,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3316 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVLPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1369,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3317 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVLPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1369,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3318 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVLPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1369,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3319 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVLPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1369,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3320 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVLPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1370,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3321 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVLPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1370,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T2,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3322 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVLPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1370,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3323 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVLPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1370,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3324 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VMOVMSKPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1371,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3325 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VMOVMSKPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1372,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3326 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVNTDQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1373,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3327 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVNTDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1373,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3328 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VMOVNTDQA,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1374,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3329 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VMOVNTDQA,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1374,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3330 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVNTPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1375,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3331 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVNTPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1375,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3332 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVNTPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1376,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E1NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3333 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVNTPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1376,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_1,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3334 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3335 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3336 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3337 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3338 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3339 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3340 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3341 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1377,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3342 Instruction:"VMOVRSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:3 l:x w:0 0x6F /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVRSB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 1378,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3343 Instruction:"VMOVRSD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:2 l:x w:0 0x6F /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVRSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 1379,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3344 Instruction:"VMOVRSQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:2 l:x w:1 0x6F /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVRSQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 1380,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3345 Instruction:"VMOVRSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:5 p:3 l:x w:1 0x6F /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVRSW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_MOVRS,
+ .Mnemonic = 1381,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_MOVRS,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3346 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3347 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3348 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3349 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3350 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3351 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3352 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3353 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVSD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1382,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3354 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1383,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3355 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
+ {
+ .Instruction = ND_INS_VMOVSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1383,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3356 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1383,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3357 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
+ {
+ .Instruction = ND_INS_VMOVSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1383,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3358 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVSHDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1384,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3359 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVSHDUP,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1384,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3360 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVSLDUP,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1385,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3361 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVSLDUP,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1385,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3362 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3363 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3364 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3365 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3366 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3367 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3368 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3369 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVSS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1386,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3370 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVUPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1387,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3371 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVUPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1387,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3372 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVUPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1387,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3373 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVUPD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1387,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3374 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VMOVUPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1388,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3375 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VMOVUPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1388,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3376 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVUPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1388,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3377 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVUPS,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1388,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3378 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM"
+ {
+ .Instruction = ND_INS_VMOVW,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1389,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3379 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VMOVW,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1389,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3380 Instruction:"VMOVW Vdq,Ww" Encoding:"evex m:5 p:2 l:0 w:0 0x6E /r"/"RM"
+ {
+ .Instruction = ND_INS_VMOVW,
+ .Category = ND_CAT_AVX10PARTCOPY,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1389,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3381 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_VMOVW,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1389,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3382 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR"
+ {
+ .Instruction = ND_INS_VMOVW,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1389,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3383 Instruction:"VMOVW Ww,Vdq" Encoding:"evex m:5 p:2 l:0 w:0 0x7E /r"/"MR"
+ {
+ .Instruction = ND_INS_VMOVW,
+ .Category = ND_CAT_AVX10PARTCOPY,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1389,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3384 Instruction:"VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:2 l:x w:0 0x42 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VMPSADBW,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1390,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3385 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VMPSADBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1390,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3386 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_VMPTRLD,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1391,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3387 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
+ {
+ .Instruction = ND_INS_VMPTRST,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1392,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3388 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
+ {
+ .Instruction = ND_INS_VMREAD,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1393,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_F64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3389 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/""
+ {
+ .Instruction = ND_INS_VMRESUME,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1394,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3390 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
+ {
+ .Instruction = ND_INS_VMRUN,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 1395,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3391 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
+ {
+ .Instruction = ND_INS_VMSAVE,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_SVM,
+ .Mnemonic = 1396,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_SVM,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:3392 Instruction:"VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x59 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMULNEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1397,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3393 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMULPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1398,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3394 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMULPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1398,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3395 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMULPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1399,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3396 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMULPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1400,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3397 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMULPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1400,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3398 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMULSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1401,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3399 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMULSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1401,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3400 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMULSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1402,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3401 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VMULSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1403,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:3402 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VMULSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1403,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3403 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
+ {
+ .Instruction = ND_INS_VMWRITE,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1404,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_F64|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3404 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/""
+ {
+ .Instruction = ND_INS_VMXOFF,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1405,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3405 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
+ {
+ .Instruction = ND_INS_VMXON,
+ .Category = ND_CAT_VTX,
+ .IsaSet = ND_SET_VTX,
+ .Mnemonic = 1406,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_VTX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3406 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VORPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3407 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VORPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1407,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3408 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VORPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3409 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VORPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1408,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3410 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VP2INTERSECTD,
+ .Category = ND_CAT_AVX512VP2INTERSECT,
+ .IsaSet = ND_SET_AVX512VP2INTERSECT,
+ .Mnemonic = 1409,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VP2INTERSECT,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3411 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VP2INTERSECTQ,
+ .Category = ND_CAT_AVX512VP2INTERSECT,
+ .IsaSet = ND_SET_AVX512VP2INTERSECT,
+ .Mnemonic = 1410,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VP2INTERSECT,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3412 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
+ {
+ .Instruction = ND_INS_VP4DPWSSD,
+ .Category = ND_CAT_VNNIW,
+ .IsaSet = ND_SET_AVX5124VNNIW,
+ .Mnemonic = 1411,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1_4X,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX5124VNNIW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3413 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
+ {
+ .Instruction = ND_INS_VP4DPWSSDS,
+ .Category = ND_CAT_VNNIW,
+ .IsaSet = ND_SET_AVX5124VNNIW,
+ .Mnemonic = 1412,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1_4X,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX5124VNNIW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4),
+ OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3414 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPABSB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1413,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3415 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
+ {
+ .Instruction = ND_INS_VPABSB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1413,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3416 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPABSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1414,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3417 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
+ {
+ .Instruction = ND_INS_VPABSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1414,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3418 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPABSQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1415,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3419 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPABSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1416,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3420 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
+ {
+ .Instruction = ND_INS_VPABSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1416,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3421 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPACKSSDW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1417,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3422 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPACKSSDW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1417,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3423 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPACKSSWB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1418,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3424 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPACKSSWB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1418,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3425 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPACKUSDW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1419,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3426 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPACKUSDW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1419,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3427 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPACKUSWB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1420,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3428 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPACKUSWB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1420,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3429 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1421,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3430 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1421,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3431 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1422,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3432 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1422,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3433 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1423,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3434 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1423,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3435 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDSB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1424,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3436 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDSB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1424,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3437 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1425,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3438 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1425,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3439 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDUSB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1426,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3440 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDUSB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1426,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3441 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDUSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1427,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3442 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDUSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1427,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3443 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPADDW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1428,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3444 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPADDW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1428,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3445 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPALIGNR,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1429,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3446 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPALIGNR,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1429,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3447 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPAND,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1430,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3448 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPANDD,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1431,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3449 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPANDN,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1432,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3450 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPANDND,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1433,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3451 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPANDNQ,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1434,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3452 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPANDQ,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1435,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3453 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPAVGB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1436,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3454 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPAVGB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1436,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3455 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPAVGW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1437,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3456 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPAVGW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1437,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3457 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPBLENDD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1438,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3458 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPBLENDMB,
+ .Category = ND_CAT_BLEND,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1439,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3459 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPBLENDMD,
+ .Category = ND_CAT_BLEND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1440,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3460 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPBLENDMQ,
+ .Category = ND_CAT_BLEND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1441,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3461 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPBLENDMW,
+ .Category = ND_CAT_BLEND,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1442,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3462 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPBLENDVB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1443,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3463 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPBLENDW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1444,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3464 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTB,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1445,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3465 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTB,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1445,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3466 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPBROADCASTB,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1445,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3467 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTD,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1446,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3468 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTD,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1446,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3469 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPBROADCASTD,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1446,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3470 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPBROADCASTMB2Q,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512CD,
+ .Mnemonic = 1447,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512CD,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3471 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPBROADCASTMW2D,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512CD,
+ .Mnemonic = 1448,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E6NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512CD,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3472 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTQ,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1449,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3473 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTQ,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1449,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3474 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPBROADCASTQ,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1449,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3475 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTW,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1450,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3476 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
+ {
+ .Instruction = ND_INS_VPBROADCASTW,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1450,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3477 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPBROADCASTW,
+ .Category = ND_CAT_BROADCAST,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1450,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3478 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCLMULQDQ,
+ .Category = ND_CAT_VPCLMULQDQ,
+ .IsaSet = ND_SET_VPCLMULQDQ,
+ .Mnemonic = 1451,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_VPCLMULQDQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3479 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCLMULQDQ,
+ .Category = ND_CAT_VPCLMULQDQ,
+ .IsaSet = ND_SET_VPCLMULQDQ,
+ .Mnemonic = 1451,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_VPCLMULQDQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3480 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPCMOV,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1452,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3481 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VPCMOV,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1452,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3482 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1453,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3483 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1454,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3484 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPEQB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1455,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3485 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPEQB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1455,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3486 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPEQD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1456,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3487 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPEQD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1456,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3488 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPEQQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1457,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3489 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPEQQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1457,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3490 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPEQW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1458,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3491 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPEQW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1458,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3492 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPCMPESTRI,
+ .Category = ND_CAT_STTNI,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1459,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 4),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3493 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPCMPESTRM,
+ .Category = ND_CAT_STTNI,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1460,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 4),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3494 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPGTB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1461,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3495 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPGTB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1461,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3496 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPGTD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1462,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3497 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPGTD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1462,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3498 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPGTQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1463,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3499 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPGTQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1463,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3500 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPCMPGTW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1464,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3501 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPCMPGTW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1464,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3502 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPCMPISTRI,
+ .Category = ND_CAT_STTNI,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1465,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3503 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPCMPISTRM,
+ .Category = ND_CAT_STTNI,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1466,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 2),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3504 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1467,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3505 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPUB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1468,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3506 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPUD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1469,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3507 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPUQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1470,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3508 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPUW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1471,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3509 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPCMPW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1472,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3510 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1473,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3511 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1474,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3512 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPCOMPRESSB,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1475,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3513 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPCOMPRESSD,
+ .Category = ND_CAT_COMPRESS,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1476,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3514 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPCOMPRESSQ,
+ .Category = ND_CAT_COMPRESS,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1477,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3515 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPCOMPRESSW,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1478,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3516 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1479,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3517 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMUB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1480,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3518 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMUD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1481,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3519 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMUQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1482,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3520 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMUW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1483,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3521 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPCOMW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1484,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3522 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPCONFLICTD,
+ .Category = ND_CAT_CONFLICT,
+ .IsaSet = ND_SET_AVX512CD,
+ .Mnemonic = 1485,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512CD,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3523 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPCONFLICTQ,
+ .Category = ND_CAT_CONFLICT,
+ .IsaSet = ND_SET_AVX512CD,
+ .Mnemonic = 1486,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512CD,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3524 Instruction:"VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x50 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBSSD,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1487,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3525 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBSSD,
+ .Category = ND_CAT_AVXVNNIINT8,
+ .IsaSet = ND_SET_AVXVNNIINT8,
+ .Mnemonic = 1487,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT8,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3526 Instruction:"VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x51 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBSSDS,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1488,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3527 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBSSDS,
+ .Category = ND_CAT_AVXVNNIINT8,
+ .IsaSet = ND_SET_AVXVNNIINT8,
+ .Mnemonic = 1488,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT8,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3528 Instruction:"VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x50 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBSUD,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1489,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3529 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBSUD,
+ .Category = ND_CAT_AVXVNNIINT8,
+ .IsaSet = ND_SET_AVXVNNIINT8,
+ .Mnemonic = 1489,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT8,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3530 Instruction:"VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x51 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBSUDS,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1490,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3531 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBSUDS,
+ .Category = ND_CAT_AVXVNNIINT8,
+ .IsaSet = ND_SET_AVXVNNIINT8,
+ .Mnemonic = 1490,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT8,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3532 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBUSD,
+ .Category = ND_CAT_VNNI,
+ .IsaSet = ND_SET_AVX512VNNI,
+ .Mnemonic = 1491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3533 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBUSD,
+ .Category = ND_CAT_AVXVNNI,
+ .IsaSet = ND_SET_AVXVNNI,
+ .Mnemonic = 1491,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3534 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBUSDS,
+ .Category = ND_CAT_VNNI,
+ .IsaSet = ND_SET_AVX512VNNI,
+ .Mnemonic = 1492,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3535 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBUSDS,
+ .Category = ND_CAT_AVXVNNI,
+ .IsaSet = ND_SET_AVXVNNI,
+ .Mnemonic = 1492,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3536 Instruction:"VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x50 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBUUD,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1493,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3537 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBUUD,
+ .Category = ND_CAT_AVXVNNIINT8,
+ .IsaSet = ND_SET_AVXVNNIINT8,
+ .Mnemonic = 1493,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT8,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3538 Instruction:"VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x51 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPBUUDS,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3539 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPBUUDS,
+ .Category = ND_CAT_AVXVNNIINT8,
+ .IsaSet = ND_SET_AVXVNNIINT8,
+ .Mnemonic = 1494,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT8,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3540 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWSSD,
+ .Category = ND_CAT_VNNI,
+ .IsaSet = ND_SET_AVX512VNNI,
+ .Mnemonic = 1495,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3541 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWSSD,
+ .Category = ND_CAT_AVXVNNI,
+ .IsaSet = ND_SET_AVXVNNI,
+ .Mnemonic = 1495,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3542 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWSSDS,
+ .Category = ND_CAT_VNNI,
+ .IsaSet = ND_SET_AVX512VNNI,
+ .Mnemonic = 1496,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3543 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWSSDS,
+ .Category = ND_CAT_AVXVNNI,
+ .IsaSet = ND_SET_AVXVNNI,
+ .Mnemonic = 1496,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3544 Instruction:"VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD2 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWSUD,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1497,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3545 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWSUD,
+ .Category = ND_CAT_AVXVNNIINT16,
+ .IsaSet = ND_SET_AVXVNNIINT16,
+ .Mnemonic = 1497,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3546 Instruction:"VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD3 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWSUDS,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1498,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3547 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWSUDS,
+ .Category = ND_CAT_AVXVNNIINT16,
+ .IsaSet = ND_SET_AVXVNNIINT16,
+ .Mnemonic = 1498,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3548 Instruction:"VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD2 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWUSD,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1499,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3549 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWUSD,
+ .Category = ND_CAT_AVXVNNIINT16,
+ .IsaSet = ND_SET_AVXVNNIINT16,
+ .Mnemonic = 1499,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3550 Instruction:"VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD3 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWUSDS,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1500,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3551 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWUSDS,
+ .Category = ND_CAT_AVXVNNIINT16,
+ .IsaSet = ND_SET_AVXVNNIINT16,
+ .Mnemonic = 1500,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3552 Instruction:"VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD2 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWUUD,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1501,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3553 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWUUD,
+ .Category = ND_CAT_AVXVNNIINT16,
+ .IsaSet = ND_SET_AVXVNNIINT16,
+ .Mnemonic = 1501,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3554 Instruction:"VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD3 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPDPWUUDS,
+ .Category = ND_CAT_AVX10INT,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1502,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3555 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPDPWUUDS,
+ .Category = ND_CAT_AVXVNNIINT16,
+ .IsaSet = ND_SET_AVXVNNIINT16,
+ .Mnemonic = 1502,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXVNNIINT16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3556 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPERM2F128,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1503,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3557 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPERM2I128,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1504,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3558 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMB,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI,
+ .Mnemonic = 1505,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3559 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1506,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3560 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPERMD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1506,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3561 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMI2B,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI,
+ .Mnemonic = 1507,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3562 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMI2D,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1508,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3563 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMI2PD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1509,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3564 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMI2PS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1510,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3565 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMI2Q,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1511,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3566 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMI2W,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1512,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3567 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVMLL"
+ {
+ .Instruction = ND_INS_VPERMIL2PD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1513,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3568 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLML"
+ {
+ .Instruction = ND_INS_VPERMIL2PD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1513,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3569 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVMLL"
+ {
+ .Instruction = ND_INS_VPERMIL2PS,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1514,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3570 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLML"
+ {
+ .Instruction = ND_INS_VPERMIL2PS,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1514,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3571 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMILPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1515,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3572 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VPERMILPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1515,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3573 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPERMILPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1515,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3574 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPERMILPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1515,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3575 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMILPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1516,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3576 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VPERMILPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1516,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3577 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPERMILPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1516,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3578 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPERMILPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1516,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3579 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1517,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3580 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1517,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3581 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VPERMPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1517,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3582 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPERMPD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1517,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3583 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3584 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3585 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPERMPS,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1518,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3586 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1519,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3587 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VPERMQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1519,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3588 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPERMQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1519,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3589 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMT2B,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI,
+ .Mnemonic = 1520,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3590 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMT2D,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1521,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3591 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMT2PD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1522,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3592 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMT2PS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1523,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3593 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMT2Q,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1524,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3594 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMT2W,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1525,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3595 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPERMW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1526,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3596 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPEXPANDB,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1527,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3597 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPEXPANDD,
+ .Category = ND_CAT_EXPAND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1528,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3598 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPEXPANDQ,
+ .Category = ND_CAT_EXPAND,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1529,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3599 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPEXPANDW,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1530,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3600 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1531,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3601 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1531,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3602 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1531,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3603 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1531,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3604 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1532,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3605 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1532,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3606 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1532,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3607 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1532,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3608 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1533,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3609 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1533,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3610 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1533,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3611 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1533,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3612 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPEXTRW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3613 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3614 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3615 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPEXTRW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3616 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3617 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+ {
+ .Instruction = ND_INS_VPEXTRW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1534,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3618 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VPGATHERDD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1535,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3619 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VPGATHERDD,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1535,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3620 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VPGATHERDQ,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1536,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3621 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VPGATHERDQ,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1536,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3622 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VPGATHERQD,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1537,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3623 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VPGATHERQD,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1537,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3624 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
+ {
+ .Instruction = ND_INS_VPGATHERQQ,
+ .Category = ND_CAT_GATHER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1538,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3625 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
+ {
+ .Instruction = ND_INS_VPGATHERQQ,
+ .Category = ND_CAT_AVX2GATHER,
+ .IsaSet = ND_SET_AVX2GATHER,
+ .Mnemonic = 1538,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0),
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3626 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDBD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1539,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3627 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDBQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1540,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3628 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDBW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1541,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3629 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPHADDD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1542,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3630 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDDQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1543,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3631 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPHADDSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1544,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3632 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDUBD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1545,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3633 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDUBQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1546,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3634 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDUBW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1547,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3635 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDUDQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1548,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3636 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDUWD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1549,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3637 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDUWQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1550,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3638 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPHADDW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1551,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3639 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDWD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1552,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3640 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHADDWQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1553,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3641 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHMINPOSUW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1554,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3642 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHSUBBW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1555,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3643 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPHSUBD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1556,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3644 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHSUBDQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1557,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3645 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPHSUBSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1558,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3646 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPHSUBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1559,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3647 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPHSUBWD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1560,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3648 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1561,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3649 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1561,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S8,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3650 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1561,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3651 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1561,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3652 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1562,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3653 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1562,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3654 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1563,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3655 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1563,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3656 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1564,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3657 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1564,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E9NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3658 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1564,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3659 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VPINSRW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1564,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3660 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPLZCNTD,
+ .Category = ND_CAT_CONFLICT,
+ .IsaSet = ND_SET_AVX512CD,
+ .Mnemonic = 1565,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512CD,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3661 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPLZCNTQ,
+ .Category = ND_CAT_CONFLICT,
+ .IsaSet = ND_SET_AVX512CD,
+ .Mnemonic = 1566,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512CD,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3662 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSDD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1567,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3663 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSDQH,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1568,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3664 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSDQL,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1569,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3665 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSSDD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1570,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3666 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSSDQH,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1571,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3667 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSSDQL,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1572,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3668 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSSWD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1573,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3669 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSSWW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1574,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3670 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSWD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1575,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3671 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMACSWW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1576,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3672 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMADCSSWD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1577,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3673 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPMADCSWD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1578,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3674 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMADD52HUQ,
+ .Category = ND_CAT_IFMA,
+ .IsaSet = ND_SET_AVX512IFMA,
+ .Mnemonic = 1579,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512IFMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3675 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMADD52HUQ,
+ .Category = ND_CAT_AVXIFMA,
+ .IsaSet = ND_SET_AVXIFMA,
+ .Mnemonic = 1579,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXIFMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3676 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMADD52LUQ,
+ .Category = ND_CAT_IFMA,
+ .IsaSet = ND_SET_AVX512IFMA,
+ .Mnemonic = 1580,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512IFMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3677 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMADD52LUQ,
+ .Category = ND_CAT_AVXIFMA,
+ .IsaSet = ND_SET_AVXIFMA,
+ .Mnemonic = 1580,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVXIFMA,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3678 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMADDUBSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1581,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3679 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMADDUBSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1581,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3680 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMADDWD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1582,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3681 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMADDWD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1582,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3682 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VPMASKMOVD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1583,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3683 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
+ {
+ .Instruction = ND_INS_VPMASKMOVD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1583,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3684 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
+ {
+ .Instruction = ND_INS_VPMASKMOVQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1584,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3685 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
+ {
+ .Instruction = ND_INS_VPMASKMOVQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1584,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3686 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXSB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1585,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3687 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMAXSB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1585,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3688 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1586,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3689 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMAXSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1586,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3690 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXSQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1587,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3691 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1588,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3692 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMAXSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1588,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3693 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXUB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1589,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3694 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMAXUB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1589,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3695 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXUD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1590,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3696 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMAXUD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1590,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3697 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXUQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1591,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3698 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMAXUW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1592,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3699 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMAXUW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1592,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3700 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINSB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1593,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3701 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMINSB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1593,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3702 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1594,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3703 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMINSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1594,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3704 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINSQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1595,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3705 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1596,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3706 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMINSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1596,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3707 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINUB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1597,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3708 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMINUB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1597,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3709 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINUD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1598,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3710 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMINUD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1598,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3711 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINUQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1599,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3712 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMINUW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1600,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3713 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMINUW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1600,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3714 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVB2M,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1601,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3715 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVD2M,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1602,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3716 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVDB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1603,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3717 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVDW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1604,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3718 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVM2B,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1605,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3719 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVM2D,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1606,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3720 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVM2Q,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1607,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3721 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVM2W,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1608,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3722 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVMSKB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1609,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3723 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVQ2M,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1610,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3724 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVQB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1611,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_OVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3725 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVQD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1612,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3726 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVQW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1613,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3727 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVSDB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1614,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3728 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVSDW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1615,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3729 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVSQB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1616,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_OVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3730 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVSQD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1617,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3731 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVSQW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1618,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3732 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVSWB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1619,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3733 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVSXBD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1620,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3734 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXBD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1620,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3735 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXBD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1620,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3736 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVSXBQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1621,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_OVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3737 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXBQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1621,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3738 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXBQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1621,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3739 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVSXBW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1622,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3740 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1622,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3741 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXBW,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1622,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3742 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVSXDQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1623,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3743 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1623,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3744 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXDQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1623,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3745 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVSXWD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1624,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3746 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXWD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1624,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3747 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXWD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1624,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3748 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVSXWQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1625,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3749 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXWQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1625,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3750 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVSXWQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1625,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3751 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVUSDB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1626,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3752 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVUSDW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1627,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3753 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVUSQB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1628,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_OVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3754 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVUSQD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1629,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3755 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVUSQW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1630,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3756 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVUSWB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1631,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3757 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVW2M,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1632,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_E7NM,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3758 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
+ {
+ .Instruction = ND_INS_VPMOVWB,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1633,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3759 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVZXBD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1634,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3760 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXBD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1634,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3761 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXBD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1634,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3762 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVZXBQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1635,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_OVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3763 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXBQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1635,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3764 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXBQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1635,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3765 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVZXBW,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1636,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3766 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1636,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3767 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXBW,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1636,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3768 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVZXDQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1637,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3769 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1637,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3770 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXDQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1637,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3771 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVZXWD,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1638,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_HVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3772 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXWD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1638,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3773 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXWD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1638,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3774 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPMOVZXWQ,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1639,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_QVM,
+ .ExcType = ND_EXT_E5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3775 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXWQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1639,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3776 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPMOVZXWQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1639,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3777 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1640,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3778 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMULDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1640,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3779 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULHRSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1641,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3780 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMULHRSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1641,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3781 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULHUW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1642,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3782 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMULHUW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1642,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3783 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULHW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1643,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3784 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMULHW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1643,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3785 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULLD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1644,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3786 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMULLD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1644,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3787 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULLQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1645,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3788 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULLW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1646,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3789 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMULLW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1646,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3790 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULTISHIFTQB,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI,
+ .Mnemonic = 1647,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3791 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPMULUDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1648,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3792 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPMULUDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1648,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3793 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPOPCNTB,
+ .Category = ND_CAT_VPOPCNT,
+ .IsaSet = ND_SET_AVX512BITALG,
+ .Mnemonic = 1649,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BITALG,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3794 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPOPCNTD,
+ .Category = ND_CAT_VPOPCNT,
+ .IsaSet = ND_SET_AVX512VPOPCNTDQ,
+ .Mnemonic = 1650,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3795 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPOPCNTQ,
+ .Category = ND_CAT_VPOPCNT,
+ .IsaSet = ND_SET_AVX512VPOPCNTDQ,
+ .Mnemonic = 1651,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3796 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VPOPCNTW,
+ .Category = ND_CAT_VPOPCNT,
+ .IsaSet = ND_SET_AVX512BITALG,
+ .Mnemonic = 1652,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BITALG,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3797 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPOR,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1653,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3798 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPORD,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1654,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3799 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPORQ,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1655,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3800 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
+ {
+ .Instruction = ND_INS_VPPERM,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1656,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3801 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
+ {
+ .Instruction = ND_INS_VPPERM,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1656,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3802 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPROLD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1657,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3803 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPROLQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1658,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3804 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPROLVD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1659,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3805 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPROLVQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1660,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3806 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPRORD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1661,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3807 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPRORQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1662,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3808 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPRORVD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1663,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3809 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPRORVQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1664,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3810 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPROTB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1665,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3811 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPROTB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1665,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3812 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPROTB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1665,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3813 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPROTD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3814 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPROTD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3815 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPROTD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1666,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3816 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPROTQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1667,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3817 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPROTQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1667,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3818 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPROTQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1667,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3819 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPROTW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1668,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3820 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPROTW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1668,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3821 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPROTW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1668,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3822 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSADBW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1669,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3823 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSADBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1669,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3824 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VPSCATTERDD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1670,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3825 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VPSCATTERDQ,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1671,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3826 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VPSCATTERQD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1672,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3827 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VPSCATTERQQ,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1673,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:3828 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHAB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1674,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3829 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHAB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1674,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3830 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHAD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3831 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHAD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1675,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3832 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHAQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1676,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3833 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHAQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1676,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3834 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHAW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1677,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3835 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHAW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1677,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3836 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHLB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1678,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3837 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHLB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1678,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3838 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHLB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1678,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3839 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHLB,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1678,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3840 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHLD,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1679,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3841 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPSHLDD,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1680,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3842 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPSHLDQ,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1681,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3843 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHLDVD,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1682,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3844 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHLDVQ,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1683,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3845 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHLDVW,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1684,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3846 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPSHLDW,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1685,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3847 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHLQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1686,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3848 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHLQ,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1686,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3849 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
+ {
+ .Instruction = ND_INS_VPSHLW,
+ .Category = ND_CAT_XOP,
+ .IsaSet = ND_SET_XOP,
+ .Mnemonic = 1687,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_XOP,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3850 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPSHRDD,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1688,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3851 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPSHRDQ,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1689,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3852 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHRDVD,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1690,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3853 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHRDVQ,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1691,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3854 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHRDVW,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1692,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3855 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPSHRDW,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512VBMI2,
+ .Mnemonic = 1693,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512VBMI2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3856 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHUFB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1694,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3857 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSHUFB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1694,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3858 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSHUFBITQMB,
+ .Category = ND_CAT_AVX512VBMI,
+ .IsaSet = ND_SET_AVX512BITALG,
+ .Mnemonic = 1695,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BITALG,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3859 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VPSHUFD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1696,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3860 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPSHUFD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1696,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3861 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VPSHUFHW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1697,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3862 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPSHUFHW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1697,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3863 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VPSHUFLW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1698,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3864 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VPSHUFLW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1698,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3865 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSIGNB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1699,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3866 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSIGND,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1700,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3867 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSIGNW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1701,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3868 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSLLD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1702,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3869 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSLLD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1702,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3870 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSLLD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1702,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3871 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSLLD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1702,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3872 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSLLDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1703,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3873 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSLLDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1703,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3874 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSLLQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3875 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSLLQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3876 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSLLQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3877 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSLLQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1704,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3878 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSLLVD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1705,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3879 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSLLVD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1705,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3880 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSLLVQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1706,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3881 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSLLVQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1706,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3882 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSLLVW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1707,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3883 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSLLW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3884 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSLLW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3885 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSLLW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3886 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSLLW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1708,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3887 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSRAD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1709,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3888 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRAD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1709,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3889 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSRAD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1709,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3890 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRAD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1709,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3891 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSRAQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1710,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3892 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRAQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1710,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3893 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRAVD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1711,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3894 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRAVD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1711,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3895 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRAVQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1712,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3896 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRAVW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1713,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3897 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSRAW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1714,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3898 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRAW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1714,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3899 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSRAW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1714,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3900 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRAW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1714,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3901 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSRLD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1715,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3902 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRLD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1715,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3903 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSRLD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1715,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3904 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRLD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1715,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3905 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSRLDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1716,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3906 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSRLDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1716,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3907 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSRLQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1717,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3908 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRLQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1717,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3909 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSRLQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1717,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3910 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRLQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1717,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3911 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRLVD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1718,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3912 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRLVD,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1718,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3913 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRLVQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1719,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3914 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRLVQ,
+ .Category = ND_CAT_AVX2,
+ .IsaSet = ND_SET_AVX2,
+ .Mnemonic = 1719,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3915 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRLVW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1720,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3916 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
+ {
+ .Instruction = ND_INS_VPSRLW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1721,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3917 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSRLW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1721,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_M128,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3918 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
+ {
+ .Instruction = ND_INS_VPSRLW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1721,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_7,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3919 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSRLW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1721,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3920 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1722,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3921 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1722,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3922 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1723,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3923 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1723,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3924 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1724,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3925 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1724,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3926 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBSB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1725,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3927 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBSB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1725,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3928 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1726,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3929 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1726,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3930 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBUSB,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1727,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3931 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBUSB,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1727,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3932 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBUSW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3933 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBUSW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1728,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3934 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPSUBW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1729,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3935 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPSUBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1729,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3936 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPTERNLOGD,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1730,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3937 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VPTERNLOGQ,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1731,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3938 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
+ {
+ .Instruction = ND_INS_VPTEST,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1732,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:3939 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTMB,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1733,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3940 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTMD,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1734,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3941 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTMQ,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1735,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3942 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTMW,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1736,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3943 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTNMB,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1737,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3944 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTNMD,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1738,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3945 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTNMQ,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1739,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3946 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPTESTNMW,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1740,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4nb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3947 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHBW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1741,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3948 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1741,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3949 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3950 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1742,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3951 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHQDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1743,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3952 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHQDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1743,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3953 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHWD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1744,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3954 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKHWD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1744,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3955 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLBW,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1745,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3956 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLBW,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1745,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3957 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1746,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3958 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1746,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3959 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLQDQ,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1747,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3960 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLQDQ,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1747,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3961 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLWD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512BW,
+ .Mnemonic = 1748,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E4NFnb,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512BW,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3962 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPUNPCKLWD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1748,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3963 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
+ {
+ .Instruction = ND_INS_VPXOR,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1749,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3964 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPXORD,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1750,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3965 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VPXORQ,
+ .Category = ND_CAT_LOGICAL,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1751,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3966 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VRANGEPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1752,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3967 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VRANGEPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1753,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3968 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VRANGESD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1754,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3969 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VRANGESS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1755,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3970 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRCP14PD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1756,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3971 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRCP14PS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1757,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3972 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRCP14SD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1758,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3973 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRCP14SS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1759,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3974 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRCP28PD,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1760,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:3975 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRCP28PS,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1761,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:3976 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRCP28SD,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1762,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3977 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRCP28SS,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1763,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:3978 Instruction:"VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRCPPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1764,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3979 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRCPPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1765,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:3980 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
+ {
+ .Instruction = ND_INS_VRCPPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1766,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3981 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRCPSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1767,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3982 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VRCPSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1768,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3983 Instruction:"VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x56 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VREDUCENEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1769,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3984 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VREDUCEPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1770,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3985 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VREDUCEPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1771,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3986 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VREDUCEPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1772,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3987 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VREDUCESD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1773,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3988 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VREDUCESH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1774,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3989 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VREDUCESS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1775,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3990 Instruction:"VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x08 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VRNDSCALENEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1776,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3991 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VRNDSCALEPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1777,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3992 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VRNDSCALEPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1778,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_UE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3993 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
+ {
+ .Instruction = ND_INS_VRNDSCALEPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1779,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3994 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VRNDSCALESD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1780,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3995 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VRNDSCALESH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1781,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3996 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VRNDSCALESS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1782,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3997 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VROUNDPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1783,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3998 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
+ {
+ .Instruction = ND_INS_VROUNDPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1784,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:3999 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VROUNDSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1785,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4000 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VROUNDSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1786,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4001 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRSQRT14PD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1787,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4002 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRSQRT14PS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1788,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4003 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRSQRT14SD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1789,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4004 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRSQRT14SS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1790,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4005 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRSQRT28PD,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1791,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4006 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRSQRT28PS,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1792,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4007 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRSQRT28SD,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1793,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:4008 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRSQRT28SS,
+ .Category = ND_CAT_KNL,
+ .IsaSet = ND_SET_AVX512ER,
+ .Mnemonic = 1794,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_ZE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512ER,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:4009 Instruction:"VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4E /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRSQRTPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1795,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4010 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM"
+ {
+ .Instruction = ND_INS_VRSQRTPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1796,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4011 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
+ {
+ .Instruction = ND_INS_VRSQRTPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1797,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4012 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VRSQRTSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1798,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E10,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4013 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VRSQRTSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1799,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4014 Instruction:"VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x2C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSCALEFPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1800,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4015 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSCALEFPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1801,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4016 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSCALEFPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1802,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4017 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSCALEFPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1803,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4018 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSCALEFSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1804,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4019 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSCALEFSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1805,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4020 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSCALEFSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1806,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4021 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VSCATTERDPD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1807,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4022 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VSCATTERDPS,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1808,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4023 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF0DPD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1809,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4024 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF0DPS,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1810,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4025 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF0QPD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1811,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4026 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF0QPS,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1812,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4027 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF1DPD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1813,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4028 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF1DPS,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1814,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4029 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF1QPD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1815,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4030 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
+ {
+ .Instruction = ND_INS_VSCATTERPF1QPS,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512PF,
+ .Mnemonic = 1816,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12NP,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512PF,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4031 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VSCATTERQPD,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1817,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4032 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
+ {
+ .Instruction = ND_INS_VSCATTERQPS,
+ .Category = ND_CAT_SCATTER,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1818,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E12,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4033 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VSHA512MSG1,
+ .Category = ND_CAT_SHA512,
+ .IsaSet = ND_SET_SHA512,
+ .Mnemonic = 1819,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_SHA512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4034 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM"
+ {
+ .Instruction = ND_INS_VSHA512MSG2,
+ .Category = ND_CAT_SHA512,
+ .IsaSet = ND_SET_SHA512,
+ .Mnemonic = 1820,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_SHA512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_U, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4035 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM"
+ {
+ .Instruction = ND_INS_VSHA512RNDS2,
+ .Category = ND_CAT_SHA512,
+ .IsaSet = ND_SET_SHA512,
+ .Mnemonic = 1821,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SHA512,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4036 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VSHUFF32X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1822,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4037 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VSHUFF64X2,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1823,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4038 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VSHUFI32X4,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1824,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4039 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VSHUFI64X2,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1825,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4040 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VSHUFPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1826,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4041 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VSHUFPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1826,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4042 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
+ {
+ .Instruction = ND_INS_VSHUFPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1827,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(5, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4043 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VSHUFPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1827,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4044 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSM3MSG1,
+ .Category = ND_CAT_SM3,
+ .IsaSet = ND_SET_SM3,
+ .Mnemonic = 1828,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SM3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4045 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSM3MSG2,
+ .Category = ND_CAT_SM3,
+ .IsaSet = ND_SET_SM3,
+ .Mnemonic = 1829,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SM3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4046 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI"
+ {
+ .Instruction = ND_INS_VSM3RNDS2,
+ .Category = ND_CAT_SM3,
+ .IsaSet = ND_SET_SM3,
+ .Mnemonic = 1830,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SM3,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4047 Instruction:"VSM4KEY4 Vfv,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0xDA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSM4KEY4,
+ .Category = ND_CAT_SM4,
+ .IsaSet = ND_SET_SM4,
+ .Mnemonic = 1831,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SM4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4048 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSM4KEY4,
+ .Category = ND_CAT_SM4,
+ .IsaSet = ND_SET_SM4,
+ .Mnemonic = 1831,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SM4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4049 Instruction:"VSM4RNDS4 Vfv,Hfv,Wfv" Encoding:"evex m:2 p:3 l:x w:0 0xDA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSM4RNDS4,
+ .Category = ND_CAT_SM4,
+ .IsaSet = ND_SET_SM4,
+ .Mnemonic = 1832,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FVM,
+ .ExcType = ND_EXT_E6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SM4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4050 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSM4RNDS4,
+ .Category = ND_CAT_SM4,
+ .IsaSet = ND_SET_SM4,
+ .Mnemonic = 1832,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_6,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SM4,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4051 Instruction:"VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x51 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VSQRTNEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1833,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4052 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VSQRTPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1834,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4053 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
+ {
+ .Instruction = ND_INS_VSQRTPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1834,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4054 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VSQRTPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1835,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4055 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
+ {
+ .Instruction = ND_INS_VSQRTPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1836,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4056 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
+ {
+ .Instruction = ND_INS_VSQRTPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1836,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4057 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSQRTSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1837,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4058 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSQRTSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1837,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4059 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSQRTSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1838,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4060 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSQRTSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1839,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4061 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSQRTSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1839,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4062 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
+ {
+ .Instruction = ND_INS_VSTMXCSR,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1840,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_5,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4063 Instruction:"VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSUBNEPBF16,
+ .Category = ND_CAT_AVX10BF16,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1841,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4064 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSUBPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1842,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4065 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSUBPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1842,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4066 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSUBPH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1843,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0),
+ },
+ },
+
+ // Pos:4067 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSUBPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1844,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4068 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSUBPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1844,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4069 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSUBSD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1845,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4070 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSUBSD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1845,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4071 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSUBSH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1846,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ },
+ },
+
+ // Pos:4072 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VSUBSS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0),
+ },
+ },
+
+ // Pos:4073 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
+ {
+ .Instruction = ND_INS_VSUBSS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1847,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_2,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_OE|ND_SIMD_EXC_UE|ND_SIMD_EXC_PE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4074 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
+ {
+ .Instruction = ND_INS_VTESTPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1848,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4075 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
+ {
+ .Instruction = ND_INS_VTESTPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1849,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4076 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMISD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1850,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4077 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMISD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1850,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4078 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMISH,
+ .Category = ND_CAT_AVX512FP16,
+ .IsaSet = ND_SET_AVX512FP16,
+ .Mnemonic = 1851,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512FP16,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4079 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMISS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1852,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4080 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMISS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1852,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_3,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4081 Instruction:"VUCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMXSD,
+ .Category = ND_CAT_AVX10CMPSFP,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1853,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4082 Instruction:"VUCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMXSH,
+ .Category = ND_CAT_AVX10CMPSFP,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1854,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S16,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4083 Instruction:"VUCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x2E /r"/"RM"
+ {
+ .Instruction = ND_INS_VUCOMXSS,
+ .Category = ND_CAT_AVX10CMPSFP,
+ .IsaSet = ND_SET_AVX102,
+ .Mnemonic = 1855,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_SAE,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = ND_TUPLE_T1S,
+ .ExcType = ND_EXT_E3NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = ND_SIMD_EXC_IE|ND_SIMD_EXC_DE,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4084 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VUNPCKHPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1856,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4085 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VUNPCKHPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1856,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4086 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VUNPCKHPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1857,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4087 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VUNPCKHPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1857,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4088 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VUNPCKLPD,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1858,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4089 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VUNPCKLPD,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1858,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4090 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VUNPCKLPS,
+ .Category = ND_CAT_AVX512,
+ .IsaSet = ND_SET_AVX512F,
+ .Mnemonic = 1859,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4NF,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512F,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4091 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VUNPCKLPS,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1859,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4092 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VXORPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1860,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0),
+ },
+ },
+
+ // Pos:4093 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VXORPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1860,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4094 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
+ {
+ .Instruction = ND_INS_VXORPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX512DQ,
+ .Mnemonic = 1861,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST,
+ .OpsCount = ND_OPS_CNT(4, 0),
+ .TupleType = ND_TUPLE_FV,
+ .ExcType = ND_EXT_E4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX512DQ,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0),
+ OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0),
+ },
+ },
+
+ // Pos:4095 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
+ {
+ .Instruction = ND_INS_VXORPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1861,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4096 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
+ {
+ .Instruction = ND_INS_VZEROALL,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1862,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4097 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
+ {
+ .Instruction = ND_INS_VZEROUPPER,
+ .Category = ND_CAT_AVX,
+ .IsaSet = ND_SET_AVX,
+ .Mnemonic = 1863,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_8,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOV,
+ .CpuidFlag = ND_CFF_AVX,
+ .Operands =
+ {
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4098 Instruction:"WAIT" Encoding:"0x9B"/""
+ {
+ .Instruction = ND_INS_WAIT,
+ .Category = ND_CAT_X87_ALU,
+ .IsaSet = ND_SET_X87,
+ .Mnemonic = 1864,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0xff,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:4099 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
+ {
+ .Instruction = ND_INS_WBINVD,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 1865,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:4100 Instruction:"WBNOINVD" Encoding:"repz 0x0F 0x09"/""
+ {
+ .Instruction = ND_INS_WBNOINVD,
+ .Category = ND_CAT_WBNOINVD,
+ .IsaSet = ND_SET_WBNOINVD,
+ .Mnemonic = 1866,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = ND_CFF_WBNOINVD,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:4101 Instruction:"WRFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /2:reg"/"M"
+ {
+ .Instruction = ND_INS_WRFSBASE,
+ .Category = ND_CAT_RDWRFSGS,
+ .IsaSet = ND_SET_RDWRFSGS,
+ .Mnemonic = 1867,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_RDWRFSGS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_FSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4102 Instruction:"WRGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /3:reg"/"M"
+ {
+ .Instruction = ND_INS_WRGSBASE,
+ .Category = ND_CAT_RDWRFSGS,
+ .IsaSet = ND_SET_RDWRFSGS,
+ .Mnemonic = 1868,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_RDWRFSGS,
+ .Operands =
+ {
+ OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4103 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
+ {
+ .Instruction = ND_INS_WRMSR,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_PENTIUMREAL,
+ .Mnemonic = 1869,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2,
+ .CpuidFlag = ND_CFF_MSR,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4104 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/""
+ {
+ .Instruction = ND_INS_WRMSRLIST,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MSRLIST,
+ .Mnemonic = 1870,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 3),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MSRLIST,
+ .Operands =
+ {
+ OP(ND_OPT_SMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_DMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4105 Instruction:"WRMSRNS Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF6 /0:reg id"/"IM"
+ {
+ .Instruction = ND_INS_WRMSRNS,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MSR_IMM,
+ .Mnemonic = 1871,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_VEX,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MSR_IMM,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4106 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/""
+ {
+ .Instruction = ND_INS_WRMSRNS,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_WRMSRNS,
+ .Mnemonic = 1871,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_WRMSRNS,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4107 Instruction:"WRMSRNS Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF6 /0:reg id"/"IM"
+ {
+ .Instruction = ND_INS_WRMSRNS,
+ .Category = ND_CAT_SYSTEM,
+ .IsaSet = ND_SET_MSR_IMM,
+ .Mnemonic = 1871,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64,
+ .CpuidFlag = ND_CFF_MSR_IMM,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4108 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
+ {
+ .Instruction = ND_INS_WRPKRU,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_PKU,
+ .Mnemonic = 1872,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_PKU,
+ .Operands =
+ {
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4109 Instruction:"WRSSD My,Gy" Encoding:"evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1873,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_WRSS,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4110 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 1873,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4111 Instruction:"WRSSQ My,Gy" Encoding:"evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1874,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_WRSS,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4112 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 1874,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4113 Instruction:"WRUSSD My,Gy" Encoding:"evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRUSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1875,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_WRUSS,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4114 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRUSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 1875,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4115 Instruction:"WRUSSQ My,Gy" Encoding:"evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRUSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1876,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_WRUSS,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4116 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+ {
+ .Instruction = ND_INS_WRUSS,
+ .Category = ND_CAT_CET,
+ .IsaSet = ND_SET_CET_SS,
+ .Mnemonic = 1876,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_CET_SS,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4117 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
+ {
+ .Instruction = ND_INS_XABORT,
+ .Category = ND_CAT_UNCOND_BR,
+ .IsaSet = ND_SET_TSX,
+ .Mnemonic = 1877,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RTM,
+ .Operands =
+ {
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ },
+ },
+
+ // Pos:4118 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
+ {
+ .Instruction = ND_INS_XADD,
+ .Category = ND_CAT_SEMAPHORE,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 1878,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4119 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
+ {
+ .Instruction = ND_INS_XADD,
+ .Category = ND_CAT_SEMAPHORE,
+ .IsaSet = ND_SET_I486REAL,
+ .Mnemonic = 1878,
+ .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4120 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
+ {
+ .Instruction = ND_INS_XBEGIN,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_TSX,
+ .Mnemonic = 1879,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RTM,
+ .Operands =
+ {
+ OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ },
+ },
+
+ // Pos:4121 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4122 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4123 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4124 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4125 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4126 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4127 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4128 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4129 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4130 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O"
+ {
+ .Instruction = ND_INS_XCHG,
+ .Category = ND_CAT_DATAXFER,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1880,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ },
+ },
+
+ // Pos:4131 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
+ {
+ .Instruction = ND_INS_XEND,
+ .Category = ND_CAT_COND_BR,
+ .IsaSet = ND_SET_TSX,
+ .Mnemonic = 1881,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RTM,
+ .Operands =
+ {
+ OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CW, 0, 0),
+ },
+ },
+
+ // Pos:4132 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
+ {
+ .Instruction = ND_INS_XGETBV,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1882,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4133 Instruction:"XLATB" Encoding:"0xD7"/""
+ {
+ .Instruction = ND_INS_XLATB,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1883,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 2),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ OP(ND_OPT_pBXAL, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4134 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4135 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4136 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4137 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4138 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4139 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4140 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4141 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4142 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4143 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4144 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4145 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4146 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4147 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4148 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4149 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4150 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4151 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4152 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4153 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4154 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4155 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4156 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r"/"VMR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4157 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r"/"VMR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4158 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r"/"VMR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4159 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r"/"VRM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4160 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r"/"VRM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4161 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r"/"VRM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4162 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4163 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4164 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4165 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4166 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND,
+ .OpsCount = ND_OPS_CNT(3, 1),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4167 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r"/"VMR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4168 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r"/"VMR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4169 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r"/"VMR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4170 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r"/"VRM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4171 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r"/"VRM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4172 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r"/"VRM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4173 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4174 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4175 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4176 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4177 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib"/"VMI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_APX_F,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF,
+ .ValidDecorators = ND_DECO_ND|ND_DECO_NF,
+ .OpsCount = ND_OPS_CNT(3, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_APX_EVEX_INT,
+ .FpuFlags = 0,
+ .EvexMode = ND_EVEXM_LEGACY,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_APX_F,
+ .Operands =
+ {
+ OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4178 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4179 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4180 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4181 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4182 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4183 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = 0,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4184 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4185 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4186 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_I64,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4187 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
+ {
+ .Instruction = ND_INS_XOR,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_I86,
+ .Mnemonic = 1884,
+ .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF,
+ .SetFlags = 0|NDR_RFLAG_AF,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = 0,
+ .Operands =
+ {
+ OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0),
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4188 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
+ {
+ .Instruction = ND_INS_XORPD,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE2,
+ .Mnemonic = 1885,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE2,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4189 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
+ {
+ .Instruction = ND_INS_XORPS,
+ .Category = ND_CAT_LOGICAL_FP,
+ .IsaSet = ND_SET_SSE,
+ .Mnemonic = 1886,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(2, 0),
+ .TupleType = 0,
+ .ExcType = ND_EXT_4,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR,
+ .CpuidFlag = ND_CFF_SSE,
+ .Operands =
+ {
+ OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0),
+ OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4190 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
+ {
+ .Instruction = ND_INS_XRESLDTRK,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_TSXLDTRK,
+ .Mnemonic = 1887,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TSXLDTRK,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:4191 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
+ {
+ .Instruction = ND_INS_XRSTOR,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1888,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4192 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
+ {
+ .Instruction = ND_INS_XRSTOR,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1889,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4193 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_XRSTORS,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVES,
+ .Mnemonic = 1890,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVES,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4194 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
+ {
+ .Instruction = ND_INS_XRSTORS,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVES,
+ .Mnemonic = 1891,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVES,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4195 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVE,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1892,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4196 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVE,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1893,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4197 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVEC,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVEC,
+ .Mnemonic = 1894,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVEC,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4198 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVEC,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVEC,
+ .Mnemonic = 1895,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVEC,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4199 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVEOPT,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1896,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4200 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVEOPT,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1897,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4201 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVES,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVES,
+ .Mnemonic = 1898,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVES,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4202 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
+ {
+ .Instruction = ND_INS_XSAVES,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVES,
+ .Mnemonic = 1899,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(1, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVES,
+ .Operands =
+ {
+ OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ },
+ },
+
+ // Pos:4203 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
+ {
+ .Instruction = ND_INS_XSETBV,
+ .Category = ND_CAT_XSAVE,
+ .IsaSet = ND_SET_XSAVE,
+ .Mnemonic = 1900,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 4),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_XSAVE,
+ .Operands =
+ {
+ OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0),
+ OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+ // Pos:4204 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
+ {
+ .Instruction = ND_INS_XSUSLDTRK,
+ .Category = ND_CAT_MISC,
+ .IsaSet = ND_SET_TSXLDTRK,
+ .Mnemonic = 1901,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 0),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0,
+ .SetFlags = 0,
+ .ClearedFlags = 0,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_TSXLDTRK,
+ .Operands =
+ {
+ 0
+ },
+ },
+
+ // Pos:4205 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
+ {
+ .Instruction = ND_INS_XTEST,
+ .Category = ND_CAT_LOGIC,
+ .IsaSet = ND_SET_TSX,
+ .Mnemonic = 1902,
+ .ValidPrefixes = 0,
+ .ValidModes = ND_MOD_ANY,
+ .ValidDecorators = 0,
+ .OpsCount = ND_OPS_CNT(0, 1),
+ .TupleType = 0,
+ .ExcType = 0,
+ .FpuFlags = 0,
+ .EvexMode = 0,
+ .SimdExc = 0,
+ .TestedFlags = 0,
+ .ModifiedFlags = 0|NDR_RFLAG_ZF,
+ .SetFlags = 0,
+ .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+ .Attributes = ND_FLAG_MODRM,
+ .CpuidFlag = ND_CFF_RTM,
+ .Operands =
+ {
+ OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0),
+ },
+ },
+
+
+};
+
+#endif
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_mnemonics.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_mnemonics.h
new file mode 100644
index 00000000000000..43546da69772c4
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_mnemonics.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_MNEMONICS_H
+#define BDX86_MNEMONICS_H
+
+#ifndef BDDISASM_NO_MNEMONIC
+
+const char *gMnemonics[1903] =
+{
+ "AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD",
+ "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX",
+ "AESDEC", "AESDEC128KL", "AESDEC256KL", "AESDECLAST", "AESDECWIDE128KL",
+ "AESDECWIDE256KL", "AESENC", "AESENC128KL", "AESENC256KL", "AESENCLAST",
+ "AESENCWIDE128KL", "AESENCWIDE256KL", "AESIMC", "AESKEYGENASSIST",
+ "AND", "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", "AOR", "ARPL",
+ "AXOR", "BEXTR", "BLCFILL", "BLCI", "BLCIC", "BLCMSK", "BLCS",
+ "BLENDPD", "BLENDPS", "BLENDVPD", "BLENDVPS", "BLSFILL", "BLSI",
+ "BLSIC", "BLSMSK", "BLSR", "BNDCL", "BNDCN", "BNDCU", "BNDLDX",
+ "BNDMK", "BNDMOV", "BNDSTX", "BOUND", "BSF", "BSR", "BSWAP",
+ "BT", "BTC", "BTR", "BTS", "BZHI", "CALL", "CALLF", "CBW", "CCMPBE",
+ "CCMPC", "CCMPF", "CCMPL", "CCMPLE", "CCMPNBE", "CCMPNC", "CCMPNL",
+ "CCMPNLE", "CCMPNO", "CCMPNS", "CCMPNZ", "CCMPO", "CCMPS", "CCMPT",
+ "CCMPZ", "CDQ", "CDQE", "CFCMOVBE", "CFCMOVC", "CFCMOVL", "CFCMOVLE",
+ "CFCMOVNBE", "CFCMOVNC", "CFCMOVNL", "CFCMOVNLE", "CFCMOVNO",
+ "CFCMOVNP", "CFCMOVNS", "CFCMOVNZ", "CFCMOVO", "CFCMOVP", "CFCMOVS",
+ "CFCMOVZ", "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", "CLEVICT1",
+ "CLFLUSH", "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLUI",
+ "CLWB", "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE",
+ "CMOVNBE", "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP",
+ "CMOVNS", "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP",
+ "CMPBEXADD", "CMPCXADD", "CMPLEXADD", "CMPLXADD", "CMPNBEXADD",
+ "CMPNCXADD", "CMPNLEXADD", "CMPNLXADD", "CMPNOXADD", "CMPNPXADD",
+ "CMPNSXADD", "CMPNZXADD", "CMPOXADD", "CMPPD", "CMPPS", "CMPPXADD",
+ "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPSXADD", "CMPXCHG",
+ "CMPXCHG16B", "CMPXCHG8B", "CMPZXADD", "COMISD", "COMISS", "CPUID",
+ "CQO", "CRC32", "CTESTBE", "CTESTC", "CTESTF", "CTESTL", "CTESTLE",
+ "CTESTNBE", "CTESTNC", "CTESTNL", "CTESTNLE", "CTESTNO", "CTESTNS",
+ "CTESTNZ", "CTESTO", "CTESTS", "CTESTT", "CTESTZ", "CVTDQ2PD",
+ "CVTDQ2PS", "CVTPD2DQ", "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS",
+ "CVTPS2DQ", "CVTPS2PD", "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD",
+ "CVTSI2SS", "CVTSS2SD", "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI",
+ "CVTTPS2DQ", "CVTTPS2PI", "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE",
+ "DAA", "DAS", "DEC", "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD",
+ "DIVSS", "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128",
+ "ENCODEKEY256", "ENDBR32", "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER",
+ "ERETS", "ERETU", "EXTRACTPS", "EXTRQ", "F2XM1", "FABS", "FADD",
+ "FADDP", "FBLD", "FBSTP", "FCHS", "FCMOVB", "FCMOVBE", "FCMOVE",
+ "FCMOVNB", "FCMOVNBE", "FCMOVNE", "FCMOVNU", "FCMOVU", "FCOM",
+ "FCOMI", "FCOMIP", "FCOMP", "FCOMPP", "FCOS", "FDECSTP", "FDIV",
+ "FDIVP", "FDIVR", "FDIVRP", "FEMMS", "FFREE", "FFREEP", "FIADD",
+ "FICOM", "FICOMP", "FIDIV", "FIDIVR", "FILD", "FIMUL", "FINCSTP",
+ "FIST", "FISTP", "FISTTP", "FISUB", "FISUBR", "FLD", "FLD1",
+ "FLDCW", "FLDENV", "FLDL2E", "FLDL2T", "FLDLG2", "FLDLN2", "FLDPI",
+ "FLDZ", "FMUL", "FMULP", "FNCLEX", "FNDISI", "FNINIT", "FNOP",
+ "FNSAVE", "FNSTCW", "FNSTENV", "FNSTSW", "FPATAN", "FPREM", "FPREM1",
+ "FPTAN", "FRINEAR", "FRNDINT", "FRSTOR", "FSCALE", "FSIN", "FSINCOS",
+ "FSQRT", "FST", "FSTDW", "FSTP", "FSTPNCE", "FSTSG", "FSUB",
+ "FSUBP", "FSUBR", "FSUBRP", "FTST", "FUCOM", "FUCOMI", "FUCOMIP",
+ "FUCOMP", "FUCOMPP", "FXAM", "FXCH", "FXRSTOR", "FXRSTOR64",
+ "FXSAVE", "FXSAVE64", "FXTRACT", "FYL2X", "FYL2XP1", "GETSEC",
+ "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", "GF2P8MULB", "HADDPD", "HADDPS",
+ "HLT", "HRESET", "HSUBPD", "HSUBPS", "IDIV", "IMUL", "IN", "INC",
+ "INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", "INSERTQ",
+ "INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", "INVLPG",
+ "INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", "IRETQ",
+ "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPABS",
+ "JMPE", "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS",
+ "JNZ", "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ",
+ "KADDW", "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW",
+ "KANDQ", "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD",
+ "KMOVQ", "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB",
+ "KORD", "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW",
+ "KORW", "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB",
+ "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ",
+ "KTESTW", "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD",
+ "KXNORQ", "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF",
+ "LAR", "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE",
+ "LES", "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LKGS", "LLDT",
+ "LLWPCB", "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", "LODSW",
+ "LOOP", "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", "LWPVAL",
+ "LZCNT", "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD",
+ "MAXSS", "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", "MINSS",
+ "MONITOR", "MONITORX", "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD",
+ "MOVDDUP", "MOVDIR64B", "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU",
+ "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS",
+ "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD",
+ "MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ",
+ "MOVRS", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS",
+ "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW",
+ "MUL", "MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX",
+ "NEG", "NOP", "NOT", "OR", "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD",
+ "OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW",
+ "PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB",
+ "PADDUSW", "PADDW", "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB",
+ "PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PBNDKB", "PCLMULQDQ",
+ "PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM",
+ "PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM",
+ "PCONFIG", "PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW",
+ "PF2ID", "PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT",
+ "PFMAX", "PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1",
+ "PFRCPIT2", "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB",
+ "PFSUBR", "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD",
+ "PHSUBSW", "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ",
+ "PINSRW", "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW",
+ "PMAXUB", "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB",
+ "PMINUD", "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW",
+ "PMOVSXDQ", "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW",
+ "PMOVZXDQ", "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW",
+ "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POP2",
+ "POP2P", "POPA", "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW",
+ "POPP", "POR", "PREFETCH", "PREFETCHE", "PREFETCHIT0", "PREFETCHIT1",
+ "PREFETCHM", "PREFETCHNTA", "PREFETCHRST2", "PREFETCHT0", "PREFETCHT1",
+ "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB",
+ "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND",
+ "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH", "PSRAD",
+ "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB", "PSUBD",
+ "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD",
+ "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD",
+ "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH",
+ "PUSH2", "PUSH2P", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW",
+ "PUSHP", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR",
+ "RDFSBASE", "RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU",
+ "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSSPD", "RDSSPQ", "RDTSC",
+ "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPQUERY", "RMPREAD",
+ "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD",
+ "ROUNDSS", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "SAHF", "SAL",
+ "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD",
+ "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI",
+ "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC",
+ "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO",
+ "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1",
+ "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2",
+ "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX",
+ "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMSW",
+ "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", "STC",
+ "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", "STOSW",
+ "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS", "SUBSD",
+ "SUBSS", "SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET",
+ "T1MSKC", "T2RPNTLVWZ0", "T2RPNTLVWZ0RS", "T2RPNTLVWZ0RST1",
+ "T2RPNTLVWZ0T1", "T2RPNTLVWZ1", "T2RPNTLVWZ1RS", "T2RPNTLVWZ1RST1",
+ "T2RPNTLVWZ1T1", "TCMMIMFP16PS", "TCMMRLFP16PS", "TCONJTCMMIMFP16PS",
+ "TCONJTFP16", "TCVTROWD2PS", "TCVTROWPS2PBF16H", "TCVTROWPS2PBF16L",
+ "TCVTROWPS2PHH", "TCVTROWPS2PHL", "TDCALL", "TDPBF16PS", "TDPBF8PS",
+ "TDPBHF8PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TDPFP16PS",
+ "TDPHBF8PS", "TDPHF8PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDRS",
+ "TILELOADDRST1", "TILELOADDT1", "TILEMOVROW", "TILERELEASE",
+ "TILESTORED", "TILEZERO", "TLBSYNC", "TMMULTF32PS", "TPAUSE",
+ "TTCMMIMFP16PS", "TTCMMRLFP16PS", "TTDPBF16PS", "TTDPFP16PS",
+ "TTMMULTF32PS", "TTRANSPOSED", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS",
+ "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD",
+ "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR", "UWRMSR", "V4FMADDPS",
+ "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDNEPBF16", "VADDPD",
+ "VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD",
+ "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST",
+ "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD",
+ "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS",
+ "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD",
+ "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4",
+ "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128",
+ "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2",
+ "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPBF16",
+ "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD",
+ "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCOMSBF16",
+ "VCOMXSD", "VCOMXSH", "VCOMXSS", "VCVT2PS2PHX", "VCVTBIASPH2BF8",
+ "VCVTBIASPH2BF8S", "VCVTBIASPH2HF8", "VCVTBIASPH2HF8S", "VCVTDQ2PD",
+ "VCVTDQ2PH", "VCVTDQ2PS", "VCVTHF82PH", "VCVTNE2PH2BF8", "VCVTNE2PH2BF8S",
+ "VCVTNE2PH2HF8", "VCVTNE2PH2HF8S", "VCVTNE2PS2BF16", "VCVTNEBF162IBS",
+ "VCVTNEBF162IUBS", "VCVTNEEBF162PS", "VCVTNEEPH2PS", "VCVTNEOBF162PS",
+ "VCVTNEOPH2PS", "VCVTNEPH2BF8", "VCVTNEPH2BF8S", "VCVTNEPH2HF8",
+ "VCVTNEPH2HF8S", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS",
+ "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2IBS",
+ "VCVTPH2IUBS", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX", "VCVTPH2QQ",
+ "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W", "VCVTPS2DQ",
+ "VCVTPS2IBS", "VCVTPS2IUBS", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX",
+ "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH",
+ "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI",
+ "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD",
+ "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI",
+ "VCVTSS2USI", "VCVTTNEBF162IBS", "VCVTTNEBF162IUBS", "VCVTTPD2DQ",
+ "VCVTTPD2DQS", "VCVTTPD2QQ", "VCVTTPD2QQS", "VCVTTPD2UDQ", "VCVTTPD2UDQS",
+ "VCVTTPD2UQQ", "VCVTTPD2UQQS", "VCVTTPH2DQ", "VCVTTPH2IBS", "VCVTTPH2IUBS",
+ "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W",
+ "VCVTTPS2DQ", "VCVTTPS2DQS", "VCVTTPS2IBS", "VCVTTPS2IUBS", "VCVTTPS2QQ",
+ "VCVTTPS2QQS", "VCVTTPS2UDQ", "VCVTTPS2UDQS", "VCVTTPS2UQQ",
+ "VCVTTPS2UQQS", "VCVTTSD2SI", "VCVTTSD2SIS", "VCVTTSD2USI", "VCVTTSD2USIS",
+ "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2SIS", "VCVTTSS2USI",
+ "VCVTTSS2USIS", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD",
+ "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS",
+ "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVNEPBF16", "VDIVPD",
+ "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS",
+ "VDPPD", "VDPPHPS", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS",
+ "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
+ "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4",
+ "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS",
+ "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", "VFCMULCSH", "VFIXUPIMMPD",
+ "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132NEPBF16",
+ "VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH",
+ "VFMADD132SS", "VFMADD213NEPBF16", "VFMADD213PD", "VFMADD213PH",
+ "VFMADD213PS", "VFMADD213SD", "VFMADD213SH", "VFMADD213SS", "VFMADD231NEPBF16",
+ "VFMADD231PD", "VFMADD231PH", "VFMADD231PS", "VFMADD231SD", "VFMADD231SH",
+ "VFMADD231SS", "VFMADDCPH", "VFMADDCSH", "VFMADDPD", "VFMADDPS",
+ "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", "VFMADDSUB132PH", "VFMADDSUB132PS",
+ "VFMADDSUB213PD", "VFMADDSUB213PH", "VFMADDSUB213PS", "VFMADDSUB231PD",
+ "VFMADDSUB231PH", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS",
+ "VFMSUB132NEPBF16", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS",
+ "VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213NEPBF16",
+ "VFMSUB213PD", "VFMSUB213PH", "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH",
+ "VFMSUB213SS", "VFMSUB231NEPBF16", "VFMSUB231PD", "VFMSUB231PH",
+ "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", "VFMSUBADD132PD",
+ "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", "VFMSUBADD213PH",
+ "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", "VFMSUBADD231PS",
+ "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD",
+ "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132NEPBF16", "VFNMADD132PD",
+ "VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH",
+ "VFNMADD132SS", "VFNMADD213NEPBF16", "VFNMADD213PD", "VFNMADD213PH",
+ "VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS",
+ "VFNMADD231NEPBF16", "VFNMADD231PD", "VFNMADD231PH", "VFNMADD231PS",
+ "VFNMADD231SD", "VFNMADD231SH", "VFNMADD231SS", "VFNMADDPD",
+ "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132NEPBF16", "VFNMSUB132PD",
+ "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SH",
+ "VFNMSUB132SS", "VFNMSUB213NEPBF16", "VFNMSUB213PD", "VFNMSUB213PH",
+ "VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS",
+ "VFNMSUB231NEPBF16", "VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS",
+ "VFNMSUB231SD", "VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD",
+ "VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", "VFPCLASSPBF16", "VFPCLASSPD",
+ "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", "VFPCLASSSH", "VFPCLASSSS",
+ "VFRCZPD", "VFRCZPS", "VFRCZSD", "VFRCZSS", "VGATHERDPD", "VGATHERDPS",
+ "VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD", "VGATHERPF0QPS",
+ "VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD", "VGATHERPF1QPS",
+ "VGATHERQPD", "VGATHERQPS", "VGETEXPPBF16", "VGETEXPPD", "VGETEXPPH",
+ "VGETEXPPS", "VGETEXPSD", "VGETEXPSH", "VGETEXPSS", "VGETMANTPBF16",
+ "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", "VGETMANTSH",
+ "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", "VGF2P8MULB",
+ "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", "VINSERTF32X4",
+ "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", "VINSERTI128",
+ "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", "VINSERTI64X4",
+ "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", "VMASKMOVPD",
+ "VMASKMOVPS", "VMAXPBF16", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD",
+ "VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT",
+ "VMINMAXNEPBF16", "VMINMAXPD", "VMINMAXPH", "VMINMAXPS", "VMINMAXSD",
+ "VMINMAXSH", "VMINMAXSS", "VMINPBF16", "VMINPD", "VMINPH", "VMINPS",
+ "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", "VMLOAD", "VMMCALL",
+ "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", "VMOVDQA", "VMOVDQA32",
+ "VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64",
+ "VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS", "VMOVLPD",
+ "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA",
+ "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVRSB", "VMOVRSD", "VMOVRSQ",
+ "VMOVRSW", "VMOVSD", "VMOVSH", "VMOVSHDUP", "VMOVSLDUP", "VMOVSS",
+ "VMOVUPD", "VMOVUPS", "VMOVW", "VMPSADBW", "VMPTRLD", "VMPTRST",
+ "VMREAD", "VMRESUME", "VMRUN", "VMSAVE", "VMULNEPBF16", "VMULPD",
+ "VMULPH", "VMULPS", "VMULSD", "VMULSH", "VMULSS", "VMWRITE",
+ "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD", "VP2INTERSECTQ",
+ "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD", "VPABSQ", "VPABSW",
+ "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB", "VPADDB",
+ "VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB", "VPADDUSW",
+ "VPADDW", "VPALIGNR", "VPAND", "VPANDD", "VPANDN", "VPANDND",
+ "VPANDNQ", "VPANDQ", "VPAVGB", "VPAVGW", "VPBLENDD", "VPBLENDMB",
+ "VPBLENDMD", "VPBLENDMQ", "VPBLENDMW", "VPBLENDVB", "VPBLENDW",
+ "VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTMB2Q", "VPBROADCASTMW2D",
+ "VPBROADCASTQ", "VPBROADCASTW", "VPCLMULQDQ", "VPCMOV", "VPCMPB",
+ "VPCMPD", "VPCMPEQB", "VPCMPEQD", "VPCMPEQQ", "VPCMPEQW", "VPCMPESTRI",
+ "VPCMPESTRM", "VPCMPGTB", "VPCMPGTD", "VPCMPGTQ", "VPCMPGTW",
+ "VPCMPISTRI", "VPCMPISTRM", "VPCMPQ", "VPCMPUB", "VPCMPUD", "VPCMPUQ",
+ "VPCMPUW", "VPCMPW", "VPCOMB", "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD",
+ "VPCOMPRESSQ", "VPCOMPRESSW", "VPCOMQ", "VPCOMUB", "VPCOMUD",
+ "VPCOMUQ", "VPCOMUW", "VPCOMW", "VPCONFLICTD", "VPCONFLICTQ",
+ "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD", "VPDPBSUDS", "VPDPBUSD",
+ "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS", "VPDPWSSD", "VPDPWSSDS",
+ "VPDPWSUD", "VPDPWSUDS", "VPDPWUSD", "VPDPWUSDS", "VPDPWUUD",
+ "VPDPWUUDS", "VPERM2F128", "VPERM2I128", "VPERMB", "VPERMD",
+ "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
+ "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS",
+ "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD",
+ "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD",
+ "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW",
+ "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", "VPGATHERQQ", "VPHADDBD",
+ "VPHADDBQ", "VPHADDBW", "VPHADDD", "VPHADDDQ", "VPHADDSW", "VPHADDUBD",
+ "VPHADDUBQ", "VPHADDUBW", "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ",
+ "VPHADDW", "VPHADDWD", "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW",
+ "VPHSUBD", "VPHSUBDQ", "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB",
+ "VPINSRD", "VPINSRQ", "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD",
+ "VPMACSDQH", "VPMACSDQL", "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL",
+ "VPMACSSWD", "VPMACSSWW", "VPMACSWD", "VPMACSWW", "VPMADCSSWD",
+ "VPMADCSWD", "VPMADD52HUQ", "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD",
+ "VPMASKMOVD", "VPMASKMOVQ", "VPMAXSB", "VPMAXSD", "VPMAXSQ",
+ "VPMAXSW", "VPMAXUB", "VPMAXUD", "VPMAXUQ", "VPMAXUW", "VPMINSB",
+ "VPMINSD", "VPMINSQ", "VPMINSW", "VPMINUB", "VPMINUD", "VPMINUQ",
+ "VPMINUW", "VPMOVB2M", "VPMOVD2M", "VPMOVDB", "VPMOVDW", "VPMOVM2B",
+ "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", "VPMOVMSKB", "VPMOVQ2M",
+ "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", "VPMOVSDW", "VPMOVSQB",
+ "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", "VPMOVSXBQ",
+ "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", "VPMOVUSDB",
+ "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB",
+ "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXBW",
+ "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", "VPMULHRSW",
+ "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", "VPMULTISHIFTQB",
+ "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", "VPOPCNTW", "VPOR",
+ "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", "VPROLVD", "VPROLVQ",
+ "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD",
+ "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ",
+ "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW",
+ "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ",
+ "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", "VPSHRDD", "VPSHRDQ",
+ "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB",
+ "VPSHUFD", "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW",
+ "VPSLLD", "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW",
+ "VPSLLW", "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW",
+ "VPSRAW", "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ",
+ "VPSRLVW", "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB",
+ "VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ",
+ "VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB",
+ "VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ",
+ "VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ",
+ "VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS",
+ "VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS",
+ "VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPBF16",
+ "VRCPPH", "VRCPPS", "VRCPSH", "VRCPSS", "VREDUCENEPBF16", "VREDUCEPD",
+ "VREDUCEPH", "VREDUCEPS", "VREDUCESD", "VREDUCESH", "VREDUCESS",
+ "VRNDSCALENEPBF16", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS",
+ "VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS",
+ "VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD",
+ "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS",
+ "VRSQRTPBF16", "VRSQRTPH", "VRSQRTPS", "VRSQRTSH", "VRSQRTSS",
+ "VSCALEFPBF16", "VSCALEFPD", "VSCALEFPH", "VSCALEFPS", "VSCALEFSD",
+ "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD",
+ "VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD",
+ "VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD",
+ "VSCATTERQPS", "VSHA512MSG1", "VSHA512MSG2", "VSHA512RNDS2",
+ "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD",
+ "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2", "VSM4KEY4", "VSM4RNDS4",
+ "VSQRTNEPBF16", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", "VSQRTSH",
+ "VSQRTSS", "VSTMXCSR", "VSUBNEPBF16", "VSUBPD", "VSUBPH", "VSUBPS",
+ "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD",
+ "VUCOMISH", "VUCOMISS", "VUCOMXSD", "VUCOMXSH", "VUCOMXSS", "VUNPCKHPD",
+ "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL",
+ "VZEROUPPER", "WAIT", "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE",
+ "WRMSR", "WRMSRLIST", "WRMSRNS", "WRPKRU", "WRSSD", "WRSSQ",
+ "WRUSSD", "WRUSSQ", "XABORT", "XADD", "XBEGIN", "XCHG", "XEND",
+ "XGETBV", "XLATB", "XOR", "XORPD", "XORPS", "XRESLDTRK", "XRSTOR",
+ "XRSTOR64", "XRSTORS", "XRSTORS64", "XSAVE", "XSAVE64", "XSAVEC",
+ "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64", "XSETBV",
+ "XSUSLDTRK", "XTEST",
+};
+
+#endif // !BDDISASM_NO_MNEMONIC
+
+
+#endif
+
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_prefixes.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_prefixes.h
new file mode 100644
index 00000000000000..c5e01c9a33f3ac
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_prefixes.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDX86_PREFIXES_H
+#define BDX86_PREFIXES_H
+
+#define ND_PREF_CODE_NONE 0
+#define ND_PREF_CODE_STANDARD 1
+#define ND_PREF_CODE_EX 2
+#define ND_PREF_CODE_REX 3
+
+static const ND_UINT8 gPrefixesMap[256] =
+{
+// 0 1 2 3 4 5 6 7 8 9 A B C D E F
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 1
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, // 2
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, // 3
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 4
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 5
+ 0, 0, 2, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, // 6
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 7
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, // 8
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 9
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // A
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // B
+ 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // C
+ 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // D
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // E
+ 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // F
+};
+
+#endif // BDX86_PREFIXES_H
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_evex.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_evex.h
new file mode 100644
index 00000000000000..aed26d135cbe51
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_evex.h
@@ -0,0 +1,39825 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_TABLE_EVEX_H
+#define BDX86_TABLE_EVEX_H
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2675] // URDMSR Rq,Id
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2679] // UWRMSR Id,Rq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_07_opcode_f8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2078] // RDMSR Rq,Id
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4105] // WRMSRNS Id,Rq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_07_opcode_f6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_02_modrmreg,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp_03_modrmreg,
+ }
+};
+
+const ND_TABLE_OPCODE gEvexMap_mmmmm_07_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)&gEvexMap_mmmmm_07_opcode_f6_pp,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2948] // VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3076] // VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2947] // VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3075] // VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bf_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3148] // VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bf_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bf_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bf_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bf_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_be_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3143] // VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_be_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3140] // VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_be_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bd_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3107] // VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bd_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bd_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bd_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bc_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3102] // VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bc_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3099] // VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bb_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3045] // VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bb_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bb_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bb_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ba_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3040] // VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ba_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3037] // VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ba_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b9_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2983] // VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b9_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b9_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b9_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b8_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2978] // VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b8_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2975] // VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b7_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3060] // VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b7_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b7_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b7_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b6_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3008] // VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b6_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b6_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_af_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3137] // VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_af_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_af_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_af_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_af_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ae_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3132] // VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ae_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3129] // VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ae_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ad_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3096] // VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ad_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ad_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ad_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ad_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ac_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3091] // VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ac_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3088] // VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ac_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ab_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3034] // VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ab_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ab_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ab_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ab_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_aa_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3029] // VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_aa_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3026] // VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_aa_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a9_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2972] // VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a9_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a9_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a9_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a8_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2967] // VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a8_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2964] // VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a7_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3055] // VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a7_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a7_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a7_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a6_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3003] // VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a6_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a6_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3126] // VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3121] // VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9e_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3118] // VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3085] // VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3080] // VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9c_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3077] // VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3023] // VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3018] // VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9a_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3015] // VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_99_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2961] // VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_99_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_99_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_99_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_99_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_98_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2956] // VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_98_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2953] // VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_98_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_97_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3050] // VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_97_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_97_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_97_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_97_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_96_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2998] // VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_96_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_96_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_96_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_96_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2946] // VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2987] // VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_57_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2945] // VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2986] // VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_56_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4012] // VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4010] // VRSQRTPH Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4e_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4009] // VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3981] // VRCPSH Vdq{K}{z},aKq,Hdq,Wsh
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3979] // VRCPPH Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4c_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3978] // VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_43_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3191] // VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_43_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_43_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_43_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_43_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_42_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3188] // VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_42_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_42_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3186] // VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_42_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_42_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4019] // VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_2d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4016] // VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2c_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4014] // VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2810] // VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2841] // VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_13_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gEvexMap_mmmmm_06_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp,
+ /* 2d */ (const void *)&gEvexMap_mmmmm_06_opcode_2d_pp,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp,
+ /* 43 */ (const void *)&gEvexMap_mmmmm_06_opcode_43_pp,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp,
+ /* 4d */ (const void *)&gEvexMap_mmmmm_06_opcode_4d_pp,
+ /* 4e */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp,
+ /* 4f */ (const void *)&gEvexMap_mmmmm_06_opcode_4f_pp,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp,
+ /* 57 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)&gEvexMap_mmmmm_06_opcode_96_pp,
+ /* 97 */ (const void *)&gEvexMap_mmmmm_06_opcode_97_pp,
+ /* 98 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp,
+ /* 99 */ (const void *)&gEvexMap_mmmmm_06_opcode_99_pp,
+ /* 9a */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp,
+ /* 9b */ (const void *)&gEvexMap_mmmmm_06_opcode_9b_pp,
+ /* 9c */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp,
+ /* 9d */ (const void *)&gEvexMap_mmmmm_06_opcode_9d_pp,
+ /* 9e */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp,
+ /* 9f */ (const void *)&gEvexMap_mmmmm_06_opcode_9f_pp,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)&gEvexMap_mmmmm_06_opcode_a6_pp,
+ /* a7 */ (const void *)&gEvexMap_mmmmm_06_opcode_a7_pp,
+ /* a8 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp,
+ /* a9 */ (const void *)&gEvexMap_mmmmm_06_opcode_a9_pp,
+ /* aa */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp,
+ /* ab */ (const void *)&gEvexMap_mmmmm_06_opcode_ab_pp,
+ /* ac */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp,
+ /* ad */ (const void *)&gEvexMap_mmmmm_06_opcode_ad_pp,
+ /* ae */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp,
+ /* af */ (const void *)&gEvexMap_mmmmm_06_opcode_af_pp,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)&gEvexMap_mmmmm_06_opcode_b6_pp,
+ /* b7 */ (const void *)&gEvexMap_mmmmm_06_opcode_b7_pp,
+ /* b8 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp,
+ /* b9 */ (const void *)&gEvexMap_mmmmm_06_opcode_b9_pp,
+ /* ba */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp,
+ /* bb */ (const void *)&gEvexMap_mmmmm_06_opcode_bb_pp,
+ /* bc */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp,
+ /* bd */ (const void *)&gEvexMap_mmmmm_06_opcode_bd_pp,
+ /* be */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp,
+ /* bf */ (const void *)&gEvexMap_mmmmm_06_opcode_bf_pp,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp,
+ /* d7 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3383] // VMOVW Ww,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3382] // VMOVW Rd,Vdq
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3381] // VMOVW Mw,Vdq
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_02_l,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2907] // VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2908] // VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2815] // VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2814] // VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2873] // VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2872] // VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2905] // VCVTUSI2SH Vdq,Hdq,Ey{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2811] // VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2901] // VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2898] // VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_03_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2869] // VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2842] // VCVTSH2USI Gy,Wsh{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2813] // VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2812] // VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_79_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_02_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2891] // VCVTTSH2USI Gy,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_02_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_02_wi_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2871] // VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2870] // VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_78_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_02_wi,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2778] // VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2789] // VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2767] // VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_74_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3345] // VMOVRSW Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3342] // VMOVRSB Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3344] // VMOVRSQ Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3343] // VMOVRSD Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3380] // VMOVW Vdq,Ww
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3379] // VMOVW Vdq,Rd
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3378] // VMOVW Vdq,Mw
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_02_l,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2887] // VCVTTSD2SIS Gy,Wsd{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2894] // VCVTTSS2SIS Gy,Wss{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2861] // VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2880] // VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2859] // VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2876] // VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6d_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2889] // VCVTTSD2USIS Gy,Wsd{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2896] // VCVTTSS2USIS Gy,Wss{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2865] // VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2884] // VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2863] // VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2882] // VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6c_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2783] // VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2819] // VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2805] // VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2856] // VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2878] // VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2868] // VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2782] // VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2818] // VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2804] // VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_69_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2855] // VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2877] // VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2867] // VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_68_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3239] // VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3231] // VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3234] // VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2918] // VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2910] // VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2913] // VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3262] // VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3254] // VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3257] // VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4071] // VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4063] // VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4066] // VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2866] // VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2803] // VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2831] // VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2773] // VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2833] // VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2839] // VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2796] // VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2806] // VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3400] // VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3392] // VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3395] // VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_59_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2694] // VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2686] // VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2689] // VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_58_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4059] // VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4051] // VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4054] // VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_51_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2763] // VCOMXSH Vdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2761] // VCOMSBF16 Vdq,Wsh
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2756] // VCOMISH Vdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4082] // VUCOMXSH Vdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4078] // VUCOMISH Vdq,Wsh{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2d_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2840] // VCVTSH2SI Gy,Wsh{er}
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2d_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2c_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2890] // VCVTTSH2SI Gy,Wsh{sae}
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2c_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2a_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2846] // VCVTSI2SH Vdq,Hdq,Ey
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2a_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1e_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2776] // VCVTHF82PH Vfv{K}{z},aKq,Whv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1e_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1e_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_1e_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2826] // VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2851] // VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2780] // VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2791] // VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2769] // VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2779] // VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2790] // VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2768] // VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_18_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3357] // VMOVSH Wsh{K}{z},aKq,Hdq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3356] // VMOVSH Wsh{K},aKq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_11_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3355] // VMOVSH Vdq{K}{z},aKq,Hdq,Wsh
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3354] // VMOVSH Vdq{K}{z},aKq,Wsh
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_10_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp,
+ /* 11 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp,
+ /* 1e */ (const void *)&gEvexMap_mmmmm_05_opcode_1e_pp,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)&gEvexMap_mmmmm_05_opcode_2a_pp,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)&gEvexMap_mmmmm_05_opcode_2c_pp,
+ /* 2d */ (const void *)&gEvexMap_mmmmm_05_opcode_2d_pp,
+ /* 2e */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp,
+ /* 2f */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp,
+ /* 59 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp,
+ /* 5a */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp,
+ /* 5b */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp,
+ /* 5c */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp,
+ /* 5d */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp,
+ /* 5e */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp,
+ /* 5f */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp,
+ /* 69 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp,
+ /* 6a */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp,
+ /* 6b */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp,
+ /* 6c */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp,
+ /* 6d */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp,
+ /* 6e */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp,
+ /* 6f */ (const void *)&gEvexMap_mmmmm_05_opcode_6f_pp,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp,
+ /* 79 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp,
+ /* 7a */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp,
+ /* 7b */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp,
+ /* 7c */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp,
+ /* 7d */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp,
+ /* 7e */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 863] // DEC Bv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 860] // DEC Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 857] // DEC Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 854] // DEC Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1127] // INC Bv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1124] // INC Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1121] // INC Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1118] // INC Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1973] // PUSH2P Bv,Rv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1972] // PUSH2 Bv,Rv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 862] // DEC Bv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 859] // DEC Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 856] // DEC Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 853] // DEC Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1126] // INC Bv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1123] // INC Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1120] // INC Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1117] // INC Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_ff_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 861] // DEC Bb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 858] // DEC Bb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 855] // DEC Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 852] // DEC Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1125] // INC Bb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1122] // INC Bb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1119] // INC Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1116] // INC Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_fe_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 181] // AOR My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 184] // AXOR My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 5] // AAND My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2] // AADD My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_fc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1412] // MOVDIRI My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2674] // URDMSR Eq,Gq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 897] // ENQCMD rM?,Moq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2678] // UWRMSR Gq,Eq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 899] // ENQCMDS rM?,Moq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1410] // MOVDIR64B rMoq,Moq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1074] // IDIV Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1071] // IDIV Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 880] // DIV Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 877] // DIV Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1102] // IMUL Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1097] // IMUL Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1478] // MUL Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1475] // MUL Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1500] // NEG Bv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1497] // NEG Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1494] // NEG Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1491] // NEG Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1579] // NOT Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1576] // NOT Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 762] // CTESTNLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 726] // CTESTLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 753] // CTESTNL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 717] // CTESTL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 708] // CTESTF Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 816] // CTESTT Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 780] // CTESTNS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 807] // CTESTS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 735] // CTESTNBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 690] // CTESTBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 789] // CTESTNZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 825] // CTESTZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 744] // CTESTNC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 699] // CTESTC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 771] // CTESTNO Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 798] // CTESTO Ev,Iz,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 760] // CTESTNLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 724] // CTESTLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 751] // CTESTNL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 715] // CTESTL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 706] // CTESTF Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 814] // CTESTT Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 778] // CTESTNS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 805] // CTESTS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 733] // CTESTNBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 688] // CTESTBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 787] // CTESTNZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 823] // CTESTZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 742] // CTESTNC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 697] // CTESTC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 769] // CTESTNO Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 796] // CTESTO Ev,Iz,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1073] // IDIV Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1070] // IDIV Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 879] // DIV Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 876] // DIV Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1101] // IMUL Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1096] // IMUL Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1477] // MUL Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1474] // MUL Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1499] // NEG Bv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1496] // NEG Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1493] // NEG Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1490] // NEG Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1578] // NOT Bv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1575] // NOT Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 761] // CTESTNLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 725] // CTESTLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 752] // CTESTNL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 716] // CTESTL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 707] // CTESTF Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 815] // CTESTT Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 779] // CTESTNS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 806] // CTESTS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 734] // CTESTNBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 689] // CTESTBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 788] // CTESTNZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 824] // CTESTZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 743] // CTESTNC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 698] // CTESTC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 770] // CTESTNO Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 797] // CTESTO Ev,Iz,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 759] // CTESTNLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 723] // CTESTLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 750] // CTESTNL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 714] // CTESTL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 705] // CTESTF Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 813] // CTESTT Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 777] // CTESTNS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 804] // CTESTS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 732] // CTESTNBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 687] // CTESTBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 786] // CTESTNZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 822] // CTESTZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 741] // CTESTNC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 696] // CTESTC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 768] // CTESTNO Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 795] // CTESTO Ev,Iz,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1072] // IDIV Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1069] // IDIV Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 878] // DIV Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 875] // DIV Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1100] // IMUL Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1095] // IMUL Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1476] // MUL Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1473] // MUL Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1498] // NEG Bb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1495] // NEG Bb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1492] // NEG Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1489] // NEG Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1577] // NOT Bb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1574] // NOT Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 758] // CTESTNLE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 722] // CTESTLE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 749] // CTESTNL Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 713] // CTESTL Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 704] // CTESTF Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 812] // CTESTT Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 776] // CTESTNS Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 803] // CTESTS Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 731] // CTESTNBE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 686] // CTESTBE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 785] // CTESTNZ Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 821] // CTESTZ Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 740] // CTESTNC Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 695] // CTESTC Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 767] // CTESTNO Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 794] // CTESTO Eb,Ib,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 757] // CTESTNLE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 721] // CTESTLE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 748] // CTESTNL Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 712] // CTESTL Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 703] // CTESTF Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 811] // CTESTT Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 775] // CTESTNS Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 802] // CTESTS Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 730] // CTESTNBE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 685] // CTESTBE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 784] // CTESTNZ Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 820] // CTESTZ Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 739] // CTESTNC Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 694] // CTESTC Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 766] // CTESTNO Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 793] // CTESTO Eb,Ib,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1341] // LZCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1339] // LZCNT Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f5_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1340] // LZCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1338] // LZCNT Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f5_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2659] // TZCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2657] // TZCNT Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f4_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2658] // TZCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2656] // TZCNT Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f4_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1160] // INVPCID Gy,Mdq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1162] // INVVPID Gy,Mdq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 679] // CRC32 Gy,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f1_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 678] // CRC32 Gy,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f1_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1155] // INVEPT Gy,Mdq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 677] // CRC32 Gy,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f0_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2275] // SAR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2266] // SAR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2257] // SAR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2248] // SAR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2232] // SAL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2223] // SAL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2214] // SAL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2205] // SAL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2469] // SHR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2460] // SHR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2451] // SHR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2442] // SHR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2407] // SHL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2398] // SHL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2389] // SHL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2380] // SHL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2069] // RCR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2060] // RCR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2051] // RCR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2042] // RCR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2025] // RCL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2016] // RCL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2007] // RCL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1998] // RCL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2179] // ROR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2170] // ROR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2161] // ROR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2152] // ROR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2137] // ROL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2128] // ROL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2119] // ROL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2110] // ROL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2274] // SAR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2265] // SAR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2256] // SAR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2247] // SAR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2231] // SAL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2222] // SAL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2213] // SAL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2204] // SAL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2468] // SHR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2459] // SHR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2450] // SHR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2441] // SHR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2406] // SHL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2397] // SHL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2388] // SHL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2379] // SHL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2068] // RCR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2059] // RCR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2050] // RCR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2041] // RCR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2024] // RCL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2015] // RCL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2006] // RCL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1997] // RCL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2178] // ROR Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2169] // ROR Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2160] // ROR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2151] // ROR Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2136] // ROL Bv,Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2127] // ROL Bv,Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2118] // ROL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2109] // ROL Ev,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2273] // SAR Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2264] // SAR Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2255] // SAR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2246] // SAR Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2230] // SAL Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2221] // SAL Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2212] // SAL Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2203] // SAL Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2467] // SHR Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2458] // SHR Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2449] // SHR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2440] // SHR Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2405] // SHL Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2396] // SHL Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2387] // SHL Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2378] // SHL Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2067] // RCR Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2058] // RCR Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2049] // RCR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2040] // RCR Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2023] // RCL Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2014] // RCL Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2005] // RCL Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1996] // RCL Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2177] // ROR Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2168] // ROR Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2159] // ROR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2150] // ROR Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2135] // ROL Bb,Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2126] // ROL Bb,Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2117] // ROL Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2108] // ROL Eb,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2272] // SAR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2263] // SAR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2254] // SAR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2245] // SAR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2229] // SAL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2220] // SAL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2211] // SAL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2202] // SAL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2466] // SHR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2457] // SHR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2448] // SHR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2439] // SHR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2404] // SHL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2395] // SHL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2386] // SHL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2377] // SHL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2066] // RCR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2057] // RCR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2048] // RCR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2039] // RCR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2022] // RCL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2013] // RCL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2004] // RCL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1995] // RCL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2176] // ROR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2167] // ROR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2158] // ROR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2149] // ROR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2134] // ROL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2125] // ROL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2116] // ROL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2107] // ROL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2271] // SAR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2262] // SAR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2253] // SAR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2244] // SAR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2228] // SAL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2219] // SAL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2210] // SAL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2201] // SAL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2465] // SHR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2456] // SHR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2447] // SHR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2438] // SHR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2403] // SHL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2394] // SHL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2385] // SHL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2376] // SHL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2065] // RCR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2056] // RCR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2047] // RCR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2038] // RCR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2021] // RCL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2012] // RCL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2003] // RCL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1994] // RCL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2175] // ROR Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2166] // ROR Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2157] // ROR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2148] // ROR Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2133] // ROL Bv,Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2124] // ROL Bv,Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2115] // ROL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2106] // ROL Ev,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2270] // SAR Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2261] // SAR Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2252] // SAR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2243] // SAR Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2227] // SAL Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2218] // SAL Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2209] // SAL Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2200] // SAL Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2464] // SHR Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2455] // SHR Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2446] // SHR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2437] // SHR Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2402] // SHL Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2393] // SHL Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2384] // SHL Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2375] // SHL Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2064] // RCR Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2055] // RCR Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2046] // RCR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2037] // RCR Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2020] // RCL Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2011] // RCL Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2002] // RCL Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1993] // RCL Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2174] // ROR Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2165] // ROR Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2156] // ROR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2147] // ROR Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2132] // ROL Bb,Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2123] // ROL Bb,Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2114] // ROL Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2105] // ROL Eb,1
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2269] // SAR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2260] // SAR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2251] // SAR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2242] // SAR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2226] // SAL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2217] // SAL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2208] // SAL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2199] // SAL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2463] // SHR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2454] // SHR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2445] // SHR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2436] // SHR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2401] // SHL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2392] // SHL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2383] // SHL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2374] // SHL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2063] // RCR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2054] // RCR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2045] // RCR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2036] // RCR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2019] // RCL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2010] // RCL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2001] // RCL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1992] // RCL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2173] // ROR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2164] // ROR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2155] // ROR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2146] // ROR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2131] // ROL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2122] // ROL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2113] // ROL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2104] // ROL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2268] // SAR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2259] // SAR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2250] // SAR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2241] // SAR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2225] // SAL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2216] // SAL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2207] // SAL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2198] // SAL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2462] // SHR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2453] // SHR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2444] // SHR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2435] // SHR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2400] // SHL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2391] // SHL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2382] // SHL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2373] // SHL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2062] // RCR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2053] // RCR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2044] // RCR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2035] // RCR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2018] // RCL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2009] // RCL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2000] // RCL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1991] // RCL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2172] // ROR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2163] // ROR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2154] // ROR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2145] // ROR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2130] // ROL Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2121] // ROL Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2112] // ROL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2103] // ROL Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_c1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2267] // SAR Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2258] // SAR Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2249] // SAR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2240] // SAR Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2224] // SAL Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2215] // SAL Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2206] // SAL Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2197] // SAL Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2461] // SHR Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2452] // SHR Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2443] // SHR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2434] // SHR Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2399] // SHL Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2390] // SHL Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2381] // SHL Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2372] // SHL Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2061] // RCR Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2052] // RCR Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2043] // RCR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2034] // RCR Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2017] // RCL Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2008] // RCL Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1999] // RCL Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1990] // RCL Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2171] // ROR Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2162] // ROR Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2153] // ROR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2144] // ROR Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2129] // ROL Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2120] // ROL Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2111] // ROL Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2102] // ROL Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_c0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1106] // IMUL Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1104] // IMUL Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1099] // IMUL Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1094] // IMUL Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_af_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1105] // IMUL Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1103] // IMUL Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1098] // IMUL Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1093] // IMUL Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_af_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_af_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2491] // SHRD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2487] // SHRD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2483] // SHRD Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2479] // SHRD Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ad_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2489] // SHRD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2485] // SHRD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2481] // SHRD Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2477] // SHRD Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ad_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_ad_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2429] // SHLD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2425] // SHLD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2421] // SHLD Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2417] // SHLD Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_a5_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2427] // SHLD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2423] // SHLD Bv,Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2419] // SHLD Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2415] // SHLD Ev,Gv,CL
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_a5_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_a5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1832] // POP2P Bv,Rv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1831] // POP2 Bv,Rv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_8f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1838] // POPCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1836] // POPCNT Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_88_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1837] // POPCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1835] // POPCNT Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_88_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_88_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 756] // CTESTNLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 720] // CTESTLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 747] // CTESTNL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 711] // CTESTL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 702] // CTESTF Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 810] // CTESTT Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 774] // CTESTNS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 801] // CTESTS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 729] // CTESTNBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 684] // CTESTBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 783] // CTESTNZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 819] // CTESTZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 738] // CTESTNC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 693] // CTESTC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 765] // CTESTNO Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 792] // CTESTO Ev,Gv,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_85_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 755] // CTESTNLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 719] // CTESTLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 746] // CTESTNL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 710] // CTESTL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 701] // CTESTF Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 809] // CTESTT Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 773] // CTESTNS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 800] // CTESTS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 728] // CTESTNBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 683] // CTESTBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 782] // CTESTNZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 818] // CTESTZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 737] // CTESTNC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 692] // CTESTC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 764] // CTESTNO Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 791] // CTESTO Ev,Gv,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_85_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_85_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 754] // CTESTNLE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 718] // CTESTLE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 745] // CTESTNL Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 709] // CTESTL Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 700] // CTESTF Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 808] // CTESTT Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 772] // CTESTNS Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 799] // CTESTS Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 727] // CTESTNBE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 682] // CTESTBE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 781] // CTESTNZ Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 817] // CTESTZ Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 736] // CTESTNC Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 691] // CTESTC Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 763] // CTESTNO Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 790] // CTESTO Eb,Gb,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_84_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_84_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 343] // CCMPNLE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 299] // CCMPLE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 332] // CCMPNL Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 288] // CCMPL Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 277] // CCMPF Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 409] // CCMPT Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 365] // CCMPNS Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 398] // CCMPS Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 310] // CCMPNBE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 255] // CCMPBE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 376] // CCMPNZ Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 420] // CCMPZ Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 321] // CCMPNC Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 266] // CCMPC Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 354] // CCMPNO Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 387] // CCMPO Ev,Ib,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4177] // XOR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4166] // XOR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4155] // XOR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4144] // XOR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2572] // SUB Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2561] // SUB Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2550] // SUB Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2539] // SUB Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 163] // AND Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 152] // AND Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 141] // AND Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 130] // AND Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2306] // SBB Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2295] // SBB Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 29] // ADC Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 18] // ADC Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1625] // OR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1614] // OR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1603] // OR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1592] // OR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 86] // ADD Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 75] // ADD Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 64] // ADD Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 53] // ADD Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 342] // CCMPNLE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 298] // CCMPLE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 331] // CCMPNL Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 287] // CCMPL Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 276] // CCMPF Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 408] // CCMPT Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 364] // CCMPNS Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 397] // CCMPS Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 309] // CCMPNBE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 254] // CCMPBE Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 375] // CCMPNZ Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 419] // CCMPZ Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 320] // CCMPNC Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 265] // CCMPC Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 353] // CCMPNO Ev,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 386] // CCMPO Ev,Ib,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4176] // XOR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4165] // XOR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4154] // XOR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4143] // XOR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2571] // SUB Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2560] // SUB Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2549] // SUB Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2538] // SUB Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 162] // AND Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 151] // AND Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 140] // AND Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 129] // AND Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2305] // SBB Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2294] // SBB Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 28] // ADC Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 17] // ADC Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1624] // OR Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1613] // OR Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1602] // OR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1591] // OR Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 85] // ADD Bv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 74] // ADD Bv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 63] // ADD Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 52] // ADD Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_83_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 341] // CCMPNLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 297] // CCMPLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 330] // CCMPNL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 286] // CCMPL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 275] // CCMPF Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 407] // CCMPT Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 363] // CCMPNS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 396] // CCMPS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 308] // CCMPNBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 253] // CCMPBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 374] // CCMPNZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 418] // CCMPZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 319] // CCMPNC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 264] // CCMPC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 352] // CCMPNO Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 385] // CCMPO Ev,Iz,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4175] // XOR Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4164] // XOR Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4153] // XOR Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4142] // XOR Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2570] // SUB Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2559] // SUB Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2548] // SUB Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2537] // SUB Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 161] // AND Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 150] // AND Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 139] // AND Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 128] // AND Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2304] // SBB Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2293] // SBB Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 27] // ADC Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 16] // ADC Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1623] // OR Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1612] // OR Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1601] // OR Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1590] // OR Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 84] // ADD Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 73] // ADD Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 62] // ADD Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 51] // ADD Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 340] // CCMPNLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 296] // CCMPLE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 329] // CCMPNL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 285] // CCMPL Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 274] // CCMPF Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 406] // CCMPT Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 362] // CCMPNS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 395] // CCMPS Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 307] // CCMPNBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 252] // CCMPBE Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 373] // CCMPNZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 417] // CCMPZ Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 318] // CCMPNC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 263] // CCMPC Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 351] // CCMPNO Ev,Iz,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 384] // CCMPO Ev,Iz,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4174] // XOR Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4163] // XOR Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4152] // XOR Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4141] // XOR Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2569] // SUB Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2558] // SUB Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2547] // SUB Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2536] // SUB Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 160] // AND Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 149] // AND Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 138] // AND Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 127] // AND Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2303] // SBB Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2292] // SBB Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 26] // ADC Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 15] // ADC Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1622] // OR Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1611] // OR Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1600] // OR Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1589] // OR Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 83] // ADD Bv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 72] // ADD Bv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 61] // ADD Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 50] // ADD Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_81_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 339] // CCMPNLE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 295] // CCMPLE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 328] // CCMPNL Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 284] // CCMPL Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 273] // CCMPF Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 405] // CCMPT Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 361] // CCMPNS Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 394] // CCMPS Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 306] // CCMPNBE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 251] // CCMPBE Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 372] // CCMPNZ Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 416] // CCMPZ Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 317] // CCMPNC Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 262] // CCMPC Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 350] // CCMPNO Eb,Ib,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 383] // CCMPO Eb,Ib,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4173] // XOR Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4162] // XOR Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4151] // XOR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4140] // XOR Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2568] // SUB Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2557] // SUB Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2546] // SUB Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2535] // SUB Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 159] // AND Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 148] // AND Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 137] // AND Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 126] // AND Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2302] // SBB Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2291] // SBB Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 25] // ADC Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 14] // ADC Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1621] // OR Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1610] // OR Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1599] // OR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1588] // OR Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 82] // ADD Bb,Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 71] // ADD Bb,Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 60] // ADD Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 49] // ADD Eb,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_80_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1092] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1088] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1084] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1080] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_6b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1091] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1087] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1083] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1079] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_6b_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_6b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1090] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1086] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1082] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1078] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_69_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1089] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1085] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1081] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1077] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_69_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_69_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 104] // ADOX By,Gy,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 103] // ADOX Gy,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 41] // ADCX By,Gy,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 40] // ADCX Gy,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4111] // WRSSQ My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4109] // WRSSD My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_66_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4115] // WRUSSQ My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4113] // WRUSSD My,Gy
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_65_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1400] // MOVBE Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_61_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1399] // MOVBE Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_61_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_61_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1398] // MOVBE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_60_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1397] // MOVBE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_60_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_60_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2344] // SETNLE Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 486] // CFCMOVNLE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 589] // CMOVNLE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 483] // CFCMOVNLE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 484] // CFCMOVNLE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 482] // CFCMOVNLE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 485] // CFCMOVNLE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 588] // CMOVNLE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 480] // CFCMOVNLE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 481] // CFCMOVNLE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 479] // CFCMOVNLE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2336] // SETLE Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 454] // CFCMOVLE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 577] // CMOVLE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 451] // CFCMOVLE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 452] // CFCMOVLE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 450] // CFCMOVLE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 453] // CFCMOVLE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 576] // CMOVLE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 448] // CFCMOVLE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 449] // CFCMOVLE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 447] // CFCMOVLE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2342] // SETNL Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 478] // CFCMOVNL Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 586] // CMOVNL Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 475] // CFCMOVNL Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 476] // CFCMOVNL Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 474] // CFCMOVNL Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 477] // CFCMOVNL Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 585] // CMOVNL Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 472] // CFCMOVNL Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 473] // CFCMOVNL Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 471] // CFCMOVNL Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2334] // SETL Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 446] // CFCMOVL Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 574] // CMOVL Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 443] // CFCMOVL Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 444] // CFCMOVL Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 442] // CFCMOVL Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 445] // CFCMOVL Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 573] // CMOVL Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 440] // CFCMOVL Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 441] // CFCMOVL Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 439] // CFCMOVL Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2348] // SETNP Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 502] // CFCMOVNP Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 595] // CMOVNP Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 499] // CFCMOVNP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 500] // CFCMOVNP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 498] // CFCMOVNP Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 501] // CFCMOVNP Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 594] // CMOVNP Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 496] // CFCMOVNP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 497] // CFCMOVNP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 495] // CFCMOVNP Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2356] // SETP Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 534] // CFCMOVP Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 607] // CMOVP Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 531] // CFCMOVP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 532] // CFCMOVP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 530] // CFCMOVP Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 533] // CFCMOVP Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 606] // CMOVP Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 528] // CFCMOVP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 529] // CFCMOVP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 527] // CFCMOVP Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2350] // SETNS Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 510] // CFCMOVNS Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 598] // CMOVNS Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 507] // CFCMOVNS Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 508] // CFCMOVNS Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 506] // CFCMOVNS Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 509] // CFCMOVNS Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 597] // CMOVNS Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 504] // CFCMOVNS Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 505] // CFCMOVNS Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 503] // CFCMOVNS Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_49_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2358] // SETS Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 542] // CFCMOVS Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 610] // CMOVS Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 539] // CFCMOVS Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 540] // CFCMOVS Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 538] // CFCMOVS Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 541] // CFCMOVS Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 609] // CMOVS Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 536] // CFCMOVS Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 537] // CFCMOVS Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 535] // CFCMOVS Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_48_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2338] // SETNBE Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 462] // CFCMOVNBE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 580] // CMOVNBE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 459] // CFCMOVNBE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 460] // CFCMOVNBE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 458] // CFCMOVNBE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 461] // CFCMOVNBE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 579] // CMOVNBE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 456] // CFCMOVNBE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 457] // CFCMOVNBE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 455] // CFCMOVNBE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_47_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2330] // SETBE Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 430] // CFCMOVBE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 568] // CMOVBE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 427] // CFCMOVBE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 428] // CFCMOVBE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 426] // CFCMOVBE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 429] // CFCMOVBE Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 567] // CMOVBE Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 424] // CFCMOVBE Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 425] // CFCMOVBE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 423] // CFCMOVBE Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_46_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2352] // SETNZ Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 518] // CFCMOVNZ Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 601] // CMOVNZ Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 515] // CFCMOVNZ Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 516] // CFCMOVNZ Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 514] // CFCMOVNZ Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 517] // CFCMOVNZ Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 600] // CMOVNZ Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 512] // CFCMOVNZ Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 513] // CFCMOVNZ Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 511] // CFCMOVNZ Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_45_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2361] // SETZ Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 550] // CFCMOVZ Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 613] // CMOVZ Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 547] // CFCMOVZ Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 548] // CFCMOVZ Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 546] // CFCMOVZ Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 549] // CFCMOVZ Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 612] // CMOVZ Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 544] // CFCMOVZ Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 545] // CFCMOVZ Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 543] // CFCMOVZ Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_44_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2340] // SETNC Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 470] // CFCMOVNC Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 583] // CMOVNC Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 467] // CFCMOVNC Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 468] // CFCMOVNC Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 466] // CFCMOVNC Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 469] // CFCMOVNC Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 582] // CMOVNC Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 464] // CFCMOVNC Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 465] // CFCMOVNC Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 463] // CFCMOVNC Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_43_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2332] // SETC Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 438] // CFCMOVC Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 571] // CMOVC Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 435] // CFCMOVC Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 436] // CFCMOVC Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 434] // CFCMOVC Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 437] // CFCMOVC Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 570] // CMOVC Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 432] // CFCMOVC Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 433] // CFCMOVC Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 431] // CFCMOVC Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_42_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2346] // SETNO Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 494] // CFCMOVNO Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 592] // CMOVNO Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 491] // CFCMOVNO Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 492] // CFCMOVNO Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 490] // CFCMOVNO Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 493] // CFCMOVNO Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 591] // CMOVNO Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 488] // CFCMOVNO Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 489] // CFCMOVNO Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 487] // CFCMOVNO Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_41_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2354] // SETO Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 526] // CFCMOVO Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 604] // CMOVO Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 523] // CFCMOVO Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 524] // CFCMOVO Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 522] // CFCMOVO Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 525] // CFCMOVO Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 603] // CMOVO Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 520] // CFCMOVO Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 521] // CFCMOVO Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 519] // CFCMOVO Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_40_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 338] // CCMPNLE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 294] // CCMPLE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 327] // CCMPNL Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 283] // CCMPL Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 272] // CCMPF Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 404] // CCMPT Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 360] // CCMPNS Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 393] // CCMPS Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 305] // CCMPNBE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 250] // CCMPBE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 371] // CCMPNZ Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 415] // CCMPZ Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 316] // CCMPNC Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 261] // CCMPC Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 349] // CCMPNO Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 382] // CCMPO Gv,Ev,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_3b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 337] // CCMPNLE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 293] // CCMPLE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 326] // CCMPNL Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 282] // CCMPL Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 271] // CCMPF Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 403] // CCMPT Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 359] // CCMPNS Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 392] // CCMPS Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 304] // CCMPNBE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 249] // CCMPBE Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 370] // CCMPNZ Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 414] // CCMPZ Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 315] // CCMPNC Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 260] // CCMPC Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 348] // CCMPNO Gv,Ev,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 381] // CCMPO Gv,Ev,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_3b_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_3b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 336] // CCMPNLE Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 292] // CCMPLE Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 325] // CCMPNL Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 281] // CCMPL Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 270] // CCMPF Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 402] // CCMPT Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 358] // CCMPNS Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 391] // CCMPS Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 303] // CCMPNBE Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 248] // CCMPBE Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 369] // CCMPNZ Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 413] // CCMPZ Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 314] // CCMPNC Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 259] // CCMPC Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 347] // CCMPNO Gb,Eb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 380] // CCMPO Gb,Eb,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_3a_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_3a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 335] // CCMPNLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 291] // CCMPLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 324] // CCMPNL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 280] // CCMPL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 269] // CCMPF Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 401] // CCMPT Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 357] // CCMPNS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 390] // CCMPS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 302] // CCMPNBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 247] // CCMPBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 368] // CCMPNZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 412] // CCMPZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 313] // CCMPNC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 258] // CCMPC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 346] // CCMPNO Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 379] // CCMPO Ev,Gv,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_39_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 334] // CCMPNLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 290] // CCMPLE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 323] // CCMPNL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 279] // CCMPL Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 268] // CCMPF Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 400] // CCMPT Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 356] // CCMPNS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 389] // CCMPS Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 301] // CCMPNBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 246] // CCMPBE Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 367] // CCMPNZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 411] // CCMPZ Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 312] // CCMPNC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 257] // CCMPC Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 345] // CCMPNO Ev,Gv,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 378] // CCMPO Ev,Gv,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_39_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_39_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 333] // CCMPNLE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 289] // CCMPLE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 322] // CCMPNL Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 278] // CCMPL Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 267] // CCMPF Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 399] // CCMPT Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 355] // CCMPNS Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 388] // CCMPS Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 300] // CCMPNBE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 245] // CCMPBE Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 366] // CCMPNZ Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 410] // CCMPZ Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 311] // CCMPNC Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 256] // CCMPC Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 344] // CCMPNO Eb,Gb,dfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 377] // CCMPO Eb,Gb,dfv
+};
+
+const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc =
+{
+ ND_ILUT_EX_SC,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_03_leaf,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_04_leaf,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_05_leaf,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_06_leaf,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_07_leaf,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_08_leaf,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_09_leaf,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0a_leaf,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0b_leaf,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0c_leaf,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0d_leaf,
+ /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0e_leaf,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0f_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_38_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_38_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4172] // XOR Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4161] // XOR Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4150] // XOR Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4139] // XOR Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_33_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4171] // XOR Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4160] // XOR Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4149] // XOR Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4138] // XOR Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_33_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_33_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4170] // XOR Bb,Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4159] // XOR Bb,Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4148] // XOR Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4137] // XOR Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_32_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_32_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4169] // XOR Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4158] // XOR Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4147] // XOR Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4136] // XOR Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_31_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4168] // XOR Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4157] // XOR Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4146] // XOR Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4135] // XOR Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_31_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_31_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4167] // XOR Bb,Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4156] // XOR Bb,Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4145] // XOR Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4134] // XOR Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_30_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_30_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2490] // SHRD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2486] // SHRD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2482] // SHRD Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2478] // SHRD Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2c_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2488] // SHRD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2484] // SHRD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2480] // SHRD Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2476] // SHRD Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2c_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2567] // SUB Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2556] // SUB Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2545] // SUB Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2534] // SUB Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2566] // SUB Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2555] // SUB Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2544] // SUB Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2533] // SUB Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2b_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2565] // SUB Bb,Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2554] // SUB Bb,Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2543] // SUB Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2532] // SUB Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2a_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2564] // SUB Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2553] // SUB Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2542] // SUB Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2531] // SUB Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_29_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2563] // SUB Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2552] // SUB Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2541] // SUB Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2530] // SUB Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_29_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_29_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2562] // SUB Bb,Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2551] // SUB Bb,Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2540] // SUB Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2529] // SUB Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_28_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_28_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2428] // SHLD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2424] // SHLD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2420] // SHLD Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2416] // SHLD Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_24_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2426] // SHLD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2422] // SHLD Bv,Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2418] // SHLD Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2414] // SHLD Ev,Gv,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_24_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_24_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 158] // AND Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 147] // AND Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 136] // AND Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 125] // AND Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_23_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 157] // AND Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 146] // AND Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 135] // AND Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 124] // AND Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_23_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_23_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 156] // AND Bb,Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 145] // AND Bb,Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 134] // AND Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 123] // AND Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_22_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_22_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 155] // AND Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 144] // AND Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 133] // AND Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 122] // AND Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_21_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 154] // AND Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 143] // AND Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 132] // AND Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 121] // AND Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_21_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_21_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 153] // AND Bb,Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 142] // AND Bb,Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 131] // AND Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 120] // AND Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_20_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_20_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2301] // SBB Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2290] // SBB Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2300] // SBB Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2289] // SBB Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1b_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2299] // SBB Bb,Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2288] // SBB Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1a_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2298] // SBB Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2287] // SBB Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_19_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2297] // SBB Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2286] // SBB Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_19_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_19_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2296] // SBB Bb,Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2285] // SBB Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_18_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_18_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 24] // ADC Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 13] // ADC Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_13_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 23] // ADC Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 12] // ADC Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_13_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_13_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 22] // ADC Bb,Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 11] // ADC Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_12_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_12_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 21] // ADC Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 10] // ADC Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_11_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 20] // ADC Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 9] // ADC Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_11_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_11_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 19] // ADC Bb,Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 8] // ADC Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_10_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_10_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1620] // OR Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1609] // OR Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1598] // OR Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1587] // OR Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1619] // OR Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1608] // OR Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1597] // OR Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1586] // OR Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0b_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1618] // OR Bb,Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1607] // OR Bb,Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1596] // OR Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1585] // OR Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0a_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1617] // OR Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1606] // OR Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1595] // OR Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1584] // OR Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_09_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1616] // OR Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1605] // OR Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1594] // OR Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1583] // OR Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_09_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_09_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1615] // OR Bb,Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1604] // OR Bb,Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1593] // OR Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1582] // OR Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_08_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_08_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 81] // ADD Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 70] // ADD Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 59] // ADD Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 48] // ADD Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_03_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 80] // ADD Bv,Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 69] // ADD Bv,Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 58] // ADD Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 47] // ADD Gv,Ev
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_03_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_03_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 79] // ADD Bb,Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 68] // ADD Bb,Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 57] // ADD Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 46] // ADD Gb,Eb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_02_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_02_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 78] // ADD Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 67] // ADD Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 56] // ADD Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 45] // ADD Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_01_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 77] // ADD Bv,Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 66] // ADD Bv,Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 55] // ADD Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 44] // ADD Ev,Gv
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_01_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_01_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 76] // ADD Bb,Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 65] // ADD Bb,Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 54] // ADD Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 43] // ADD Eb,Gb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_00_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_00_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gEvexMap_mmmmm_04_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp,
+ /* 11 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp,
+ /* 12 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp,
+ /* 13 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp,
+ /* 19 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp,
+ /* 1a */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp,
+ /* 1b */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp,
+ /* 21 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp,
+ /* 22 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp,
+ /* 23 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp,
+ /* 24 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp,
+ /* 29 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp,
+ /* 2a */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp,
+ /* 2b */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp,
+ /* 2c */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp,
+ /* 31 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp,
+ /* 32 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp,
+ /* 33 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp,
+ /* 39 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp,
+ /* 3a */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp,
+ /* 3b */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp,
+ /* 41 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp,
+ /* 42 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp,
+ /* 43 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp,
+ /* 44 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp,
+ /* 45 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp,
+ /* 46 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp,
+ /* 47 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp,
+ /* 48 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp,
+ /* 49 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp,
+ /* 4a */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp,
+ /* 4b */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp,
+ /* 4c */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp,
+ /* 4d */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp,
+ /* 4e */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp,
+ /* 4f */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp,
+ /* 61 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp,
+ /* 66 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp,
+ /* 81 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp,
+ /* 84 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp,
+ /* 85 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp,
+ /* c1 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp,
+ /* d1 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp,
+ /* d2 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp,
+ /* d3 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp,
+ /* f1 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp,
+ /* f2 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp,
+ /* f5 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp,
+ /* f6 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp,
+ /* f7 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp,
+ /* f8 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp,
+ /* f9 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp,
+ /* ff */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2186] // RORX Gy,Ey,Ib
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_ND gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd =
+{
+ ND_ILUT_EX_ND,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_f0_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_f0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3200] // VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_cf_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_cf_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_cf_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3202] // VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_ce_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_ce_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_ce_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2743] // VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2751] // VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2746] // VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_c2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2614] // TCVTROWPS2PHL Voq,mTt,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2610] // TCVTROWPS2PBF16L Voq,mTt,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_77_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3851] // VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3850] // VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_73_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_73_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_72_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3855] // VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_72_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_72_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_72_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_72_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3842] // VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3841] // VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_71_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_71_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_70_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3846] // VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_70_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_70_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_70_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_70_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3163] // VFPCLASSSD rKq{K},aKq,Wsd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3165] // VFPCLASSSS rKq{K},aKq,Wss,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3164] // VFPCLASSSH rKq{K},aKq,Wsh,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_67_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3159] // VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3160] // VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3162] // VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3161] // VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_66_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3987] // VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3989] // VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3988] // VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_57_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3983] // VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3984] // VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3986] // VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3985] // VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_56_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2951] // VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2952] // VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_55_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_55_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2949] // VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2950] // VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_54_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_54_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3251] // VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3253] // VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_53_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3252] // VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_53_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_53_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3247] // VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3248] // VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3250] // VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3249] // VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_52_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3968] // VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3969] // VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_51_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_51_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3966] // VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3967] // VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_50_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_50_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_44_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3478] // VPCLMULQDQ Vfv,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_44_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_44_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4039] // VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4038] // VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_43_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_43_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_42_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3384] // VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_42_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2909] // VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_42_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3509] // VPCMPW rKq{K},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3482] // VPCMPB rKq{K},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3508] // VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3505] // VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2940] // VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2938] // VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_3b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3219] // VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3217] // VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_3a_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2939] // VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2937] // VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_39_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_39_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3218] // VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3216] // VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_38_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_38_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3197] // VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3199] // VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3198] // VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_27_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3193] // VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3194] // VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3196] // VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3195] // VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_26_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3937] // VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3936] // VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_25_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_25_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4037] // VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4036] // VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_23_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_23_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3654] // VPINSRQ Vdq,Hdq,Eq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3652] // VPINSRD Vdq,Hdq,Ed,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_22_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_22_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3221] // VINSERTPS Vdq,Hdq,Udq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3220] // VINSERTPS Vdq,Hdq,Md,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_21_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3649] // VPINSRB Vdq,Hdq,Rd,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3648] // VPINSRB Vdq,Hdq,Mb,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_20_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3504] // VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3483] // VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3507] // VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3506] // VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2823] // VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2935] // VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2933] // VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_1b_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3214] // VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3212] // VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_1a_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2934] // VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2932] // VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_19_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_19_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3213] // VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3211] // VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_18_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_18_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2942] // VEXTRACTPS Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2941] // VEXTRACTPS Md,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_17_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3609] // VPEXTRQ Ry,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3605] // VPEXTRD Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3608] // VPEXTRQ Mq,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3604] // VPEXTRD Md,Vdq,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_16_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3614] // VPEXTRW Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3613] // VPEXTRW Mw,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_15_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3601] // VPEXTRB Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3600] // VPEXTRB Mb,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_14_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0f_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3445] // VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0f_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3994] // VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3996] // VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3995] // VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_09_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3991] // VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_09_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_09_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_09_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_09_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3990] // VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3993] // VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3992] // VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_08_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2608] // TCVTROWPS2PBF16H Voq,mTt,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2606] // TCVTROWD2PS Voq,mTt,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2642] // TILEMOVROW Voq,mTt,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2612] // TCVTROWPS2PHH Voq,mTt,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_07_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_05_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3572] // VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_05_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_05_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_05_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_05_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3576] // VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_04_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_04_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_04_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2710] // VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2709] // VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_03_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_03_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_01_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3581] // VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_01_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_01_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_01_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_01_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_00_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3587] // VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_00_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_00_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_00_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_00_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gEvexMap_mmmmm_03_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_00_pp,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_01_pp,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_03_opcode_04_pp,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_03_opcode_05_pp,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_03_opcode_07_pp,
+ /* 08 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp,
+ /* 09 */ (const void *)&gEvexMap_mmmmm_03_opcode_09_pp,
+ /* 0a */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_03_opcode_0b_pp,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)&gEvexMap_mmmmm_03_opcode_0f_pp,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp,
+ /* 15 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp,
+ /* 16 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp,
+ /* 17 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp,
+ /* 18 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp,
+ /* 19 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp,
+ /* 1a */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp,
+ /* 1b */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)&gEvexMap_mmmmm_03_opcode_1d_pp,
+ /* 1e */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp,
+ /* 1f */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp,
+ /* 20 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp,
+ /* 21 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp,
+ /* 22 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp,
+ /* 23 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp,
+ /* 26 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp,
+ /* 27 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp,
+ /* 39 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp,
+ /* 3a */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp,
+ /* 3b */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp,
+ /* 3f */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp,
+ /* 43 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp,
+ /* 44 */ (const void *)&gEvexMap_mmmmm_03_opcode_44_pp,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp,
+ /* 51 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp,
+ /* 52 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp,
+ /* 53 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp,
+ /* 54 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp,
+ /* 55 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp,
+ /* 56 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp,
+ /* 57 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp,
+ /* 67 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)&gEvexMap_mmmmm_03_opcode_70_pp,
+ /* 71 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp,
+ /* 72 */ (const void *)&gEvexMap_mmmmm_03_opcode_72_pp,
+ /* 73 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)&gEvexMap_mmmmm_03_opcode_77_pp,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)&gEvexMap_mmmmm_03_opcode_ce_pp,
+ /* cf */ (const void *)&gEvexMap_mmmmm_03_opcode_cf_pp,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2494] // SHRX Gy,Ey,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2282] // SARX Gy,Ey,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2432] // SHLX Gy,Ey,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 187] // BEXTR Gy,Ey,By
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 186] // BEXTR Gy,Ey,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1485] // MULX Gy,By,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f6_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1712] // PDEP Gy,By,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1714] // PEXT Gy,By,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 238] // BZHI Gy,Ey,By
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 237] // BZHI Gy,Ey,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 201] // BLSI By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 200] // BLSI By,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 205] // BLSMSK By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 204] // BLSMSK By,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 208] // BLSR By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 207] // BLSR By,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 175] // ANDN Gy,By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 174] // ANDN Gy,By,Ey
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f2_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 637] // CMPNLEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ef_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 629] // CMPLEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ee_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 639] // CMPNLXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ed_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 631] // CMPLXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ec_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 643] // CMPNPXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_eb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 653] // CMPPXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ea_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 645] // CMPNSXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 665] // CMPSXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 633] // CMPNBEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 625] // CMPBEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 647] // CMPNZXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 671] // CMPZXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 635] // CMPNCXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 627] // CMPCXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 641] // CMPNOXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 649] // CMPOXADD My,Gy,By
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_df_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2701] // VAESDECLAST Vfv,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_df_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_df_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_de_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2699] // VAESDEC Vfv,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_de_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_de_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dd_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2705] // VAESENCLAST Vfv,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_dd_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dc_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2703] // VAESENC Vfv,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_dc_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4049] // VSM4RNDS4 Vfv,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_da_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4047] // VSM4KEY4 Vfv,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_da_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_da_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3546] // VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3550] // VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3554] // VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_d3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3544] // VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3548] // VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3552] // VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_d2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3204] // VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cf_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cf_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cf_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4007] // VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4008] // VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cd_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4005] // VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4006] // VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_cc_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3976] // VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3977] // VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cb_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3974] // VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3975] // VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ca_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ca_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2927] // VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2928] // VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c8_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4029] // VSCATTERPF1QPD Mvm64n{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4030] // VSCATTERPF1QPS Mvm64n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4025] // VSCATTERPF0QPD Mvm64n{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4026] // VSCATTERPF0QPS Mvm64n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3180] // VGATHERPF1QPD Mvm64n{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3181] // VGATHERPF1QPS Mvm64n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3176] // VGATHERPF0QPD Mvm64n{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3177] // VGATHERPF0QPS Mvm64n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4027] // VSCATTERPF1DPD Mvm32h{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4028] // VSCATTERPF1DPS Mvm32n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4023] // VSCATTERPF0DPD Mvm32h{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4024] // VSCATTERPF0DPS Mvm32n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3178] // VGATHERPF1DPD Mvm32h{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3179] // VGATHERPF1DPS Mvm32n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3174] // VGATHERPF0DPD Mvm32h{K},aKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3175] // VGATHERPF0DPS Mvm32n{K},aKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3523] // VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3522] // VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c4_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3146] // VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3149] // VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bf_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bf_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3141] // VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3144] // VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_be_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_be_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3105] // VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3108] // VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bd_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3100] // VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3103] // VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bc_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3043] // VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3046] // VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bb_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3038] // VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3041] // VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ba_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ba_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2981] // VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2984] // VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b9_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2976] // VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2979] // VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b8_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3058] // VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3061] // VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b7_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3006] // VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3009] // VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3674] // VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b5_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b5_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3676] // VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b4_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b4_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3135] // VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3138] // VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_af_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_af_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3130] // VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3133] // VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ae_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ae_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3094] // VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3097] // VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ad_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ad_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3089] // VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3092] // VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ac_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ac_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2685] // V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3032] // VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3035] // VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ab_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2684] // V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3027] // VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3030] // VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_aa_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2970] // VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2973] // VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a9_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2965] // VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2968] // VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a8_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3053] // VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3056] // VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a7_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3001] // VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3004] // VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4031] // VSCATTERQPD Mvm64n{K},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4032] // VSCATTERQPS Mvm64n{K},aKq,Vhv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4021] // VSCATTERDPD Mvm32h{K},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4022] // VSCATTERDPS Mvm32n{K},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3827] // VPSCATTERQQ Mvm64n{K},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3826] // VPSCATTERQD Mvm64n{K},aKq,Vhv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3825] // VPSCATTERDQ Mvm32h{K},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3824] // VPSCATTERDD Mvm32n{K},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3124] // VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3127] // VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3119] // VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3122] // VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3083] // VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3086] // VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3078] // VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3081] // VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2683] // V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3021] // VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3024] // VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2682] // V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3016] // VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3019] // VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2959] // VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2962] // VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_99_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_99_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2954] // VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2957] // VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_98_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_98_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3048] // VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3051] // VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_97_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_97_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2996] // VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2999] // VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_96_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_96_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3182] // VGATHERQPD Vfv{K},aKq,Mvm64n
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3184] // VGATHERQPS Vhv{K},aKq,Mvm64n
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_93_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3170] // VGATHERDPD Vfv{K},aKq,Mvm32h
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3172] // VGATHERDPS Vfv{K},aKq,Mvm32n
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_92_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3624] // VPGATHERQQ Vfv{K},aKq,Mvm64n
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3622] // VPGATHERQD Vhv{K},aKq,Mvm64n
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_91_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3620] // VPGATHERDQ Vfv{K},aKq,Mvm32h
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3618] // VPGATHERDD Vfv{K},aKq,Mvm32n
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_90_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3858] // VPSHUFBITQMB rK{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3595] // VPERMW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3558] // VPERMB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3514] // VPCOMPRESSQ Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3513] // VPCOMPRESSD Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2759] // VCOMPRESSPD Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2760] // VCOMPRESSPS Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3598] // VPEXPANDQ Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3597] // VPEXPANDD Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_89_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_89_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2929] // VEXPANDPD Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2930] // VEXPANDPS Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_88_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_88_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_83_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3790] // VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_83_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_83_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_83_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_83_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3591] // VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3592] // VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3593] // VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3590] // VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3594] // VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3589] // VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3473] // VPBROADCASTQ Vfv{K}{z},aKq,Rq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3468] // VPBROADCASTD Vfv{K}{z},aKq,Rd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3476] // VPBROADCASTW Vfv{K}{z},aKq,Rw
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3465] // VPBROADCASTB Vfv{K}{z},aKq,Rb
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3475] // VPBROADCASTW Vfv{K}{z},aKq,Ww
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_79_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_79_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_79_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3464] // VPBROADCASTB Vfv{K}{z},aKq,Wb
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_78_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_78_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_78_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3563] // VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3564] // VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_77_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_77_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3565] // VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3562] // VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_76_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_76_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3566] // VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3561] // VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_75_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_75_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_74_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2777] // VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_74_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_74_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2788] // VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_74_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_74_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2766] // VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_74_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_74_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3853] // VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3852] // VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_73_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_73_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2781] // VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2792] // VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3854] // VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_72_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3844] // VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3843] // VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_71_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_71_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_70_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3845] // VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_70_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_70_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_70_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_70_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2607] // TCVTROWPS2PBF16H Voq,mTt,Bd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2609] // TCVTROWPS2PBF16L Voq,mTt,Bd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2613] // TCVTROWPS2PHL Voq,mTt,Bd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2611] // TCVTROWPS2PHH Voq,mTt,Bd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_6d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3411] // VP2INTERSECTQ rKq+1,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3410] // VP2INTERSECTD rKq+1,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_68_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp_03_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_68_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_67_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2765] // VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_67_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_67_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_67_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_67_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3461] // VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3458] // VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_66_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_66_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2721] // VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2722] // VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_65_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_65_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3460] // VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3459] // VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_64_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_64_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3515] // VPCOMPRESSW Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3512] // VPCOMPRESSB Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_63_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_63_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3599] // VPEXPANDW Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3596] // VPEXPANDB Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_62_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_62_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2738] // VBROADCASTI64X4 Voq{K}{z},aKq,Mqq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2736] // VBROADCASTI32X8 Voq{K}{z},aKq,Mqq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2737] // VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2735] // VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3472] // VPBROADCASTQ Vfv{K}{z},aKq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2734] // VBROADCASTI32X2 Vfv{K}{z},aKq,Wq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_59_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_59_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3467] // VPBROADCASTD Vfv{K}{z},aKq,Wd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_58_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_58_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_58_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3795] // VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3794] // VPOPCNTD Vfv{K}{z},aKq,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_55_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_55_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3796] // VPOPCNTW Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3793] // VPOPCNTB Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_54_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_54_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3413] // VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3542] // VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_53_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3412] // VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2921] // VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3540] // VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2923] // VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_52_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3526] // VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3530] // VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3534] // VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3538] // VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_51_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3524] // VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3528] // VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3532] // VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3536] // VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_50_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4003] // VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4004] // VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4001] // VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4002] // VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3972] // VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3973] // VRCP14SS Vdq{K}{z},aKq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3970] // VRCP14PD Vfv{K}{z},aKq,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3971] // VRCP14PS Vfv{K}{z},aKq,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2635] // TILELOADD rTt,Mt
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_RM gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2644] // TILESTORED Mt,rTt
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_RM gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2639] // TILELOADDT1 rTt,Mt
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_RM gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2605] // TCVTROWD2PS Voq,mTt,Bd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2641] // TILEMOVROW Voq,mTt,Bd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2526] // STTILECFG Moq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1305] // LDTILECFG Moq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_49_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3880] // VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3878] // VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_47_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_47_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3895] // VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3893] // VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_46_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_46_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3913] // VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3911] // VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_45_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_45_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3661] // VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3660] // VPLZCNTD Vfv{K}{z},aKq,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_44_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_44_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3190] // VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3192] // VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_43_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_43_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3187] // VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3189] // VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_42_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_42_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3787] // VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3785] // VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_40_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_40_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3697] // VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3695] // VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3e_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3698] // VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3e_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3690] // VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3688] // VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3686] // VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3c_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3711] // VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3709] // VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3471] // VPBROADCASTMW2D Vfv,mKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3712] // VPMINUW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3723] // VPMOVQ2M rKq,Ufv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3715] // VPMOVD2M rKq,Ufv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3704] // VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3702] // VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_39_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3720] // VPMOVM2Q Vfv,mKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3719] // VPMOVM2D Vfv,mKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3700] // VPMINSB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_38_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_37_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3498] // VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_37_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_37_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_37_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_37_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3586] // VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3559] // VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_36_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_36_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3725] // VPMOVQD Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3768] // VPMOVZXDQ Vfv{K}{z},aKq,Whv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_35_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3726] // VPMOVQW Wqv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_34_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3774] // VPMOVZXWQ Vfv{K}{z},aKq,Wqv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_34_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3717] // VPMOVDW Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_33_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3771] // VPMOVZXWD Vfv{K}{z},aKq,Whv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_33_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3724] // VPMOVQB Wev{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_32_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3762] // VPMOVZXBQ Vfv{K}{z},aKq,Wev
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_32_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3716] // VPMOVDB Wqv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_31_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3759] // VPMOVZXBD Vfv{K}{z},aKq,Wqv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_31_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3758] // VPMOVWB Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_30_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3765] // VPMOVZXBW Vfv{K}{z},aKq,Whv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_30_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4018] // VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4020] // VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4015] // VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4017] // VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3425] // VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3470] // VPBROADCASTMB2Q Vfv,mKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3328] // VMOVNTDQA Vfv,Mfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3757] // VPMOVW2M rKq,Ufv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3714] // VPMOVB2M rKq,Ufv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3488] // VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_29_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3721] // VPMOVM2W Vfv,mKq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3718] // VPMOVM2B Vfv,mKq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3777] // VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_28_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3945] // VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3944] // VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3941] // VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3940] // VPTESTMD rKq{K},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_27_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3946] // VPTESTNMW rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3943] // VPTESTNMB rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3942] // VPTESTMW rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3939] // VPTESTMB rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_26_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3730] // VPMOVSQD Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3742] // VPMOVSXDQ Vfv{K}{z},aKq,Whv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_25_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3731] // VPMOVSQW Wqv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_24_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3748] // VPMOVSXWQ Vfv{K}{z},aKq,Wqv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_24_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3728] // VPMOVSDW Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_23_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3745] // VPMOVSXWD Vfv{K}{z},aKq,Whv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_23_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3729] // VPMOVSQB Wev{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_22_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3736] // VPMOVSXBQ Vfv{K}{z},aKq,Wev
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_22_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3727] // VPMOVSDB Wqv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_21_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3733] // VPMOVSXBD Vfv{K}{z},aKq,Wqv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_21_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3732] // VPMOVSWB Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_20_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3739] // VPMOVSXBW Vfv{K}{z},aKq,Whv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_20_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp_01_leaf,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3418] // VPABSQ Vfv{K}{z},aKq,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3416] // VPABSD Vfv{K}{z},aKq,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1d_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3419] // VPABSW Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1d_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3414] // VPABSB Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1c_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2732] // VBROADCASTF64X4 Voq{K}{z},aKq,Mqq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2730] // VBROADCASTF32X8 Voq{K}{z},aKq,Mqq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2731] // VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2729] // VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2739] // VBROADCASTSD Vuv{K}{z},aKq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2728] // VBROADCASTF32X2 Vuv{K}{z},aKq,Wq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_19_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_19_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2741] // VBROADCASTSS Vfv{K}{z},aKq,Wss
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_18_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_18_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_18_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3580] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3584] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3579] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3583] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_16_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_16_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3754] // VPMOVUSQD Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3805] // VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3804] // VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_15_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3755] // VPMOVUSQW Wqv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3809] // VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3808] // VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_14_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3752] // VPMOVUSDW Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2807] // VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_13_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3753] // VPMOVUSQB Wev{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3882] // VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_12_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3751] // VPMOVUSDB Wqv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3896] // VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_11_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3756] // VPMOVUSWB Whv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3915] // VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_10_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3571] // VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3575] // VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0b_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3779] // VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0b_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_04_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3678] // VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_04_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_04_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_00_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3856] // VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_00_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_00_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_00_pp,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_04_pp,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)&gEvexMap_mmmmm_02_opcode_0b_pp,
+ /* 0c */ (const void *)&gEvexMap_mmmmm_02_opcode_0c_pp,
+ /* 0d */ (const void *)&gEvexMap_mmmmm_02_opcode_0d_pp,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp,
+ /* 11 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp,
+ /* 12 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp,
+ /* 13 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp,
+ /* 14 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp,
+ /* 15 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp,
+ /* 16 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)&gEvexMap_mmmmm_02_opcode_18_pp,
+ /* 19 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp,
+ /* 1a */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp,
+ /* 1b */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp,
+ /* 1c */ (const void *)&gEvexMap_mmmmm_02_opcode_1c_pp,
+ /* 1d */ (const void *)&gEvexMap_mmmmm_02_opcode_1d_pp,
+ /* 1e */ (const void *)&gEvexMap_mmmmm_02_opcode_1e_pp,
+ /* 1f */ (const void *)&gEvexMap_mmmmm_02_opcode_1f_pp,
+ /* 20 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp,
+ /* 21 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp,
+ /* 22 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp,
+ /* 23 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp,
+ /* 24 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp,
+ /* 25 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp,
+ /* 26 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp,
+ /* 27 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp,
+ /* 28 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp,
+ /* 29 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp,
+ /* 2a */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp,
+ /* 2b */ (const void *)&gEvexMap_mmmmm_02_opcode_2b_pp,
+ /* 2c */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp,
+ /* 2d */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp,
+ /* 31 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp,
+ /* 32 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp,
+ /* 33 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp,
+ /* 34 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp,
+ /* 35 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp,
+ /* 36 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp,
+ /* 37 */ (const void *)&gEvexMap_mmmmm_02_opcode_37_pp,
+ /* 38 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp,
+ /* 39 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp,
+ /* 3a */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp,
+ /* 3b */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp,
+ /* 3c */ (const void *)&gEvexMap_mmmmm_02_opcode_3c_pp,
+ /* 3d */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp,
+ /* 3e */ (const void *)&gEvexMap_mmmmm_02_opcode_3e_pp,
+ /* 3f */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp,
+ /* 40 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp,
+ /* 43 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp,
+ /* 44 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp,
+ /* 45 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp,
+ /* 46 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp,
+ /* 47 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp,
+ /* 4a */ (const void *)&gEvexMap_mmmmm_02_opcode_4a_pp,
+ /* 4b */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp,
+ /* 4c */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp,
+ /* 4d */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp,
+ /* 4e */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp,
+ /* 4f */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp,
+ /* 50 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp,
+ /* 51 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp,
+ /* 52 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp,
+ /* 53 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp,
+ /* 54 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp,
+ /* 55 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)&gEvexMap_mmmmm_02_opcode_58_pp,
+ /* 59 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp,
+ /* 5a */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp,
+ /* 5b */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp,
+ /* 63 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp,
+ /* 64 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp,
+ /* 65 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp,
+ /* 66 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp,
+ /* 67 */ (const void *)&gEvexMap_mmmmm_02_opcode_67_pp,
+ /* 68 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)&gEvexMap_mmmmm_02_opcode_6d_pp,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)&gEvexMap_mmmmm_02_opcode_70_pp,
+ /* 71 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp,
+ /* 72 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp,
+ /* 73 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp,
+ /* 74 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp,
+ /* 75 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp,
+ /* 76 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp,
+ /* 77 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp,
+ /* 78 */ (const void *)&gEvexMap_mmmmm_02_opcode_78_pp,
+ /* 79 */ (const void *)&gEvexMap_mmmmm_02_opcode_79_pp,
+ /* 7a */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp,
+ /* 7b */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp,
+ /* 7c */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp,
+ /* 7d */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp,
+ /* 7e */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp,
+ /* 7f */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)&gEvexMap_mmmmm_02_opcode_83_pp,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp,
+ /* 89 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp,
+ /* 8a */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp,
+ /* 8b */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)&gEvexMap_mmmmm_02_opcode_8f_pp,
+ /* 90 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp,
+ /* 91 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp,
+ /* 92 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp,
+ /* 93 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp,
+ /* 97 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp,
+ /* 98 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp,
+ /* 99 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp,
+ /* 9a */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp,
+ /* 9b */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp,
+ /* 9c */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp,
+ /* 9d */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp,
+ /* 9e */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp,
+ /* 9f */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp,
+ /* a0 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp,
+ /* a1 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp,
+ /* a2 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp,
+ /* a3 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp,
+ /* a7 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp,
+ /* a8 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp,
+ /* a9 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp,
+ /* aa */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp,
+ /* ab */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp,
+ /* ac */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp,
+ /* ad */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp,
+ /* ae */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp,
+ /* af */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)&gEvexMap_mmmmm_02_opcode_b4_pp,
+ /* b5 */ (const void *)&gEvexMap_mmmmm_02_opcode_b5_pp,
+ /* b6 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp,
+ /* b7 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp,
+ /* b8 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp,
+ /* b9 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp,
+ /* ba */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp,
+ /* bb */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp,
+ /* bc */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp,
+ /* bd */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp,
+ /* be */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp,
+ /* bf */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp,
+ /* c7 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp,
+ /* c8 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp,
+ /* cb */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp,
+ /* cc */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp,
+ /* cd */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)&gEvexMap_mmmmm_02_opcode_cf_pp,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp,
+ /* d3 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)&gEvexMap_mmmmm_02_opcode_da_pp,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)&gEvexMap_mmmmm_02_opcode_dc_pp,
+ /* dd */ (const void *)&gEvexMap_mmmmm_02_opcode_dd_pp,
+ /* de */ (const void *)&gEvexMap_mmmmm_02_opcode_de_pp,
+ /* df */ (const void *)&gEvexMap_mmmmm_02_opcode_df_pp,
+ /* e0 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp,
+ /* e1 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp,
+ /* e2 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp,
+ /* e3 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp,
+ /* e4 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp,
+ /* e5 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp,
+ /* e6 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp,
+ /* e7 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp,
+ /* e8 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp,
+ /* e9 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp,
+ /* ea */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp,
+ /* eb */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp,
+ /* ec */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp,
+ /* ed */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp,
+ /* ee */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp,
+ /* ef */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp,
+ /* f3 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp,
+ /* f6 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp,
+ /* f7 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fe_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3431] // VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fe_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_fe_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fe_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fe_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fd_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3443] // VPADDW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fd_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fc_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3429] // VPADDB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fc_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fb_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3924] // VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fb_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fb_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fb_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fa_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3922] // VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fa_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_fa_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fa_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fa_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f9_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3934] // VPSUBW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f9_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f8_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3920] // VPSUBB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f8_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f6_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3822] // VPSADBW Vfv,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f6_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f5_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3680] // VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f5_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f4_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3791] // VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f4_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f4_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f4_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f3_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3875] // VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f3_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f3_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f3_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f2_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3869] // VPSLLD Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f2_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_f2_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f2_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f1_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3884] // VPSLLW Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f1_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3965] // VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3964] // VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_ef_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ef_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ee_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3691] // VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ee_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ee_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ed_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3437] // VPADDSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ed_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ed_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ec_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3435] // VPADDSB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ec_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ec_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3799] // VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3798] // VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_eb_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_eb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ea_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3705] // VPMINSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ea_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ea_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e9_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3928] // VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e9_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e8_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3926] // VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e8_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3326] // VMOVNTDQ Mfv,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2794] // VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2830] // VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2770] // VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2857] // VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e5_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3783] // VPMULHW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e5_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e4_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3781] // VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e4_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e3_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3455] // VPAVGW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e3_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3892] // VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3888] // VPSRAD Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e2_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e1_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3898] // VPSRAW Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e1_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e0_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3453] // VPAVGB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e0_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3451] // VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3450] // VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_df_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_df_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_de_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3693] // VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_de_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_de_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dd_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3441] // VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_dd_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dc_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3439] // VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_dc_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3452] // VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3448] // VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_db_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_db_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_da_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3707] // VPMINUB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_da_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_da_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d9_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3932] // VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d9_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d8_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3930] // VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d8_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3337] // VMOVQ Wq,Vdq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3280] // VMOVD Wd,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_d6_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d5_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3788] // VPMULLW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d5_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d4_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3433] // VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d4_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d4_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d4_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d3_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3908] // VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d3_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d3_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d3_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d2_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3902] // VPSRLD Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d2_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_d2_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d2_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d1_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3917] // VPSRLW Vfv{K}{z},aKq,Hfv,Wdq
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d1_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4040] // VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4042] // VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3612] // VPEXTRW Gy,Udq,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3657] // VPINSRW Vdq,Hdq,Rv,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3656] // VPINSRW Vdq,Hdq,Mw,Ib
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2749] // VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2752] // VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2744] // VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2747] // VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1248] // KMOVQ Gy,mKq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1238] // KMOVD Gy,mKd
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1228] // KMOVB Gy,mKb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1258] // KMOVW Gy,mKw
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_93_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1247] // KMOVQ rKq,Ry
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1237] // KMOVD rKd,Ry
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1227] // KMOVB rKb,Ry
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1257] // KMOVW rKw,Ry
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_92_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1236] // KMOVD Md,rKd
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1226] // KMOVB Mb,rKb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1246] // KMOVQ Mq,rKq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1256] // KMOVW Mw,rKw
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_91_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1235] // KMOVD rKd,mKd
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1225] // KMOVB rKb,mKb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1234] // KMOVD rKd,Md
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1224] // KMOVB rKb,Mb
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1245] // KMOVQ rKq,mKq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1255] // KMOVW rKw,mKw
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1244] // KMOVQ rKq,Mq
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1254] // KMOVW rKw,Mw
+};
+
+const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf =
+{
+ ND_ILUT_EX_NF,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_90_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3297] // VMOVDQU16 Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3303] // VMOVDQU8 Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_03_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3301] // VMOVDQU64 Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3299] // VMOVDQU32 Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3293] // VMOVDQA64 Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3291] // VMOVDQA32 Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3336] // VMOVQ Vdq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3279] // VMOVD Vdq,Wd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_7e_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3335] // VMOVQ Ey,Vdq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3278] // VMOVD Ey,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_7e_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2904] // VCVTUSI2SD Vdq,Hdq{er},Ey
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2903] // VCVTUSI2SD Vdq,Hdq,Ey
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_03_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2906] // VCVTUSI2SS Vss,Hss{er},Ey
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2800] // VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2827] // VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_03_wi,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2902] // VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2899] // VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_03_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2900] // VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2897] // VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2860] // VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2879] // VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2838] // VCVTSD2USI Gy,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2854] // VCVTSS2USI Gy,Wss{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2802] // VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2829] // VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2801] // VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2828] // VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_79_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2888] // VCVTTSD2USI Gy,Wsd{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2895] // VCVTTSS2USI Gy,Wss{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2864] // VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2883] // VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2862] // VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2881] // VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_78_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_76_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3486] // VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_76_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_76_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_75_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3490] // VPCMPEQW rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_75_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_75_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3484] // VPCMPEQB rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_74_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3872] // VPSLLDQ Hfv,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3874] // VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3905] // VPSRLDQ Hfv,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3907] // VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_73_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3868] // VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3891] // VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3887] // VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3901] // VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3803] // VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3802] // VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3807] // VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3806] // VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_72_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3883] // VPSLLW Hfv{K}{z},aKq,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3897] // VPSRAW Hfv{K}{z},aKq,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3916] // VPSRLW Hfv{K}{z},aKq,Wfv,Ib
+};
+
+const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_71_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3863] // VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3861] // VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3859] // VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_70_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_70_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3296] // VMOVDQU16 Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3302] // VMOVDQU8 Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_03_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3300] // VMOVDQU64 Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3298] // VMOVDQU32 Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_02_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3292] // VMOVDQA64 Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3290] // VMOVDQA32 Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3334] // VMOVQ Vdq,Eq
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3277] // VMOVD Vdq,Ed
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_6e_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3951] // VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3959] // VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3421] // VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3949] // VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_69_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3953] // VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_69_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_69_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_68_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3947] // VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_68_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_68_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_67_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3427] // VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_67_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_67_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_66_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3496] // VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_66_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_66_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_66_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_66_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_65_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3500] // VPCMPGTW rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_65_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_65_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_64_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3494] // VPCMPGTB rKq{K},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_64_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_64_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_63_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3423] // VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_63_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_63_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_62_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3957] // VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_62_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_62_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_62_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_62_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_61_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3961] // VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_61_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_61_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_60_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3955] // VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_60_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_60_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3237] // VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3240] // VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3232] // VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3235] // VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2916] // VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2919] // VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2911] // VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2914] // VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3260] // VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3263] // VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3255] // VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3258] // VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4069] // VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4072] // VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4064] // VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4067] // VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2874] // VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2816] // VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2832] // VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2774] // VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_00_w_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2836] // VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2849] // VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2797] // VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2820] // VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3398] // VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3401] // VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3393] // VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3396] // VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_59_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2692] // VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2695] // VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2687] // VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2690] // VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_58_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4092] // VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4094] // VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_57_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3406] // VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3408] // VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_56_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2711] // VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2713] // VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_55_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2715] // VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2717] // VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_54_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4057] // VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4060] // VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4052] // VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4055] // VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_51_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2762] // VCOMXSD Vdq,Wsd{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2764] // VCOMXSS Vdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2754] // VCOMISD Vdq,Wsd{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2757] // VCOMISS Vdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_03_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4081] // VUCOMXSD Vdq,Wsd{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4083] // VUCOMXSS Vdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4076] // VUCOMISD Vdq,Wsd{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4079] // VUCOMISS Vdq,Wss{sae}
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2834] // VCVTSD2SI Gy,Wsd{er}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2852] // VCVTSS2SI Gy,Wss{er}
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2d_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2d_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2885] // VCVTTSD2SI Gy,Wsd{sae}
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2892] // VCVTTSS2SI Gy,Wss{sae}
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2c_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2c_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3330] // VMOVNTPD Mfv,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3332] // VMOVNTPS Mfv,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2844] // VCVTSI2SD Vdq,Hdq{er},Ey
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2843] // VCVTSI2SD Vdq,Hdq,Ey
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2a_pp_03_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_00_leaf,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2847] // VCVTSI2SS Vdq,Hdq{er},Ey
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_02_leaf,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_03_wi,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3270] // VMOVAPD Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3274] // VMOVAPS Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_29_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3269] // VMOVAPD Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3273] // VMOVAPS Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_28_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3307] // VMOVHPD Mq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3311] // VMOVHPS Mq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_17_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3358] // VMOVSHDUP Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3306] // VMOVHPD Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3314] // VMOVLHPS Vdq,Hdq,Udq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3310] // VMOVHPS Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_16_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4084] // VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4086] // VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_15_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4088] // VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4090] // VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_14_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3317] // VMOVLPD Mq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3321] // VMOVLPS Mq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_13_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3285] // VMOVDDUP Voq{K}{z},aKq,Woq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3284] // VMOVDDUP Vqq{K}{z},aKq,Wqq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3283] // VMOVDDUP Vdq{K}{z},aKq,Wq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3360] // VMOVSLDUP Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3316] // VMOVLPD Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3304] // VMOVHLPS Vdq,Hdq,Udq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3320] // VMOVLPS Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_12_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_02_w,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3349] // VMOVSD Udq{K}{z},aKq,Hdq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3348] // VMOVSD Msd{K},aKq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3365] // VMOVSS Udq{K}{z},aKq,Hdq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3364] // VMOVSS Mss{K},aKq,Vdq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3371] // VMOVUPD Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3375] // VMOVUPS Wfv{K}{z},aKq,Vfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_11_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3347] // VMOVSD Vdq{K}{z},aKq,Hdq,Udq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3346] // VMOVSD Vdq{K}{z},aKq,Msd
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3363] // VMOVSS Vdq{K}{z},aKq,Hdq,Udq
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3362] // VMOVSS Vdq{K}{z},aKq,Mss
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3370] // VMOVUPD Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3374] // VMOVUPS Vfv{K}{z},aKq,Wfv
+};
+
+const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_10_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_00_w,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_01_w,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_OPCODE gEvexMap_mmmmm_01_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp,
+ /* 11 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp,
+ /* 12 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp,
+ /* 13 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp,
+ /* 14 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp,
+ /* 15 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp,
+ /* 16 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp,
+ /* 17 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp,
+ /* 29 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp,
+ /* 2a */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp,
+ /* 2b */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp,
+ /* 2c */ (const void *)&gEvexMap_mmmmm_01_opcode_2c_pp,
+ /* 2d */ (const void *)&gEvexMap_mmmmm_01_opcode_2d_pp,
+ /* 2e */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp,
+ /* 2f */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp,
+ /* 55 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp,
+ /* 56 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp,
+ /* 57 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp,
+ /* 58 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp,
+ /* 59 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp,
+ /* 5a */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp,
+ /* 5b */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp,
+ /* 5c */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp,
+ /* 5d */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp,
+ /* 5e */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp,
+ /* 5f */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp,
+ /* 60 */ (const void *)&gEvexMap_mmmmm_01_opcode_60_pp,
+ /* 61 */ (const void *)&gEvexMap_mmmmm_01_opcode_61_pp,
+ /* 62 */ (const void *)&gEvexMap_mmmmm_01_opcode_62_pp,
+ /* 63 */ (const void *)&gEvexMap_mmmmm_01_opcode_63_pp,
+ /* 64 */ (const void *)&gEvexMap_mmmmm_01_opcode_64_pp,
+ /* 65 */ (const void *)&gEvexMap_mmmmm_01_opcode_65_pp,
+ /* 66 */ (const void *)&gEvexMap_mmmmm_01_opcode_66_pp,
+ /* 67 */ (const void *)&gEvexMap_mmmmm_01_opcode_67_pp,
+ /* 68 */ (const void *)&gEvexMap_mmmmm_01_opcode_68_pp,
+ /* 69 */ (const void *)&gEvexMap_mmmmm_01_opcode_69_pp,
+ /* 6a */ (const void *)&gEvexMap_mmmmm_01_opcode_6a_pp,
+ /* 6b */ (const void *)&gEvexMap_mmmmm_01_opcode_6b_pp,
+ /* 6c */ (const void *)&gEvexMap_mmmmm_01_opcode_6c_pp,
+ /* 6d */ (const void *)&gEvexMap_mmmmm_01_opcode_6d_pp,
+ /* 6e */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp,
+ /* 6f */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp,
+ /* 70 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp,
+ /* 71 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp,
+ /* 72 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp,
+ /* 73 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp,
+ /* 74 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp,
+ /* 75 */ (const void *)&gEvexMap_mmmmm_01_opcode_75_pp,
+ /* 76 */ (const void *)&gEvexMap_mmmmm_01_opcode_76_pp,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp,
+ /* 79 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp,
+ /* 7a */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp,
+ /* 7b */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp,
+ /* 7f */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp,
+ /* 91 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp,
+ /* 92 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp,
+ /* 93 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp,
+ /* c5 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp,
+ /* c6 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)&gEvexMap_mmmmm_01_opcode_d1_pp,
+ /* d2 */ (const void *)&gEvexMap_mmmmm_01_opcode_d2_pp,
+ /* d3 */ (const void *)&gEvexMap_mmmmm_01_opcode_d3_pp,
+ /* d4 */ (const void *)&gEvexMap_mmmmm_01_opcode_d4_pp,
+ /* d5 */ (const void *)&gEvexMap_mmmmm_01_opcode_d5_pp,
+ /* d6 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)&gEvexMap_mmmmm_01_opcode_d8_pp,
+ /* d9 */ (const void *)&gEvexMap_mmmmm_01_opcode_d9_pp,
+ /* da */ (const void *)&gEvexMap_mmmmm_01_opcode_da_pp,
+ /* db */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp,
+ /* dc */ (const void *)&gEvexMap_mmmmm_01_opcode_dc_pp,
+ /* dd */ (const void *)&gEvexMap_mmmmm_01_opcode_dd_pp,
+ /* de */ (const void *)&gEvexMap_mmmmm_01_opcode_de_pp,
+ /* df */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp,
+ /* e0 */ (const void *)&gEvexMap_mmmmm_01_opcode_e0_pp,
+ /* e1 */ (const void *)&gEvexMap_mmmmm_01_opcode_e1_pp,
+ /* e2 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp,
+ /* e3 */ (const void *)&gEvexMap_mmmmm_01_opcode_e3_pp,
+ /* e4 */ (const void *)&gEvexMap_mmmmm_01_opcode_e4_pp,
+ /* e5 */ (const void *)&gEvexMap_mmmmm_01_opcode_e5_pp,
+ /* e6 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp,
+ /* e7 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp,
+ /* e8 */ (const void *)&gEvexMap_mmmmm_01_opcode_e8_pp,
+ /* e9 */ (const void *)&gEvexMap_mmmmm_01_opcode_e9_pp,
+ /* ea */ (const void *)&gEvexMap_mmmmm_01_opcode_ea_pp,
+ /* eb */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp,
+ /* ec */ (const void *)&gEvexMap_mmmmm_01_opcode_ec_pp,
+ /* ed */ (const void *)&gEvexMap_mmmmm_01_opcode_ed_pp,
+ /* ee */ (const void *)&gEvexMap_mmmmm_01_opcode_ee_pp,
+ /* ef */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)&gEvexMap_mmmmm_01_opcode_f1_pp,
+ /* f2 */ (const void *)&gEvexMap_mmmmm_01_opcode_f2_pp,
+ /* f3 */ (const void *)&gEvexMap_mmmmm_01_opcode_f3_pp,
+ /* f4 */ (const void *)&gEvexMap_mmmmm_01_opcode_f4_pp,
+ /* f5 */ (const void *)&gEvexMap_mmmmm_01_opcode_f5_pp,
+ /* f6 */ (const void *)&gEvexMap_mmmmm_01_opcode_f6_pp,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)&gEvexMap_mmmmm_01_opcode_f8_pp,
+ /* f9 */ (const void *)&gEvexMap_mmmmm_01_opcode_f9_pp,
+ /* fa */ (const void *)&gEvexMap_mmmmm_01_opcode_fa_pp,
+ /* fb */ (const void *)&gEvexMap_mmmmm_01_opcode_fb_pp,
+ /* fc */ (const void *)&gEvexMap_mmmmm_01_opcode_fc_pp,
+ /* fd */ (const void *)&gEvexMap_mmmmm_01_opcode_fd_pp,
+ /* fe */ (const void *)&gEvexMap_mmmmm_01_opcode_fe_pp,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_M gEvexMap_mmmmm =
+{
+ ND_ILUT_EX_M,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode,
+ /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode,
+ /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode,
+ /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode,
+ /* 05 */ (const void *)&gEvexMap_mmmmm_05_opcode,
+ /* 06 */ (const void *)&gEvexMap_mmmmm_06_opcode,
+ /* 07 */ (const void *)&gEvexMap_mmmmm_07_opcode,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ }
+};
+
+
+#endif
+
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_root.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_root.h
new file mode 100644
index 00000000000000..8e7071101691ce
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_root.h
@@ -0,0 +1,16886 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_TABLE_ROOT_H
+#define BDX86_TABLE_ROOT_H
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1969] // PUSH Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1184] // JMPF Mp
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1179] // JMP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 243] // CALLF Mp
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 241] // CALL Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 873] // DEC Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1137] // INC Ev
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_ff_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fe_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 872] // DEC Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fe_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1136] // INC Eb
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_fe_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_fe_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_fe_modrmreg_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fd_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2512] // STD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fc_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 553] // CLD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2514] // STI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fa_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 560] // CLI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2511] // STC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f8_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 552] // CLC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1076] // IDIV Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 882] // DIV Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1110] // IMUL Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1480] // MUL Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1502] // NEG Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1581] // NOT Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2633] // TEST Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2632] // TEST Ev,Iz
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_f7_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1075] // IDIV Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 881] // DIV Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1109] // IMUL Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1479] // MUL Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1501] // NEG Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1580] // NOT Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2631] // TEST Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2630] // TEST Eb,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_f6_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f5_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 566] // CMC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f4_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1065] // HLT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1151] // INT1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ef_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1641] // OUT DX,eAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ee_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1640] // OUT DX,AL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ed_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1115] // IN eAX,DX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ec_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1114] // IN AL,DX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_eb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1178] // JMP Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ea_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1183] // JMPF Ap
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1177] // JMP Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e8_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 240] // CALL Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1639] // OUT Ib,eAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1638] // OUT Ib,AL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e5_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1113] // IN eAX,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e4_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1112] // IN AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1205] // JRCXZ Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1172] // JECXZ Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1171] // JCXZ Jb
+};
+
+const ND_TABLE_ASIZE gLegacyMap_opcode_e3_asize =
+{
+ ND_ILUT_ASIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_e3_asize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_e3_asize_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_e3_asize_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1329] // LOOP Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1331] // LOOPZ Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1330] // LOOPNZ Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1013] // FRINEAR
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 972] // FISTP Mq,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 930] // FCOMIP ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 915] // FBSTP Mfa,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1045] // FUCOMIP ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 964] // FILD ST(0),Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1031] // FSTSG AX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1023] // FSTDW AX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1008] // FNSTSW AX
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 914] // FBLD ST(0),Mfa
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1029] // FSTP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 971] // FISTP Mw,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1028] // FSTP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 969] // FIST Mw,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1051] // FXCH ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 975] // FISTTP Mw,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 951] // FFREEP ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 963] // FILD ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_df_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_df_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_df_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_df_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_df_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 943] // FDIVP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 961] // FIDIVR ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 948] // FDIVRP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 959] // FIDIV ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1036] // FSUBP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 979] // FISUBR ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1041] // FSUBRP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 977] // FISUB ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 936] // FCOMPP
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 957] // FICOMP ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 935] // FCOMP ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 955] // FICOM ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 997] // FMULP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 966] // FIMUL ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 913] // FADDP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 953] // FIADD ST(0),Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_de_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_de_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_de_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_de_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_de_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_de_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1007] // FNSTSW Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1004] // FNSAVE Mfs
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1046] // FUCOMP ST(0),ST(i)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1043] // FUCOM ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1015] // FRSTOR Mfs
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1027] // FSTP ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1026] // FSTP Mfq,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1022] // FST ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1021] // FST Mfq,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1050] // FXCH ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 974] // FISTTP Mq,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 950] // FFREE ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 983] // FLD ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_dd_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 942] // FDIV ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 946] // FDIVR ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 947] // FDIVR ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 941] // FDIV ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1035] // FSUB ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1039] // FSUBR ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1040] // FSUBR ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1034] // FSUB ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 934] // FCOMP ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 933] // FCOMP ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 928] // FCOM ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 927] // FCOM ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 996] // FMUL ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 995] // FMUL ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 912] // FADD ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 911] // FADD ST(0),Mfq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_dc_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1025] // FSTP Mft,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 929] // FCOMI ST(0),ST(i)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1044] // FUCOMI ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 982] // FLD ST(0),Mft
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1003] // FNOP
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1000] // FNINIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 998] // FNCLEX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 999] // FNDISI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1002] // FNOP
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 923] // FCMOVNU ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 970] // FISTP Md,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 921] // FCMOVNBE ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 968] // FIST Md,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 922] // FCMOVNE ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 973] // FISTTP Md,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 920] // FCMOVNB ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 962] // FILD ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_db_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_db_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_db_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_db_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_db_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_db_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 960] // FIDIVR ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 958] // FIDIV ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1047] // FUCOMPP
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 978] // FISUBR ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 976] // FISUB ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 924] // FCMOVU ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 956] // FICOMP ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 918] // FCMOVBE ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 954] // FICOM ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 919] // FCMOVE ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 965] // FIMUL ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 917] // FCMOVB ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 952] // FIADD ST(0),Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_da_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_da_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_da_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_da_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_da_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_da_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 937] // FCOS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1017] // FSIN
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1016] // FSCALE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1014] // FRNDINT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1018] // FSINCOS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1019] // FSQRT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1058] // FYL2XP1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1010] // FPREM
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1005] // FNSTCW Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 967] // FINCSTP
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 938] // FDECSTP
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1011] // FPREM1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1056] // FXTRACT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1009] // FPATAN
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1012] // FPTAN
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1057] // FYL2X
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 907] // F2XM1
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1006] // FNSTENV Mfe
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 992] // FLDZ
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 990] // FLDLN2
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 989] // FLDLG2
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 991] // FLDPI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 987] // FLDL2E
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 988] // FLDL2T
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 984] // FLD1
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 985] // FLDCW Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1048] // FXAM
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1042] // FTST
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 908] // FABS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 916] // FCHS
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 986] // FLDENV Mfe
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1030] // FSTPNCE ST(i),ST(0)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1024] // FSTP Mfd,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1001] // FNOP
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1020] // FST Mfd,ST(0)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1049] // FXCH ST(0),ST(i)
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 981] // FLD ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 980] // FLD ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_d9_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 945] // FDIVR ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 944] // FDIVR ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 940] // FDIV ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 939] // FDIV ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1038] // FSUBR ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1037] // FSUBR ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1033] // FSUB ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1032] // FSUB ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 932] // FCOMP ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 931] // FCOMP ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 926] // FCOM ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 925] // FCOM ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 994] // FMUL ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 993] // FMUL ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 910] // FADD ST(0),ST(i)
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 909] // FADD ST(0),Mfd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_d8_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4133] // XLATB
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2239] // SALC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d5_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1] // AAD Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d4_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4] // AAM Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2281] // SAR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2238] // SAL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2475] // SHR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2413] // SHL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2075] // RCR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2031] // RCL Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2185] // ROR Ev,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2143] // ROL Ev,CL
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_d3_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2280] // SAR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2237] // SAL Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2474] // SHR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2412] // SHL Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2074] // RCR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2030] // RCL Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2184] // ROR Eb,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2142] // ROL Eb,CL
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_d2_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2279] // SAR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2236] // SAL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2473] // SHR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2411] // SHL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2073] // RCR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2029] // RCL Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2183] // ROR Ev,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2141] // ROL Ev,1
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_d1_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2278] // SAR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2235] // SAL Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2472] // SHR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2410] // SHL Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2072] // RCR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2028] // RCL Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2182] // ROR Eb,1
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2140] // ROL Eb,1
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_d0_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1165] // IRETQ
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1164] // IRETD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1166] // IRETW
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_cf_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_cf_dsize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_cf_dsize_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_cf_dsize_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ce_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1153] // INTO
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cd_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1150] // INT Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cc_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1152] // INT3
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2095] // RETF
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ca_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2094] // RETF Iw
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1308] // LEAVE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c8_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 901] // ENTER Iw,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4120] // XBEGIN Jz
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c7_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c7_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1386] // MOV Ev,Iz
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_c7_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4117] // XABORT Ib
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c6_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c6_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1385] // MOV Eb,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_c6_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c5_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1304] // LDS Gz,Mp
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c5_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c5_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c4_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1309] // LES Gz,Mp
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c4_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c4_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2097] // RETN
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2096] // RETN Iw
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2277] // SAR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2234] // SAL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2471] // SHR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2409] // SHL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2071] // RCR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2027] // RCL Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2181] // ROR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2139] // ROL Ev,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_c1_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2276] // SAR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2233] // SAL Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2470] // SHR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2408] // SHL Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2070] // RCR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2026] // RCL Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2180] // ROR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2138] // ROL Eb,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_c0_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bf_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1384] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_be_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1383] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bd_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1382] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bc_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1381] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1380] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ba_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1379] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1378] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b8_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1377] // MOV Zv,Iv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1376] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1375] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b5_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1374] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b4_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1373] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1372] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1371] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1370] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1369] // MOV Zb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2322] // SCASQ RAX,Yv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2321] // SCASQ RAX,Yv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_03_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_af_dsize_03_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_af_dsize_03_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2320] // SCASD EAX,Yv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2319] // SCASD EAX,Yv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_02_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_af_dsize_02_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_af_dsize_02_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2324] // SCASW AX,Yv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2323] // SCASW AX,Yv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_af_dsize_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_af_dsize_01_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_af_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_af_dsize_01_auxiliary,
+ /* 02 */ (const void *)&gLegacyMap_opcode_af_dsize_02_auxiliary,
+ /* 03 */ (const void *)&gLegacyMap_opcode_af_dsize_03_auxiliary,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2318] // SCASB AL,Yb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2317] // SCASB AL,Yb
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ae_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ae_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ae_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_03_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1326] // LODSQ RAX,Xv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_03_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1325] // LODSQ RAX,Xv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_03_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ad_dsize_03_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ad_dsize_03_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_02_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1324] // LODSD EAX,Xv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_02_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1323] // LODSD EAX,Xv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_02_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ad_dsize_02_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ad_dsize_02_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_01_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1328] // LODSW AX,Xv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1327] // LODSW AX,Xv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ad_dsize_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ad_dsize_01_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_ad_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_ad_dsize_01_auxiliary,
+ /* 02 */ (const void *)&gLegacyMap_opcode_ad_dsize_02_auxiliary,
+ /* 03 */ (const void *)&gLegacyMap_opcode_ad_dsize_03_auxiliary,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ac_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1322] // LODSB AL,Xb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ac_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1321] // LODSB AL,Xb
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ac_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ac_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ac_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2521] // STOSQ Yv,RAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2520] // STOSQ Yv,RAX
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_03_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ab_dsize_03_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ab_dsize_03_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2519] // STOSD Yv,EAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2518] // STOSD Yv,EAX
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_02_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ab_dsize_02_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ab_dsize_02_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2523] // STOSW Yv,AX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2522] // STOSW Yv,AX
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_ab_dsize_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_ab_dsize_01_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_ab_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_ab_dsize_01_auxiliary,
+ /* 02 */ (const void *)&gLegacyMap_opcode_ab_dsize_02_auxiliary,
+ /* 03 */ (const void *)&gLegacyMap_opcode_ab_dsize_03_auxiliary,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2517] // STOSB Yb,AL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2516] // STOSB Yb,AL
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_aa_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_aa_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_aa_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2629] // TEST rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a8_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2628] // TEST AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_03_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 661] // CMPSQ Xv,Yv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_03_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 660] // CMPSQ Xv,Yv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_03_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a7_dsize_03_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a7_dsize_03_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_02_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 658] // CMPSD Xv,Yv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_02_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 657] // CMPSD Xv,Yv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_02_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a7_dsize_02_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a7_dsize_02_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_01_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 664] // CMPSW Xv,Yv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 663] // CMPSW Xv,Yv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a7_dsize_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a7_dsize_01_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_a7_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_a7_dsize_01_auxiliary,
+ /* 02 */ (const void *)&gLegacyMap_opcode_a7_dsize_02_auxiliary,
+ /* 03 */ (const void *)&gLegacyMap_opcode_a7_dsize_03_auxiliary,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a6_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 656] // CMPSB Xb,Yb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a6_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 655] // CMPSB Xb,Yb
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a6_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a6_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a6_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1458] // MOVSQ Yv,Xv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1457] // MOVSQ Yv,Xv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_03_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a5_dsize_03_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a5_dsize_03_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1452] // MOVSD Yv,Xv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1451] // MOVSD Yv,Xv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_02_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a5_dsize_02_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a5_dsize_02_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1462] // MOVSW Yv,Xv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1461] // MOVSW Yv,Xv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a5_dsize_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a5_dsize_01_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_a5_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_a5_dsize_01_auxiliary,
+ /* 02 */ (const void *)&gLegacyMap_opcode_a5_dsize_02_auxiliary,
+ /* 03 */ (const void *)&gLegacyMap_opcode_a5_dsize_03_auxiliary,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1450] // MOVSB Yb,Xb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1449] // MOVSB Yb,Xb
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a4_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a4_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_a4_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1368] // MOV Ov,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1367] // MOV Ob,AL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a1_auxiliary_07_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1180] // JMPABS Aq
+};
+
+const ND_TABLE_EX_W gLegacyMap_opcode_a1_auxiliary_07_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a1_auxiliary_07_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a1_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1366] // MOV rAX,Ov
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_a1_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_a1_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)&gLegacyMap_opcode_a1_auxiliary_07_w,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1365] // MOV AL,Ob
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1299] // LAHF
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2196] // SAHF
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1841] // POPFQ Fv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1840] // POPFD Fv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1842] // POPFW Fv
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_9d_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_9d_dsize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_9d_dsize_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_9d_dsize_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1977] // PUSHFQ Fv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1976] // PUSHFD Fv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1978] // PUSHFW Fv
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_9c_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_9c_dsize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_9c_dsize_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_9c_dsize_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4098] // WAIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 242] // CALLF Ap
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 676] // CQO
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 421] // CDQ
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 848] // CWD
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_99_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_99_dsize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_99_dsize_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_99_dsize_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 422] // CDQE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 849] // CWDE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 244] // CBW
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_98_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_98_dsize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_98_dsize_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_98_dsize_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_97_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4130] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_96_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4129] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_95_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4128] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_94_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4127] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_93_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4126] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_92_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4125] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_91_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4124] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1683] // PAUSE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4123] // XCHG Zv,rAX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1503] // NOP
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_90_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_90_auxiliary_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_90_auxiliary_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_90_auxiliary_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8f_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1828] // POP Ev
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_8f_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_8f_modrmreg_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8e_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1364] // MOV Sw,Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8e_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1363] // MOV Sw,Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8e_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_8e_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_8e_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8d_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1307] // LEA Gv,M0
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8d_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_8d_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8c_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1362] // MOV Rv,Sw
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8c_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1361] // MOV Mw,Sw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8c_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_8c_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_8c_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1360] // MOV Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1359] // MOV Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_89_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1358] // MOV Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_88_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1357] // MOV Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_87_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4122] // XCHG Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_86_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4121] // XCHG Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_85_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2627] // TEST Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_84_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2626] // TEST Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 624] // CMP Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4187] // XOR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2582] // SUB Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 173] // AND Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2316] // SBB Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 39] // ADC Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1635] // OR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 96] // ADD Ev,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_83_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_83_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_83_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_83_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_83_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_83_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_83_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_83_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_83_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 623] // CMP Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4186] // XOR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2581] // SUB Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 172] // AND Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2315] // SBB Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 38] // ADC Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1634] // OR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 95] // ADD Eb,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_82_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_82_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_82_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_82_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_82_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_82_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_82_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_82_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_82_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 622] // CMP Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4185] // XOR Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2580] // SUB Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 171] // AND Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2314] // SBB Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 37] // ADC Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1633] // OR Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 94] // ADD Ev,Iz
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_81_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_81_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_81_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_81_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_81_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_81_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_81_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_81_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_81_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 621] // CMP Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4184] // XOR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2579] // SUB Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 170] // AND Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2313] // SBB Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 36] // ADC Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1632] // OR Eb,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 93] // ADD Eb,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_80_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_80_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_80_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_80_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_80_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_80_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_80_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_80_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_80_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1191] // JNLE Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1175] // JLE Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1189] // JNL Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1173] // JL Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1195] // JNP Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1203] // JP Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_79_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1197] // JNS Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_78_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1206] // JS Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_77_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1185] // JNBE Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_76_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1167] // JBE Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_75_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1199] // JNZ Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_74_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1208] // JZ Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_73_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1187] // JNC Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_72_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1169] // JC Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_71_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1193] // JNO Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_70_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1201] // JO Jb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1647] // OUTSW DX,Xz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1646] // OUTSW DX,Xz
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6f_dsize_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_6f_dsize_01_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1645] // OUTSD DX,Xz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1644] // OUTSD DX,Xz
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6f_dsize_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_6f_dsize_00_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_6f_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6f_dsize_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_6f_dsize_01_auxiliary,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1643] // OUTSB DX,Xb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1642] // OUTSB DX,Xb
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_6e_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6e_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_6e_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_01_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1149] // INSW Yz,DX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1148] // INSW Yz,DX
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_6d_dsize_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6d_dsize_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_6d_dsize_01_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_00_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1143] // INSD Yz,DX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1142] // INSD Yz,DX
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_6d_dsize_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6d_dsize_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_6d_dsize_00_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_6d_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6d_dsize_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_6d_dsize_01_auxiliary,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6c_auxiliary_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1141] // INSB Yb,DX
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6c_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1140] // INSB Yb,DX
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_6c_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_6c_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_6c_auxiliary_05_leaf,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1108] // IMUL Gv,Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1968] // PUSH Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_69_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1107] // IMUL Gv,Ev,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_68_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1967] // PUSH Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1465] // MOVSXD Gv,Ez
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 183] // ARPL Ew,Gw
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_63_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_63_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_63_auxiliary_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_62_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 218] // BOUND Gv,Ma
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_62_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_62_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1834] // POPAD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1833] // POPA
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_61_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_61_dsize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_61_dsize_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1975] // PUSHAD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1974] // PUSHA
+};
+
+const ND_TABLE_DSIZE gLegacyMap_opcode_60_dsize =
+{
+ ND_ILUT_DSIZE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_60_dsize_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_60_dsize_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1850] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1827] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_5f_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_5f_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_5f_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1849] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1826] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_5e_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_5e_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_5e_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1848] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1825] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_5d_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_5d_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_5d_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1847] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1824] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_5c_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_5c_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_5c_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1846] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1823] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_5b_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_5b_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_5b_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1845] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1822] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_5a_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_5a_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_5a_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1844] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1821] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_59_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_59_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_59_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1843] // POPP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1820] // POP Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_58_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_58_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_58_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1986] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1966] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_57_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_57_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_57_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1985] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1965] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_56_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_56_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_56_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1984] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1964] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_55_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_55_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_55_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1983] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1963] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_54_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_54_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_54_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1982] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1962] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_53_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_53_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_53_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1981] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1961] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_52_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_52_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_52_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1980] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1960] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_51_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_51_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_51_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1979] // PUSHP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1959] // PUSH Zv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_50_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_50_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_50_auxiliary_08_leaf,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 871] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 870] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 869] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 868] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 867] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 866] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_49_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 865] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_48_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 864] // DEC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_47_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1135] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_46_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1134] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_45_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1133] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_44_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1132] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_43_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1131] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_42_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1130] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_41_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1129] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_40_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1128] // INC Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 7] // AAS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 620] // CMP rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 619] // CMP AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 618] // CMP Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 617] // CMP Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_39_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 616] // CMP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_38_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 615] // CMP Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_37_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 0] // AAA
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_35_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4183] // XOR rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_34_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4182] // XOR AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_33_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4181] // XOR Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_32_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4180] // XOR Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_31_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4179] // XOR Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_30_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4178] // XOR Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 851] // DAS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2578] // SUB rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2577] // SUB AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2576] // SUB Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2575] // SUB Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_29_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2574] // SUB Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_28_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2573] // SUB Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_27_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 850] // DAA
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_25_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 169] // AND rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_24_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 168] // AND AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_23_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 167] // AND Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_22_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 166] // AND Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_21_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 165] // AND Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_20_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 164] // AND Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1819] // POP DS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1958] // PUSH DS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2312] // SBB rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2311] // SBB AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2310] // SBB Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2309] // SBB Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_19_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2308] // SBB Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_18_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2307] // SBB Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_17_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1818] // POP SS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_16_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1957] // PUSH SS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_15_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 35] // ADC rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_14_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 34] // ADC AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_13_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 33] // ADC Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_12_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 32] // ADC Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_11_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 31] // ADC Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_10_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 30] // ADC Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ff_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2664] // UD0 Gd,Ed
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1664] // PADDD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1663] // PADDD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fe_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fe_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fe_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1676] // PADDW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1675] // PADDW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fd_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fd_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fd_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1662] // PADDB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1661] // PADDB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fc_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fc_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fc_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1927] // PSUBQ Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1926] // PSUBQ Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fb_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fb_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fb_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1925] // PSUBD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1924] // PSUBD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fa_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fa_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fa_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1937] // PSUBW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1936] // PSUBW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f9_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f9_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f9_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1923] // PSUBB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1922] // PSUBB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f8_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f8_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f8_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1343] // MASKMOVDQU Vdq,Udq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1344] // MASKMOVQ Pq,Nq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f7_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1874] // PSADBW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1873] // PSADBW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f6_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f6_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f6_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1773] // PMADDWD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1772] // PMADDWD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f5_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f5_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f5_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1816] // PMULUDQ Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1815] // PMULUDQ Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f4_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f4_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f4_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1895] // PSLLQ Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1894] // PSLLQ Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f3_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f3_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f3_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1890] // PSLLD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1889] // PSLLD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f2_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f2_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f2_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1899] // PSLLW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1898] // PSLLW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f1_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f1_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f1_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1302] // LDDQU Vx,Mx
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f0_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1989] // PXOR Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1988] // PXOR Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ef_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ef_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ef_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1777] // PMAXSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1776] // PMAXSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ee_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ee_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ee_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1670] // PADDSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1669] // PADDSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ed_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ed_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ed_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1668] // PADDSB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1667] // PADDSB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ec_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ec_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ec_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1852] // POR Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1851] // POR Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_eb_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_eb_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_eb_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1785] // PMINSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1784] // PMINSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ea_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ea_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ea_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1931] // PSUBSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1930] // PSUBSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e9_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e9_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e9_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1929] // PSUBSB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1928] // PSUBSB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e8_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e8_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e8_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1430] // MOVNTDQ Mx,Vx
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1435] // MOVNTQ Mq,Pq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e7_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 828] // CVTPD2DQ Vx,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 826] // CVTDQ2PD Vx,Wq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 842] // CVTTPD2DQ Vx,Wpd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e6_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1811] // PMULHW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1810] // PMULHW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e5_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e5_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e5_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1809] // PMULHUW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1808] // PMULHUW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e4_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e4_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e4_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1688] // PAVGW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1687] // PAVGW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e3_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e3_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e3_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1904] // PSRAD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1903] // PSRAD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e2_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e2_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e2_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1908] // PSRAW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1907] // PSRAW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e1_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e1_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e1_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1685] // PAVGB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1684] // PAVGB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e0_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e0_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e0_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1682] // PANDN Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1681] // PANDN Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_df_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_df_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_df_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1779] // PMAXUB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1778] // PMAXUB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_de_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_de_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_de_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1674] // PADDUSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1673] // PADDUSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dd_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_dd_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_dd_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1672] // PADDUSB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1671] // PADDUSB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dc_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_dc_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_dc_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1680] // PAND Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1679] // PAND Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_db_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_db_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_db_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1787] // PMINUB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1786] // PMINUB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_da_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_da_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_da_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1935] // PSUBUSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1934] // PSUBUSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d9_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d9_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d9_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1933] // PSUBUSB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1932] // PSUBUSB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d8_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d8_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d8_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1791] // PMOVMSKB Gy,Ux
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1790] // PMOVMSKB Gy,Nq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d7_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1414] // MOVDQ2Q Pq,Uq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1446] // MOVQ2DQ Vdq,Nq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1445] // MOVQ Wq,Vq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d6_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1814] // PMULLW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1813] // PMULLW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d5_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d5_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d5_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1666] // PADDQ Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1665] // PADDQ Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d4_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d4_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d4_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1917] // PSRLQ Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1916] // PSRLQ Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d3_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d3_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d3_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1912] // PSRLD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1911] // PSRLD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d2_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d2_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d2_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1921] // PSRLW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1920] // PSRLW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d1_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d1_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d1_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d0_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 102] // ADDSUBPS Vps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d0_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 101] // ADDSUBPD Vpd,Wpd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d0_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d0_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_d0_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cf_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 228] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ce_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 227] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cd_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 226] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cc_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 225] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 224] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ca_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 223] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 222] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c8_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 221] // BSWAP Zv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2082] // RDPID Ryf
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2089] // RDSEED Rv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2088] // RDSEED Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3387] // VMPTRST Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2328] // SENDUIPI Rq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3405] // VMXON Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2087] // RDRAND Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3243] // VMCLEAR Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2086] // RDRAND Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3386] // VMPTRLD Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4202] // XSAVES64 M?
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4201] // XSAVES M?
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4198] // XSAVEC64 M?
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4197] // XSAVEC M?
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4194] // XRSTORS64 M?
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4193] // XRSTORS M?
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 669] // CMPXCHG16B Mdq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 670] // CMPXCHG8B Mq
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_c7_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2496] // SHUFPD Vpd,Wpd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2497] // SHUFPS Vps,Wps,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c6_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c6_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c6_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1723] // PEXTRW Gy,Udq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1722] // PEXTRW Gy,Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c5_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1768] // PINSRW Vdq,Rd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1769] // PINSRW Vdq,Mw,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1766] // PINSRW Pq,Rd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1767] // PINSRW Pq,Mw,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c4_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1432] // MOVNTI My,Gy
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c3_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 659] // CMPSD Vsd,Wsd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 662] // CMPSS Vss,Wss,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 651] // CMPPD Vpd,Wpd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 652] // CMPPS Vps,Wps,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c2_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4119] // XADD Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4118] // XADD Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bf_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1464] // MOVSX Gv,Ew
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_be_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1463] // MOVSX Gv,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bd_auxiliary_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1342] // LZCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bd_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 220] // BSR Gv,Ev
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bd_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_bd_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_bd_auxiliary_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2660] // TZCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 219] // BSF Gv,Ev
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bc_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_bc_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_bc_auxiliary_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 232] // BTC Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 231] // BTC Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 234] // BTR Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 236] // BTS Ev,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 230] // BT Ev,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ba_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2665] // UD1 Gd,Ed
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1839] // POPCNT Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1182] // JMPE Jz
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_b8_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b8_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_b8_auxiliary_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1471] // MOVZX Gv,Ew
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1470] // MOVZX Gv,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b5_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1313] // LGS Gv,Mp
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b5_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b5_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b4_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1311] // LFS Gv,Mp
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b4_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b4_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 233] // BTR Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b2_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1334] // LSS Gv,Mp
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b2_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b2_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 668] // CMPXCHG Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 667] // CMPXCHG Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_af_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1111] // IMUL Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2669] // UMWAIT Ry
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2668] // UMONITOR mMb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 561] // CLRSSBSY Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1139] // INCSSPQ Rq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1138] // INCSSPD Rd
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1940] // PTWRITE Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4102] // WRGSBASE Ry
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4101] // WRFSBASE Ry
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2077] // RDGSBASE Ry
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2076] // RDFSBASE Ry
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 558] // CLFLUSHOPT Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2649] // TPAUSE Ry
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 564] // CLWB Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2363] // SFENCE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 557] // CLFLUSH Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1350] // MFENCE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4200] // XSAVEOPT64 M?
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4199] // XSAVEOPT M?
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1310] // LFENCE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4192] // XRSTOR64 M?
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4191] // XRSTOR M?
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4196] // XSAVE64 M?
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4195] // XSAVE M?
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2515] // STMXCSR Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1303] // LDMXCSR Md
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1053] // FXRSTOR64 Mrx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1052] // FXRSTOR Mrx
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1055] // FXSAVE64 Mrx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1054] // FXSAVE Mrx
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ae_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ad_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2493] // SHRD Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ac_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2492] // SHRD Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ab_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 235] // BTS Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_aa_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2192] // RSM
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a9_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1830] // POP GS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a8_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1971] // PUSH GS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a5_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2431] // SHLD Ev,Gv,CL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a4_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2430] // SHLD Ev,Gv,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 229] // BT Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 675] // CPUID
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1829] // POP FS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1970] // PUSH FS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2345] // SETNLE Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2337] // SETLE Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2343] // SETNL Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2335] // SETL Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2349] // SETNP Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2357] // SETP Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_99_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2351] // SETNS Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_98_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2359] // SETS Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_97_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2339] // SETNBE Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_96_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2331] // SETBE Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_95_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2353] // SETNZ Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_94_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2362] // SETZ Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_93_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2341] // SETNC Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_92_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2333] // SETC Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_91_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2347] // SETNO Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_90_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2355] // SETO Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1192] // JNLE Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1176] // JLE Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1190] // JNL Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1174] // JL Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1196] // JNP Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1204] // JP Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_89_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1198] // JNS Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_88_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1207] // JS Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_87_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1186] // JNBE Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_86_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1168] // JBE Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_85_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1200] // JNZ Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_84_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1209] // JZ Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_83_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1188] // JNC Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_82_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1170] // JC Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_81_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1194] // JNO Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_80_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1202] // JO Jz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1418] // MOVDQU Wx,Vx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1416] // MOVDQA Wx,Vx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1444] // MOVQ Qq,Pq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7f_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1443] // MOVQ Vdq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1442] // MOVQ Ey,Vdq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1408] // MOVD Ey,Vdq
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1441] // MOVQ Ey,Pq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1407] // MOVD Ey,Pd
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7e_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7d_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1068] // HSUBPS Vps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7d_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1067] // HSUBPD Vpd,Wpd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7d_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7d_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_7d_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7c_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1064] // HADDPS Vps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7c_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1063] // HADDPD Vpd,Wpd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7c_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7c_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_7c_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1147] // INSERTQ Vdq,Udq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 906] // EXTRQ Vdq,Uq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3403] // VMWRITE Gy,Ey
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_79_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1146] // INSERTQ Vdq,Udq,Ib,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 905] // EXTRQ Uq,Ib,Ib
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3388] // VMREAD Ey,Gy
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_78_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_77_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 889] // EMMS
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_77_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_77_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1696] // PCMPEQD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1695] // PCMPEQD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_76_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_76_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_76_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1699] // PCMPEQW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1698] // PCMPEQW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_75_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_75_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_75_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1694] // PCMPEQB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1693] // PCMPEQB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_74_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_74_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_74_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1891] // PSLLDQ Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1893] // PSLLQ Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1913] // PSRLDQ Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1915] // PSRLQ Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1892] // PSLLQ Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1914] // PSRLQ Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_73_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1888] // PSLLD Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1902] // PSRAD Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1910] // PSRLD Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1887] // PSLLD Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1901] // PSRAD Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1909] // PSRLD Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_72_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1897] // PSLLW Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1906] // PSRAW Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1919] // PSRLW Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1896] // PSLLW Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1905] // PSRAW Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1918] // PSRLW Nq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_71_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1879] // PSHUFLW Vx,Wx,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1878] // PSHUFHW Vx,Wx,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1877] // PSHUFD Vx,Wx,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1880] // PSHUFW Pq,Qq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_70_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1417] // MOVDQU Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1415] // MOVDQA Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1440] // MOVQ Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6f_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1439] // MOVQ Vdq,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1406] // MOVD Vdq,Ey
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1438] // MOVQ Pq,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1405] // MOVD Pq,Ey
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6e_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6d_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1945] // PUNPCKHQDQ Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6d_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6d_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6c_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1952] // PUNPCKLQDQ Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6c_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6c_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1655] // PACKSSDW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1654] // PACKSSDW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6b_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6b_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6b_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1944] // PUNPCKHDQ Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1943] // PUNPCKHDQ Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6a_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6a_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6a_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1947] // PUNPCKHWD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1946] // PUNPCKHWD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_69_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_69_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_69_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1942] // PUNPCKHBW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1941] // PUNPCKHBW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_68_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_68_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_68_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1660] // PACKUSWB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1659] // PACKUSWB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_67_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_67_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_67_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1705] // PCMPGTD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1704] // PCMPGTD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_66_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_66_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_66_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1708] // PCMPGTW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1707] // PCMPGTW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_65_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_65_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_65_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1703] // PCMPGTB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1702] // PCMPGTB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_64_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_64_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_64_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1657] // PACKSSWB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1656] // PACKSSWB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_63_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_63_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_63_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1951] // PUNPCKLDQ Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1950] // PUNPCKLDQ Pq,Qd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_62_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_62_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_62_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1954] // PUNPCKLWD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1953] // PUNPCKLWD Pq,Qd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_61_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_61_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_61_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1949] // PUNPCKLBW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1948] // PUNPCKLBW Pq,Qd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_60_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_60_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_60_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1347] // MAXSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1348] // MAXSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1345] // MAXPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1346] // MAXPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5f_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 885] // DIVSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 886] // DIVSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 883] // DIVPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 884] // DIVPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5e_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1353] // MINSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1354] // MINSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1351] // MINPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1352] // MINPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5d_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2585] // SUBSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2586] // SUBSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2583] // SUBPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2584] // SUBPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5c_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 844] // CVTTPS2DQ Vdq,Wps
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 833] // CVTPS2DQ Vdq,Wps
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 827] // CVTDQ2PS Vps,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5b_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 837] // CVTSD2SS Vss,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 840] // CVTSS2SD Vsd,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 830] // CVTPD2PS Vps,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 834] // CVTPS2PD Vpd,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5a_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1483] // MULSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1484] // MULSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1481] // MULPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1482] // MULPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_59_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 99] // ADDSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 100] // ADDSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 97] // ADDPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 98] // ADDPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_58_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4188] // XORPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4189] // XORPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_57_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_57_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_57_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1636] // ORPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1637] // ORPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_56_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_56_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_56_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_55_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 177] // ANDNPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_55_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 178] // ANDNPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_55_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_55_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_55_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_54_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 179] // ANDPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_54_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 180] // ANDPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_54_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_54_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_54_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2033] // RCPSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2032] // RCPPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_53_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_53_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_53_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2194] // RSQRTSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2193] // RSQRTPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_52_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_52_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_52_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2508] // SQRTSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2509] // SQRTSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2506] // SQRTPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2507] // SQRTPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_51_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1428] // MOVMSKPD Gy,Upd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1429] // MOVMSKPS Gy,Ups
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_50_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 590] // CMOVNLE Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 578] // CMOVLE Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 587] // CMOVNL Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 575] // CMOVL Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 596] // CMOVNP Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 608] // CMOVP Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_49_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 599] // CMOVNS Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_48_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 611] // CMOVS Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_47_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 581] // CMOVNBE Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_46_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 569] // CMOVBE Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_45_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 602] // CMOVNZ Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_44_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 614] // CMOVZ Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_43_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 584] // CMOVNC Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_42_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 572] // CMOVC Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_41_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 593] // CMOVNO Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_40_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 605] // CMOVO Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1066] // HRESET Ib
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 119] // AESKEYGENASSIST Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1060] // GF2P8AFFINEINVQB Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1061] // GF2P8AFFINEQB Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2368] // SHA1RNDS4 Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1709] // PCMPISTRI Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1710] // PCMPISTRM Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1700] // PCMPESTRI Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1701] // PCMPESTRM Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1692] // PCLMULQDQ Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1472] // MPSADBW Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 887] // DPPD Vdq,Wdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 888] // DPPS Vx,Wx,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1765] // PINSRQ Vdq,Eq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1764] // PINSRD Vdq,Ed,Ib
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1145] // INSERTPS Vdq,Udq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1144] // INSERTPS Vdq,Md,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1763] // PINSRB Vdq,Ry,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1762] // PINSRB Vdq,Mb,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 904] // EXTRACTPS Ed,Vdq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1721] // PEXTRQ Ry,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1719] // PEXTRD Ry,Vdq,Ib
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1720] // PEXTRQ Mq,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1718] // PEXTRD Md,Vdq,Ib
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1725] // PEXTRW Ry,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1724] // PEXTRW Mw,Vdq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1717] // PEXTRB Ry,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1716] // PEXTRB Mb,Vdq,Ib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1678] // PALIGNR Vx,Wx,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1677] // PALIGNR Pq,Qq,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1690] // PBLENDW Vx,Wx,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 195] // BLENDPD Vx,Wx,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 196] // BLENDPS Vx,Wx,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2190] // ROUNDSD Vsd,Wsd,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2191] // ROUNDSS Vss,Wss,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2188] // ROUNDPD Vx,Wx,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2189] // ROUNDPS Vx,Wx,Ib
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_3a_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix,
+ /* 09 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix,
+ /* 0a */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix,
+ /* 0b */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix,
+ /* 0c */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix,
+ /* 0d */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix,
+ /* 0e */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix,
+ /* 0f */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix,
+ /* 15 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix,
+ /* 16 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix,
+ /* 17 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix,
+ /* 21 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix,
+ /* 22 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix,
+ /* 41 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix,
+ /* 42 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix,
+ /* 61 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix,
+ /* 62 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix,
+ /* 63 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix,
+ /* cf */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 182] // AOR My,Gy
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 185] // AXOR My,Gy
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 6] // AAND My,Gy
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3] // AADD My,Gy
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 894] // ENCODEKEY256 Gd,Rd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 893] // ENCODEKEY128 Gd,Rd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1413] // MOVDIRI My,Gy
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2676] // URDMSR Rq,Gq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 898] // ENQCMD rM?,Moq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2680] // UWRMSR Gq,Rq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 900] // ENQCMDS rM?,Moq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1411] // MOVDIR64B rMoq,Moq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 105] // ADOX Gy,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 42] // ADCX Gy,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4112] // WRSSQ My,Gy
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4110] // WRSSD My,Gy
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4116] // WRUSSQ My,Gy
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4114] // WRUSSD My,Gy
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 681] // CRC32 Gy,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1404] // MOVBE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1403] // MOVBE Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 680] // CRC32 Gy,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1402] // MOVBE Gv,Mv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1401] // MOVBE Gv,Mv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 108] // AESDEC256KL Vdq,M512
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 109] // AESDECLAST Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 114] // AESENC256KL Vdq,M512
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 106] // AESDEC Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 107] // AESDEC128KL Vdq,M384
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 115] // AESENCLAST Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1320] // LOADIWKEY Vdq,Udq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 113] // AESENC128KL Vdq,M384
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 112] // AESENC Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 118] // AESIMC Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 111] // AESDECWIDE256KL M512
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 117] // AESENCWIDE256KL M512
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 110] // AESDECWIDE128KL M384
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 116] // AESENCWIDE128KL M384
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1062] // GF2P8MULB Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2370] // SHA256MSG2 Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2369] // SHA256MSG1 Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2371] // SHA256RNDS2 Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2366] // SHA1MSG2 Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2365] // SHA1MSG1 Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2367] // SHA1NEXTE Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1448] // MOVRS Gv,Mv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1447] // MOVRS Gb,Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1161] // INVPCID Gy,Mdq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1163] // INVVPID Gy,Mdq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1156] // INVEPT Gy,Mdq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1753] // PHMINPOSUW Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1812] // PMULLD Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1780] // PMAXUD Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1781] // PMAXUW Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1775] // PMAXSD Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1774] // PMAXSB Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1788] // PMINUD Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1789] // PMINUW Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1783] // PMINSD Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1782] // PMINSB Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1706] // PCMPGTQ Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1801] // PMOVZXDQ Vdq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1803] // PMOVZXWQ Vdq,Wd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1802] // PMOVZXWD Vdq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1799] // PMOVZXBQ Vdq,Ww
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1798] // PMOVZXBD Vdq,Wd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1800] // PMOVZXBW Vdq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1658] // PACKUSDW Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1431] // MOVNTDQA Vx,Mx
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1697] // PCMPEQQ Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1804] // PMULDQ Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1795] // PMOVSXDQ Vdq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1797] // PMOVSXWQ Vdq,Wd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1796] // PMOVSXWD Vdq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1793] // PMOVSXBQ Vdq,Ww
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1792] // PMOVSXBD Vdq,Wd
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1794] // PMOVSXBW Vdq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1651] // PABSD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1650] // PABSD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1653] // PABSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1652] // PABSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1649] // PABSB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1648] // PABSB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1939] // PTEST Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 197] // BLENDVPD Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 198] // BLENDVPS Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1689] // PBLENDVB Vdq,Wdq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1806] // PMULHRSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1805] // PMULHRSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1884] // PSIGND Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1883] // PSIGND Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1886] // PSIGNW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1885] // PSIGNW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1882] // PSIGNB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1881] // PSIGNB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1757] // PHSUBSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1756] // PHSUBSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1755] // PHSUBD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1754] // PHSUBD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1759] // PHSUBW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1758] // PHSUBW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1771] // PMADDUBSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1770] // PMADDUBSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1750] // PHADDSW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1749] // PHADDSW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1748] // PHADDD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1747] // PHADDD Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1752] // PHADDW Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1751] // PHADDW Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1876] // PSHUFB Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1875] // PSHUFB Pq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_38_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix,
+ /* 08 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix,
+ /* 09 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix,
+ /* 0a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix,
+ /* 0b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix,
+ /* 15 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix,
+ /* 1d */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix,
+ /* 1e */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix,
+ /* 21 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix,
+ /* 22 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix,
+ /* 23 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix,
+ /* 24 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix,
+ /* 25 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix,
+ /* 29 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix,
+ /* 2a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix,
+ /* 2b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix,
+ /* 31 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix,
+ /* 32 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix,
+ /* 33 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix,
+ /* 34 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix,
+ /* 35 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix,
+ /* 38 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix,
+ /* 39 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix,
+ /* 3a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix,
+ /* 3b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix,
+ /* 3c */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix,
+ /* 3d */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix,
+ /* 3e */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix,
+ /* 3f */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix,
+ /* 40 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix,
+ /* 41 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix,
+ /* 81 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix,
+ /* 82 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8a_modrmmod,
+ /* 8b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_8b_modrmmod,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix,
+ /* c9 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix,
+ /* ca */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix,
+ /* cb */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix,
+ /* cc */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix,
+ /* cd */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix,
+ /* dc */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix,
+ /* dd */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix,
+ /* de */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix,
+ /* df */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix,
+ /* f1 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix,
+ /* f6 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix,
+ /* f9 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix,
+ /* fa */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix,
+ /* fb */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix,
+ /* fc */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_37_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1059] // GETSEC
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_37_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_37_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_35_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2590] // SYSEXIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_34_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2589] // SYSENTER
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_33_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2084] // RDPMC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_32_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2079] // RDMSR
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_31_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2092] // RDTSC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_30_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4103] // WRMSR
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2f_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 673] // COMISD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2f_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 674] // COMISS Vss,Wss
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2f_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2f_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2f_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2662] // UCOMISD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2663] // UCOMISS Vss,Wss
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2e_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2e_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2e_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 836] // CVTSD2SI Gy,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 841] // CVTSS2SI Gy,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 829] // CVTPD2PI Pq,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 835] // CVTPS2PI Pq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2d_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 846] // CVTTSD2SI Gy,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 847] // CVTTSS2SI Gy,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 843] // CVTTPD2PI Pq,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 845] // CVTTPS2PI Pq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2c_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1436] // MOVNTSD Msd,Vsd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1437] // MOVNTSS Mss,Vss
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1433] // MOVNTPD Mpd,Vpd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1434] // MOVNTPS Mps,Vps
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2b_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 838] // CVTSI2SD Vsd,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 839] // CVTSI2SS Vss,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 831] // CVTPI2PD Vpd,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 832] // CVTPI2PS Vq,Qq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2a_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_29_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1394] // MOVAPD Wpd,Vpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_29_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1396] // MOVAPS Wps,Vps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_29_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_29_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_29_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_28_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1393] // MOVAPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_28_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1395] // MOVAPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_28_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_28_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_28_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_26_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1392] // MOV Ty,Ry
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_24_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1391] // MOV Ry,Ty
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_23_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1390] // MOV Dy,Ry
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_22_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1389] // MOV Cy,Ry
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_21_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1388] // MOV Ry,Dy
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_20_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1387] // MOV Ry,Cy
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1536] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1573] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1572] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1571] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1570] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 895] // ENDBR32
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1569] // NOP Rv,Gv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 896] // ENDBR64
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1568] // NOP Rv,Gv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1567] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1566] // NOP Rv,Gv
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1565] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1564] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1563] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1562] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1561] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1560] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1559] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1558] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1557] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1556] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1555] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2091] // RDSSPQ Rq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2090] // RDSSPD Rd
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1554] // NOP Rv,Gv
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1553] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1552] // NOP Rv,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1551] // NOP Mv,Gv
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1535] // NOP Ev,Gv
+};
+
+const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1e_feature =
+{
+ ND_ILUT_FEATURE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1534] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1550] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1549] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1548] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1547] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1546] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1545] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1544] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1543] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1542] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1541] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1540] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 554] // CLDEMOTE Mb
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1533] // NOP Ev,Gv
+};
+
+const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1c_feature =
+{
+ ND_ILUT_FEATURE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 211] // BNDCN rBl,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1539] // NOP Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 214] // BNDMK rBl,My
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 216] // BNDMOV mBl,rBl
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1538] // NOP Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 217] // BNDSTX Mmib,rBl
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1532] // NOP Gv,Ev
+};
+
+const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1b_feature =
+{
+ ND_ILUT_FEATURE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 212] // BNDCU rBl,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 210] // BNDCL rBl,Ey
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 215] // BNDMOV rBl,mBl
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1537] // NOP Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 213] // BNDLDX rBl,Mmib
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1531] // NOP Ev,Gv
+};
+
+const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1a_feature =
+{
+ ND_ILUT_FEATURE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_19_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1520] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1530] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1858] // PREFETCHIT0 Mb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1529] // NOP Ev
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1528] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1859] // PREFETCHIT1 Mb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1527] // NOP Ev
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1526] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1525] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1864] // PREFETCHRST2 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1524] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1870] // PREFETCHT2 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1523] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1868] // PREFETCHT1 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1522] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1866] // PREFETCHT0 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1521] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1862] // PREFETCHNTA Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1519] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1518] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1517] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1516] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1863] // PREFETCHRST2 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1515] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1869] // PREFETCHT2 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1514] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1867] // PREFETCHT1 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1513] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1865] // PREFETCHT0 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1512] // NOP Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1861] // PREFETCHNTA Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_18_feature =
+{
+ ND_ILUT_FEATURE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1421] // MOVHPD Mq,Vq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1423] // MOVHPS Mq,Vq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_17_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1455] // MOVSHDUP Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1420] // MOVHPD Vq,Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1424] // MOVLHPS Vq,Uq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1422] // MOVHPS Vq,Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_16_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2670] // UNPCKHPD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2671] // UNPCKHPS Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_15_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_15_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_15_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2672] // UNPCKLPD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2673] // UNPCKLPS Vx,Wx
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_14_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_14_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_14_prefix_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1426] // MOVLPD Mq,Vpd
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1427] // MOVLPS Mq,Vps
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_13_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1409] // MOVDDUP Vdq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1456] // MOVSLDUP Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1425] // MOVLPD Vsd,Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1419] // MOVHLPS Vq,Wq
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_12_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1454] // MOVSD Wsd,Vsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1460] // MOVSS Wss,Vss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1467] // MOVUPD Wpd,Vpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1469] // MOVUPS Wps,Vps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_11_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1453] // MOVSD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1459] // MOVSS Vss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1466] // MOVUPD Vpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1468] // MOVUPS Vps,Wps
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_10_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bf_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1686] // PAVGUSB Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1938] // PSWAPD Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1807] // PMULHRW Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1740] // PFRCPIT2 Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b4_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1735] // PFMUL Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1730] // PFCMPEQ Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_ae_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1728] // PFACC Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_aa_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1746] // PFSUBR Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1742] // PFRSQIT1 Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1739] // PFRCPIT1 Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a4_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1733] // PFMAX Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1732] // PFCMPGT Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1729] // PFADD Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1745] // PFSUB Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_97_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1743] // PFRSQRT Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_96_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1738] // PFRCP Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_94_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1734] // PFMIN Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_90_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1731] // PFCMPGE Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1737] // PFPNACC Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1736] // PFNACC Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_87_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1744] // PFRSQRTV Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_86_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1741] // PFRCPV Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1726] // PF2ID Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1727] // PF2IW Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1760] // PI2FD Pq,Qq
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1761] // PI2FW Pq,Qq
+};
+
+const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_0f_opcode_last =
+{
+ ND_ILUT_OPCODE_LAST,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_0c_leaf,
+ /* 0d */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_0d_leaf,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_1c_leaf,
+ /* 1d */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_1d_leaf,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_86_leaf,
+ /* 87 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_87_leaf,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_8a_leaf,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_8e_leaf,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_90_leaf,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_94_leaf,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_96_leaf,
+ /* 97 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_97_leaf,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_9a_leaf,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_9e_leaf,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a0_leaf,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a4_leaf,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a6_leaf,
+ /* a7 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a7_leaf,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_aa_leaf,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_ae_leaf,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b0_leaf,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b4_leaf,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b6_leaf,
+ /* b7 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b7_leaf,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_bb_leaf,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_bf_leaf,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 949] // FEMMS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1511] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1856] // PREFETCH Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1510] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1855] // PREFETCH Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1509] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1854] // PREFETCH Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1508] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1853] // PREFETCH Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1507] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1860] // PREFETCHM Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1506] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1872] // PREFETCHWT1 Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1505] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1871] // PREFETCHW Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1504] // NOP Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1857] // PREFETCHE Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_0d_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2666] // UD2
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4100] // WBNOINVD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4099] // WBINVD
+};
+
+const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_09_auxiliary =
+{
+ ND_ILUT_AUXILIARY,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_09_auxiliary_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_09_auxiliary_04_leaf,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1154] // INVD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2591] // SYSRET
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 562] // CLTS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2588] // SYSCALL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1333] // LSL Gv,Rz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1332] // LSL Gv,Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1301] // LAR Gv,Rz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1300] // LAR Gv,Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1987] // PVALIDATE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1900] // PSMASH
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2647] // TLBSYNC
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2101] // RMPUPDATE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2098] // RMPADJUST
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1159] // INVLPGB
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2100] // RMPREAD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2099] // RMPQUERY
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2085] // RDPRU
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 565] // CLZERO
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1488] // MWAITX
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1349] // MCOMMIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1356] // MONITORX
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2093] // RDTSCP
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2587] // SWAPGS
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1157] // INVLPG Mb
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1319] // LMSW Ew
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4190] // XRESLDTRK
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4204] // XSUSLDTRK
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2528] // STUI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 563] // CLUI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2634] // TESTUI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2667] // UIRET
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2284] // SAVEPREVSSP
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2360] // SETSSBSY
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2195] // RSTORSSP Mq
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4108] // WRPKRU
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2083] // RDPKRU
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2329] // SERIALIZE
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2504] // SMSW Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2503] // SMSW Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1158] // INVLPGA
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2499] // SKINIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 559] // CLGI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2513] // STGI
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3391] // VMSAVE
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3266] // VMLOAD
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3246] // VMGEXIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3245] // VMGEXIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3268] // VMMCALL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3267] // VMMCALL
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3390] // VMRUN
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1314] // LIDT Ms
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 891] // ENCLU
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4205] // XTEST
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4131] // XEND
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3244] // VMFUNC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4203] // XSETBV
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4132] // XGETBV
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1312] // LGDT Ms
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 902] // ERETS
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 903] // ERETU
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2325] // SEAMCALL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2326] // SEAMOPS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2327] // SEAMRET
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2615] // TDCALL
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 890] // ENCLS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2510] // STAC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 551] // CLAC
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1487] // MWAIT
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1355] // MONITOR
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_03_leaf,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2498] // SIDT Ms
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2081] // RDMSRLIST
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4104] // WRMSRLIST
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1691] // PBNDKB
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4106] // WRMSRNS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1711] // PCONFIG
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3404] // VMXOFF
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3389] // VMRESUME
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3265] // VMLAUNCH
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3242] // VMCALL
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 892] // ENCLV
+};
+
+const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_07_leaf,
+ }
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2364] // SGDT Ms
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1316] // LKGS Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1315] // LKGS Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1181] // JMPE Ev
+};
+
+const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix =
+{
+ ND_ILUT_MAN_PREFIX,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2926] // VERW Ew
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2925] // VERR Ew
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1335] // LTR Ew
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1317] // LLDT Ew
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2525] // STR Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2524] // STR Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2501] // SLDT Rv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2500] // SLDT Mw
+};
+
+const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg,
+ /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg,
+ /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_02_modrmmod,
+ /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_03_modrmmod,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_07_leaf,
+ /* 08 */ (const void *)&gLegacyMap_opcode_0f_opcode_08_leaf,
+ /* 09 */ (const void *)&gLegacyMap_opcode_0f_opcode_09_auxiliary,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)&gLegacyMap_opcode_0f_opcode_0b_leaf,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg,
+ /* 0e */ (const void *)&gLegacyMap_opcode_0f_opcode_0e_leaf,
+ /* 0f */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last,
+ /* 10 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix,
+ /* 11 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix,
+ /* 12 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix,
+ /* 13 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix,
+ /* 14 */ (const void *)&gLegacyMap_opcode_0f_opcode_14_prefix,
+ /* 15 */ (const void *)&gLegacyMap_opcode_0f_opcode_15_prefix,
+ /* 16 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix,
+ /* 17 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix,
+ /* 18 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature,
+ /* 19 */ (const void *)&gLegacyMap_opcode_0f_opcode_19_leaf,
+ /* 1a */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature,
+ /* 1b */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature,
+ /* 1c */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature,
+ /* 1d */ (const void *)&gLegacyMap_opcode_0f_opcode_1d_leaf,
+ /* 1e */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature,
+ /* 1f */ (const void *)&gLegacyMap_opcode_0f_opcode_1f_leaf,
+ /* 20 */ (const void *)&gLegacyMap_opcode_0f_opcode_20_leaf,
+ /* 21 */ (const void *)&gLegacyMap_opcode_0f_opcode_21_leaf,
+ /* 22 */ (const void *)&gLegacyMap_opcode_0f_opcode_22_leaf,
+ /* 23 */ (const void *)&gLegacyMap_opcode_0f_opcode_23_leaf,
+ /* 24 */ (const void *)&gLegacyMap_opcode_0f_opcode_24_leaf,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)&gLegacyMap_opcode_0f_opcode_26_leaf,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)&gLegacyMap_opcode_0f_opcode_28_prefix,
+ /* 29 */ (const void *)&gLegacyMap_opcode_0f_opcode_29_prefix,
+ /* 2a */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix,
+ /* 2b */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix,
+ /* 2c */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix,
+ /* 2d */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix,
+ /* 2e */ (const void *)&gLegacyMap_opcode_0f_opcode_2e_prefix,
+ /* 2f */ (const void *)&gLegacyMap_opcode_0f_opcode_2f_prefix,
+ /* 30 */ (const void *)&gLegacyMap_opcode_0f_opcode_30_leaf,
+ /* 31 */ (const void *)&gLegacyMap_opcode_0f_opcode_31_leaf,
+ /* 32 */ (const void *)&gLegacyMap_opcode_0f_opcode_32_leaf,
+ /* 33 */ (const void *)&gLegacyMap_opcode_0f_opcode_33_leaf,
+ /* 34 */ (const void *)&gLegacyMap_opcode_0f_opcode_34_leaf,
+ /* 35 */ (const void *)&gLegacyMap_opcode_0f_opcode_35_leaf,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)&gLegacyMap_opcode_0f_opcode_37_prefix,
+ /* 38 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)&gLegacyMap_opcode_0f_opcode_40_leaf,
+ /* 41 */ (const void *)&gLegacyMap_opcode_0f_opcode_41_leaf,
+ /* 42 */ (const void *)&gLegacyMap_opcode_0f_opcode_42_leaf,
+ /* 43 */ (const void *)&gLegacyMap_opcode_0f_opcode_43_leaf,
+ /* 44 */ (const void *)&gLegacyMap_opcode_0f_opcode_44_leaf,
+ /* 45 */ (const void *)&gLegacyMap_opcode_0f_opcode_45_leaf,
+ /* 46 */ (const void *)&gLegacyMap_opcode_0f_opcode_46_leaf,
+ /* 47 */ (const void *)&gLegacyMap_opcode_0f_opcode_47_leaf,
+ /* 48 */ (const void *)&gLegacyMap_opcode_0f_opcode_48_leaf,
+ /* 49 */ (const void *)&gLegacyMap_opcode_0f_opcode_49_leaf,
+ /* 4a */ (const void *)&gLegacyMap_opcode_0f_opcode_4a_leaf,
+ /* 4b */ (const void *)&gLegacyMap_opcode_0f_opcode_4b_leaf,
+ /* 4c */ (const void *)&gLegacyMap_opcode_0f_opcode_4c_leaf,
+ /* 4d */ (const void *)&gLegacyMap_opcode_0f_opcode_4d_leaf,
+ /* 4e */ (const void *)&gLegacyMap_opcode_0f_opcode_4e_leaf,
+ /* 4f */ (const void *)&gLegacyMap_opcode_0f_opcode_4f_leaf,
+ /* 50 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix,
+ /* 51 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix,
+ /* 52 */ (const void *)&gLegacyMap_opcode_0f_opcode_52_prefix,
+ /* 53 */ (const void *)&gLegacyMap_opcode_0f_opcode_53_prefix,
+ /* 54 */ (const void *)&gLegacyMap_opcode_0f_opcode_54_prefix,
+ /* 55 */ (const void *)&gLegacyMap_opcode_0f_opcode_55_prefix,
+ /* 56 */ (const void *)&gLegacyMap_opcode_0f_opcode_56_prefix,
+ /* 57 */ (const void *)&gLegacyMap_opcode_0f_opcode_57_prefix,
+ /* 58 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix,
+ /* 59 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix,
+ /* 5a */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix,
+ /* 5b */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix,
+ /* 5c */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix,
+ /* 5d */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix,
+ /* 5e */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix,
+ /* 5f */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix,
+ /* 60 */ (const void *)&gLegacyMap_opcode_0f_opcode_60_prefix,
+ /* 61 */ (const void *)&gLegacyMap_opcode_0f_opcode_61_prefix,
+ /* 62 */ (const void *)&gLegacyMap_opcode_0f_opcode_62_prefix,
+ /* 63 */ (const void *)&gLegacyMap_opcode_0f_opcode_63_prefix,
+ /* 64 */ (const void *)&gLegacyMap_opcode_0f_opcode_64_prefix,
+ /* 65 */ (const void *)&gLegacyMap_opcode_0f_opcode_65_prefix,
+ /* 66 */ (const void *)&gLegacyMap_opcode_0f_opcode_66_prefix,
+ /* 67 */ (const void *)&gLegacyMap_opcode_0f_opcode_67_prefix,
+ /* 68 */ (const void *)&gLegacyMap_opcode_0f_opcode_68_prefix,
+ /* 69 */ (const void *)&gLegacyMap_opcode_0f_opcode_69_prefix,
+ /* 6a */ (const void *)&gLegacyMap_opcode_0f_opcode_6a_prefix,
+ /* 6b */ (const void *)&gLegacyMap_opcode_0f_opcode_6b_prefix,
+ /* 6c */ (const void *)&gLegacyMap_opcode_0f_opcode_6c_prefix,
+ /* 6d */ (const void *)&gLegacyMap_opcode_0f_opcode_6d_prefix,
+ /* 6e */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix,
+ /* 6f */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix,
+ /* 70 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix,
+ /* 71 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix,
+ /* 72 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix,
+ /* 73 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix,
+ /* 74 */ (const void *)&gLegacyMap_opcode_0f_opcode_74_prefix,
+ /* 75 */ (const void *)&gLegacyMap_opcode_0f_opcode_75_prefix,
+ /* 76 */ (const void *)&gLegacyMap_opcode_0f_opcode_76_prefix,
+ /* 77 */ (const void *)&gLegacyMap_opcode_0f_opcode_77_prefix,
+ /* 78 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix,
+ /* 79 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)&gLegacyMap_opcode_0f_opcode_7c_prefix,
+ /* 7d */ (const void *)&gLegacyMap_opcode_0f_opcode_7d_prefix,
+ /* 7e */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix,
+ /* 7f */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix,
+ /* 80 */ (const void *)&gLegacyMap_opcode_0f_opcode_80_leaf,
+ /* 81 */ (const void *)&gLegacyMap_opcode_0f_opcode_81_leaf,
+ /* 82 */ (const void *)&gLegacyMap_opcode_0f_opcode_82_leaf,
+ /* 83 */ (const void *)&gLegacyMap_opcode_0f_opcode_83_leaf,
+ /* 84 */ (const void *)&gLegacyMap_opcode_0f_opcode_84_leaf,
+ /* 85 */ (const void *)&gLegacyMap_opcode_0f_opcode_85_leaf,
+ /* 86 */ (const void *)&gLegacyMap_opcode_0f_opcode_86_leaf,
+ /* 87 */ (const void *)&gLegacyMap_opcode_0f_opcode_87_leaf,
+ /* 88 */ (const void *)&gLegacyMap_opcode_0f_opcode_88_leaf,
+ /* 89 */ (const void *)&gLegacyMap_opcode_0f_opcode_89_leaf,
+ /* 8a */ (const void *)&gLegacyMap_opcode_0f_opcode_8a_leaf,
+ /* 8b */ (const void *)&gLegacyMap_opcode_0f_opcode_8b_leaf,
+ /* 8c */ (const void *)&gLegacyMap_opcode_0f_opcode_8c_leaf,
+ /* 8d */ (const void *)&gLegacyMap_opcode_0f_opcode_8d_leaf,
+ /* 8e */ (const void *)&gLegacyMap_opcode_0f_opcode_8e_leaf,
+ /* 8f */ (const void *)&gLegacyMap_opcode_0f_opcode_8f_leaf,
+ /* 90 */ (const void *)&gLegacyMap_opcode_0f_opcode_90_leaf,
+ /* 91 */ (const void *)&gLegacyMap_opcode_0f_opcode_91_leaf,
+ /* 92 */ (const void *)&gLegacyMap_opcode_0f_opcode_92_leaf,
+ /* 93 */ (const void *)&gLegacyMap_opcode_0f_opcode_93_leaf,
+ /* 94 */ (const void *)&gLegacyMap_opcode_0f_opcode_94_leaf,
+ /* 95 */ (const void *)&gLegacyMap_opcode_0f_opcode_95_leaf,
+ /* 96 */ (const void *)&gLegacyMap_opcode_0f_opcode_96_leaf,
+ /* 97 */ (const void *)&gLegacyMap_opcode_0f_opcode_97_leaf,
+ /* 98 */ (const void *)&gLegacyMap_opcode_0f_opcode_98_leaf,
+ /* 99 */ (const void *)&gLegacyMap_opcode_0f_opcode_99_leaf,
+ /* 9a */ (const void *)&gLegacyMap_opcode_0f_opcode_9a_leaf,
+ /* 9b */ (const void *)&gLegacyMap_opcode_0f_opcode_9b_leaf,
+ /* 9c */ (const void *)&gLegacyMap_opcode_0f_opcode_9c_leaf,
+ /* 9d */ (const void *)&gLegacyMap_opcode_0f_opcode_9d_leaf,
+ /* 9e */ (const void *)&gLegacyMap_opcode_0f_opcode_9e_leaf,
+ /* 9f */ (const void *)&gLegacyMap_opcode_0f_opcode_9f_leaf,
+ /* a0 */ (const void *)&gLegacyMap_opcode_0f_opcode_a0_leaf,
+ /* a1 */ (const void *)&gLegacyMap_opcode_0f_opcode_a1_leaf,
+ /* a2 */ (const void *)&gLegacyMap_opcode_0f_opcode_a2_leaf,
+ /* a3 */ (const void *)&gLegacyMap_opcode_0f_opcode_a3_leaf,
+ /* a4 */ (const void *)&gLegacyMap_opcode_0f_opcode_a4_leaf,
+ /* a5 */ (const void *)&gLegacyMap_opcode_0f_opcode_a5_leaf,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)&gLegacyMap_opcode_0f_opcode_a8_leaf,
+ /* a9 */ (const void *)&gLegacyMap_opcode_0f_opcode_a9_leaf,
+ /* aa */ (const void *)&gLegacyMap_opcode_0f_opcode_aa_leaf,
+ /* ab */ (const void *)&gLegacyMap_opcode_0f_opcode_ab_leaf,
+ /* ac */ (const void *)&gLegacyMap_opcode_0f_opcode_ac_leaf,
+ /* ad */ (const void *)&gLegacyMap_opcode_0f_opcode_ad_leaf,
+ /* ae */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix,
+ /* af */ (const void *)&gLegacyMap_opcode_0f_opcode_af_leaf,
+ /* b0 */ (const void *)&gLegacyMap_opcode_0f_opcode_b0_leaf,
+ /* b1 */ (const void *)&gLegacyMap_opcode_0f_opcode_b1_leaf,
+ /* b2 */ (const void *)&gLegacyMap_opcode_0f_opcode_b2_modrmmod,
+ /* b3 */ (const void *)&gLegacyMap_opcode_0f_opcode_b3_leaf,
+ /* b4 */ (const void *)&gLegacyMap_opcode_0f_opcode_b4_modrmmod,
+ /* b5 */ (const void *)&gLegacyMap_opcode_0f_opcode_b5_modrmmod,
+ /* b6 */ (const void *)&gLegacyMap_opcode_0f_opcode_b6_leaf,
+ /* b7 */ (const void *)&gLegacyMap_opcode_0f_opcode_b7_leaf,
+ /* b8 */ (const void *)&gLegacyMap_opcode_0f_opcode_b8_auxiliary,
+ /* b9 */ (const void *)&gLegacyMap_opcode_0f_opcode_b9_leaf,
+ /* ba */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg,
+ /* bb */ (const void *)&gLegacyMap_opcode_0f_opcode_bb_leaf,
+ /* bc */ (const void *)&gLegacyMap_opcode_0f_opcode_bc_auxiliary,
+ /* bd */ (const void *)&gLegacyMap_opcode_0f_opcode_bd_auxiliary,
+ /* be */ (const void *)&gLegacyMap_opcode_0f_opcode_be_leaf,
+ /* bf */ (const void *)&gLegacyMap_opcode_0f_opcode_bf_leaf,
+ /* c0 */ (const void *)&gLegacyMap_opcode_0f_opcode_c0_leaf,
+ /* c1 */ (const void *)&gLegacyMap_opcode_0f_opcode_c1_leaf,
+ /* c2 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix,
+ /* c3 */ (const void *)&gLegacyMap_opcode_0f_opcode_c3_prefix,
+ /* c4 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix,
+ /* c5 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix,
+ /* c6 */ (const void *)&gLegacyMap_opcode_0f_opcode_c6_prefix,
+ /* c7 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg,
+ /* c8 */ (const void *)&gLegacyMap_opcode_0f_opcode_c8_leaf,
+ /* c9 */ (const void *)&gLegacyMap_opcode_0f_opcode_c9_leaf,
+ /* ca */ (const void *)&gLegacyMap_opcode_0f_opcode_ca_leaf,
+ /* cb */ (const void *)&gLegacyMap_opcode_0f_opcode_cb_leaf,
+ /* cc */ (const void *)&gLegacyMap_opcode_0f_opcode_cc_leaf,
+ /* cd */ (const void *)&gLegacyMap_opcode_0f_opcode_cd_leaf,
+ /* ce */ (const void *)&gLegacyMap_opcode_0f_opcode_ce_leaf,
+ /* cf */ (const void *)&gLegacyMap_opcode_0f_opcode_cf_leaf,
+ /* d0 */ (const void *)&gLegacyMap_opcode_0f_opcode_d0_prefix,
+ /* d1 */ (const void *)&gLegacyMap_opcode_0f_opcode_d1_prefix,
+ /* d2 */ (const void *)&gLegacyMap_opcode_0f_opcode_d2_prefix,
+ /* d3 */ (const void *)&gLegacyMap_opcode_0f_opcode_d3_prefix,
+ /* d4 */ (const void *)&gLegacyMap_opcode_0f_opcode_d4_prefix,
+ /* d5 */ (const void *)&gLegacyMap_opcode_0f_opcode_d5_prefix,
+ /* d6 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix,
+ /* d7 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix,
+ /* d8 */ (const void *)&gLegacyMap_opcode_0f_opcode_d8_prefix,
+ /* d9 */ (const void *)&gLegacyMap_opcode_0f_opcode_d9_prefix,
+ /* da */ (const void *)&gLegacyMap_opcode_0f_opcode_da_prefix,
+ /* db */ (const void *)&gLegacyMap_opcode_0f_opcode_db_prefix,
+ /* dc */ (const void *)&gLegacyMap_opcode_0f_opcode_dc_prefix,
+ /* dd */ (const void *)&gLegacyMap_opcode_0f_opcode_dd_prefix,
+ /* de */ (const void *)&gLegacyMap_opcode_0f_opcode_de_prefix,
+ /* df */ (const void *)&gLegacyMap_opcode_0f_opcode_df_prefix,
+ /* e0 */ (const void *)&gLegacyMap_opcode_0f_opcode_e0_prefix,
+ /* e1 */ (const void *)&gLegacyMap_opcode_0f_opcode_e1_prefix,
+ /* e2 */ (const void *)&gLegacyMap_opcode_0f_opcode_e2_prefix,
+ /* e3 */ (const void *)&gLegacyMap_opcode_0f_opcode_e3_prefix,
+ /* e4 */ (const void *)&gLegacyMap_opcode_0f_opcode_e4_prefix,
+ /* e5 */ (const void *)&gLegacyMap_opcode_0f_opcode_e5_prefix,
+ /* e6 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix,
+ /* e7 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix,
+ /* e8 */ (const void *)&gLegacyMap_opcode_0f_opcode_e8_prefix,
+ /* e9 */ (const void *)&gLegacyMap_opcode_0f_opcode_e9_prefix,
+ /* ea */ (const void *)&gLegacyMap_opcode_0f_opcode_ea_prefix,
+ /* eb */ (const void *)&gLegacyMap_opcode_0f_opcode_eb_prefix,
+ /* ec */ (const void *)&gLegacyMap_opcode_0f_opcode_ec_prefix,
+ /* ed */ (const void *)&gLegacyMap_opcode_0f_opcode_ed_prefix,
+ /* ee */ (const void *)&gLegacyMap_opcode_0f_opcode_ee_prefix,
+ /* ef */ (const void *)&gLegacyMap_opcode_0f_opcode_ef_prefix,
+ /* f0 */ (const void *)&gLegacyMap_opcode_0f_opcode_f0_prefix,
+ /* f1 */ (const void *)&gLegacyMap_opcode_0f_opcode_f1_prefix,
+ /* f2 */ (const void *)&gLegacyMap_opcode_0f_opcode_f2_prefix,
+ /* f3 */ (const void *)&gLegacyMap_opcode_0f_opcode_f3_prefix,
+ /* f4 */ (const void *)&gLegacyMap_opcode_0f_opcode_f4_prefix,
+ /* f5 */ (const void *)&gLegacyMap_opcode_0f_opcode_f5_prefix,
+ /* f6 */ (const void *)&gLegacyMap_opcode_0f_opcode_f6_prefix,
+ /* f7 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix,
+ /* f8 */ (const void *)&gLegacyMap_opcode_0f_opcode_f8_prefix,
+ /* f9 */ (const void *)&gLegacyMap_opcode_0f_opcode_f9_prefix,
+ /* fa */ (const void *)&gLegacyMap_opcode_0f_opcode_fa_prefix,
+ /* fb */ (const void *)&gLegacyMap_opcode_0f_opcode_fb_prefix,
+ /* fc */ (const void *)&gLegacyMap_opcode_0f_opcode_fc_prefix,
+ /* fd */ (const void *)&gLegacyMap_opcode_0f_opcode_fd_prefix,
+ /* fe */ (const void *)&gLegacyMap_opcode_0f_opcode_fe_prefix,
+ /* ff */ (const void *)&gLegacyMap_opcode_0f_opcode_ff_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1956] // PUSH CS
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0d_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1631] // OR rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0c_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1630] // OR AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0b_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1629] // OR Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0a_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1628] // OR Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_09_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1627] // OR Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_08_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1626] // OR Eb,Gb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1817] // POP ES
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1955] // PUSH ES
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 92] // ADD rAX,Iz
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 91] // ADD AL,Ib
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 90] // ADD Gv,Ev
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 89] // ADD Gb,Eb
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 88] // ADD Ev,Gv
+};
+
+const ND_TABLE_INSTRUCTION gLegacyMap_opcode_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 87] // ADD Eb,Gb
+};
+
+const ND_TABLE_OPCODE gLegacyMap_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gLegacyMap_opcode_00_leaf,
+ /* 01 */ (const void *)&gLegacyMap_opcode_01_leaf,
+ /* 02 */ (const void *)&gLegacyMap_opcode_02_leaf,
+ /* 03 */ (const void *)&gLegacyMap_opcode_03_leaf,
+ /* 04 */ (const void *)&gLegacyMap_opcode_04_leaf,
+ /* 05 */ (const void *)&gLegacyMap_opcode_05_leaf,
+ /* 06 */ (const void *)&gLegacyMap_opcode_06_leaf,
+ /* 07 */ (const void *)&gLegacyMap_opcode_07_leaf,
+ /* 08 */ (const void *)&gLegacyMap_opcode_08_leaf,
+ /* 09 */ (const void *)&gLegacyMap_opcode_09_leaf,
+ /* 0a */ (const void *)&gLegacyMap_opcode_0a_leaf,
+ /* 0b */ (const void *)&gLegacyMap_opcode_0b_leaf,
+ /* 0c */ (const void *)&gLegacyMap_opcode_0c_leaf,
+ /* 0d */ (const void *)&gLegacyMap_opcode_0d_leaf,
+ /* 0e */ (const void *)&gLegacyMap_opcode_0e_leaf,
+ /* 0f */ (const void *)&gLegacyMap_opcode_0f_opcode,
+ /* 10 */ (const void *)&gLegacyMap_opcode_10_leaf,
+ /* 11 */ (const void *)&gLegacyMap_opcode_11_leaf,
+ /* 12 */ (const void *)&gLegacyMap_opcode_12_leaf,
+ /* 13 */ (const void *)&gLegacyMap_opcode_13_leaf,
+ /* 14 */ (const void *)&gLegacyMap_opcode_14_leaf,
+ /* 15 */ (const void *)&gLegacyMap_opcode_15_leaf,
+ /* 16 */ (const void *)&gLegacyMap_opcode_16_leaf,
+ /* 17 */ (const void *)&gLegacyMap_opcode_17_leaf,
+ /* 18 */ (const void *)&gLegacyMap_opcode_18_leaf,
+ /* 19 */ (const void *)&gLegacyMap_opcode_19_leaf,
+ /* 1a */ (const void *)&gLegacyMap_opcode_1a_leaf,
+ /* 1b */ (const void *)&gLegacyMap_opcode_1b_leaf,
+ /* 1c */ (const void *)&gLegacyMap_opcode_1c_leaf,
+ /* 1d */ (const void *)&gLegacyMap_opcode_1d_leaf,
+ /* 1e */ (const void *)&gLegacyMap_opcode_1e_leaf,
+ /* 1f */ (const void *)&gLegacyMap_opcode_1f_leaf,
+ /* 20 */ (const void *)&gLegacyMap_opcode_20_leaf,
+ /* 21 */ (const void *)&gLegacyMap_opcode_21_leaf,
+ /* 22 */ (const void *)&gLegacyMap_opcode_22_leaf,
+ /* 23 */ (const void *)&gLegacyMap_opcode_23_leaf,
+ /* 24 */ (const void *)&gLegacyMap_opcode_24_leaf,
+ /* 25 */ (const void *)&gLegacyMap_opcode_25_leaf,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)&gLegacyMap_opcode_27_leaf,
+ /* 28 */ (const void *)&gLegacyMap_opcode_28_leaf,
+ /* 29 */ (const void *)&gLegacyMap_opcode_29_leaf,
+ /* 2a */ (const void *)&gLegacyMap_opcode_2a_leaf,
+ /* 2b */ (const void *)&gLegacyMap_opcode_2b_leaf,
+ /* 2c */ (const void *)&gLegacyMap_opcode_2c_leaf,
+ /* 2d */ (const void *)&gLegacyMap_opcode_2d_leaf,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)&gLegacyMap_opcode_2f_leaf,
+ /* 30 */ (const void *)&gLegacyMap_opcode_30_leaf,
+ /* 31 */ (const void *)&gLegacyMap_opcode_31_leaf,
+ /* 32 */ (const void *)&gLegacyMap_opcode_32_leaf,
+ /* 33 */ (const void *)&gLegacyMap_opcode_33_leaf,
+ /* 34 */ (const void *)&gLegacyMap_opcode_34_leaf,
+ /* 35 */ (const void *)&gLegacyMap_opcode_35_leaf,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)&gLegacyMap_opcode_37_leaf,
+ /* 38 */ (const void *)&gLegacyMap_opcode_38_leaf,
+ /* 39 */ (const void *)&gLegacyMap_opcode_39_leaf,
+ /* 3a */ (const void *)&gLegacyMap_opcode_3a_leaf,
+ /* 3b */ (const void *)&gLegacyMap_opcode_3b_leaf,
+ /* 3c */ (const void *)&gLegacyMap_opcode_3c_leaf,
+ /* 3d */ (const void *)&gLegacyMap_opcode_3d_leaf,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)&gLegacyMap_opcode_3f_leaf,
+ /* 40 */ (const void *)&gLegacyMap_opcode_40_leaf,
+ /* 41 */ (const void *)&gLegacyMap_opcode_41_leaf,
+ /* 42 */ (const void *)&gLegacyMap_opcode_42_leaf,
+ /* 43 */ (const void *)&gLegacyMap_opcode_43_leaf,
+ /* 44 */ (const void *)&gLegacyMap_opcode_44_leaf,
+ /* 45 */ (const void *)&gLegacyMap_opcode_45_leaf,
+ /* 46 */ (const void *)&gLegacyMap_opcode_46_leaf,
+ /* 47 */ (const void *)&gLegacyMap_opcode_47_leaf,
+ /* 48 */ (const void *)&gLegacyMap_opcode_48_leaf,
+ /* 49 */ (const void *)&gLegacyMap_opcode_49_leaf,
+ /* 4a */ (const void *)&gLegacyMap_opcode_4a_leaf,
+ /* 4b */ (const void *)&gLegacyMap_opcode_4b_leaf,
+ /* 4c */ (const void *)&gLegacyMap_opcode_4c_leaf,
+ /* 4d */ (const void *)&gLegacyMap_opcode_4d_leaf,
+ /* 4e */ (const void *)&gLegacyMap_opcode_4e_leaf,
+ /* 4f */ (const void *)&gLegacyMap_opcode_4f_leaf,
+ /* 50 */ (const void *)&gLegacyMap_opcode_50_auxiliary,
+ /* 51 */ (const void *)&gLegacyMap_opcode_51_auxiliary,
+ /* 52 */ (const void *)&gLegacyMap_opcode_52_auxiliary,
+ /* 53 */ (const void *)&gLegacyMap_opcode_53_auxiliary,
+ /* 54 */ (const void *)&gLegacyMap_opcode_54_auxiliary,
+ /* 55 */ (const void *)&gLegacyMap_opcode_55_auxiliary,
+ /* 56 */ (const void *)&gLegacyMap_opcode_56_auxiliary,
+ /* 57 */ (const void *)&gLegacyMap_opcode_57_auxiliary,
+ /* 58 */ (const void *)&gLegacyMap_opcode_58_auxiliary,
+ /* 59 */ (const void *)&gLegacyMap_opcode_59_auxiliary,
+ /* 5a */ (const void *)&gLegacyMap_opcode_5a_auxiliary,
+ /* 5b */ (const void *)&gLegacyMap_opcode_5b_auxiliary,
+ /* 5c */ (const void *)&gLegacyMap_opcode_5c_auxiliary,
+ /* 5d */ (const void *)&gLegacyMap_opcode_5d_auxiliary,
+ /* 5e */ (const void *)&gLegacyMap_opcode_5e_auxiliary,
+ /* 5f */ (const void *)&gLegacyMap_opcode_5f_auxiliary,
+ /* 60 */ (const void *)&gLegacyMap_opcode_60_dsize,
+ /* 61 */ (const void *)&gLegacyMap_opcode_61_dsize,
+ /* 62 */ (const void *)&gLegacyMap_opcode_62_modrmmod,
+ /* 63 */ (const void *)&gLegacyMap_opcode_63_auxiliary,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)&gLegacyMap_opcode_68_leaf,
+ /* 69 */ (const void *)&gLegacyMap_opcode_69_leaf,
+ /* 6a */ (const void *)&gLegacyMap_opcode_6a_leaf,
+ /* 6b */ (const void *)&gLegacyMap_opcode_6b_leaf,
+ /* 6c */ (const void *)&gLegacyMap_opcode_6c_auxiliary,
+ /* 6d */ (const void *)&gLegacyMap_opcode_6d_dsize,
+ /* 6e */ (const void *)&gLegacyMap_opcode_6e_auxiliary,
+ /* 6f */ (const void *)&gLegacyMap_opcode_6f_dsize,
+ /* 70 */ (const void *)&gLegacyMap_opcode_70_leaf,
+ /* 71 */ (const void *)&gLegacyMap_opcode_71_leaf,
+ /* 72 */ (const void *)&gLegacyMap_opcode_72_leaf,
+ /* 73 */ (const void *)&gLegacyMap_opcode_73_leaf,
+ /* 74 */ (const void *)&gLegacyMap_opcode_74_leaf,
+ /* 75 */ (const void *)&gLegacyMap_opcode_75_leaf,
+ /* 76 */ (const void *)&gLegacyMap_opcode_76_leaf,
+ /* 77 */ (const void *)&gLegacyMap_opcode_77_leaf,
+ /* 78 */ (const void *)&gLegacyMap_opcode_78_leaf,
+ /* 79 */ (const void *)&gLegacyMap_opcode_79_leaf,
+ /* 7a */ (const void *)&gLegacyMap_opcode_7a_leaf,
+ /* 7b */ (const void *)&gLegacyMap_opcode_7b_leaf,
+ /* 7c */ (const void *)&gLegacyMap_opcode_7c_leaf,
+ /* 7d */ (const void *)&gLegacyMap_opcode_7d_leaf,
+ /* 7e */ (const void *)&gLegacyMap_opcode_7e_leaf,
+ /* 7f */ (const void *)&gLegacyMap_opcode_7f_leaf,
+ /* 80 */ (const void *)&gLegacyMap_opcode_80_modrmreg,
+ /* 81 */ (const void *)&gLegacyMap_opcode_81_modrmreg,
+ /* 82 */ (const void *)&gLegacyMap_opcode_82_modrmreg,
+ /* 83 */ (const void *)&gLegacyMap_opcode_83_modrmreg,
+ /* 84 */ (const void *)&gLegacyMap_opcode_84_leaf,
+ /* 85 */ (const void *)&gLegacyMap_opcode_85_leaf,
+ /* 86 */ (const void *)&gLegacyMap_opcode_86_leaf,
+ /* 87 */ (const void *)&gLegacyMap_opcode_87_leaf,
+ /* 88 */ (const void *)&gLegacyMap_opcode_88_leaf,
+ /* 89 */ (const void *)&gLegacyMap_opcode_89_leaf,
+ /* 8a */ (const void *)&gLegacyMap_opcode_8a_leaf,
+ /* 8b */ (const void *)&gLegacyMap_opcode_8b_leaf,
+ /* 8c */ (const void *)&gLegacyMap_opcode_8c_modrmmod,
+ /* 8d */ (const void *)&gLegacyMap_opcode_8d_modrmmod,
+ /* 8e */ (const void *)&gLegacyMap_opcode_8e_modrmmod,
+ /* 8f */ (const void *)&gLegacyMap_opcode_8f_modrmreg,
+ /* 90 */ (const void *)&gLegacyMap_opcode_90_auxiliary,
+ /* 91 */ (const void *)&gLegacyMap_opcode_91_leaf,
+ /* 92 */ (const void *)&gLegacyMap_opcode_92_leaf,
+ /* 93 */ (const void *)&gLegacyMap_opcode_93_leaf,
+ /* 94 */ (const void *)&gLegacyMap_opcode_94_leaf,
+ /* 95 */ (const void *)&gLegacyMap_opcode_95_leaf,
+ /* 96 */ (const void *)&gLegacyMap_opcode_96_leaf,
+ /* 97 */ (const void *)&gLegacyMap_opcode_97_leaf,
+ /* 98 */ (const void *)&gLegacyMap_opcode_98_dsize,
+ /* 99 */ (const void *)&gLegacyMap_opcode_99_dsize,
+ /* 9a */ (const void *)&gLegacyMap_opcode_9a_leaf,
+ /* 9b */ (const void *)&gLegacyMap_opcode_9b_leaf,
+ /* 9c */ (const void *)&gLegacyMap_opcode_9c_dsize,
+ /* 9d */ (const void *)&gLegacyMap_opcode_9d_dsize,
+ /* 9e */ (const void *)&gLegacyMap_opcode_9e_leaf,
+ /* 9f */ (const void *)&gLegacyMap_opcode_9f_leaf,
+ /* a0 */ (const void *)&gLegacyMap_opcode_a0_leaf,
+ /* a1 */ (const void *)&gLegacyMap_opcode_a1_auxiliary,
+ /* a2 */ (const void *)&gLegacyMap_opcode_a2_leaf,
+ /* a3 */ (const void *)&gLegacyMap_opcode_a3_leaf,
+ /* a4 */ (const void *)&gLegacyMap_opcode_a4_auxiliary,
+ /* a5 */ (const void *)&gLegacyMap_opcode_a5_dsize,
+ /* a6 */ (const void *)&gLegacyMap_opcode_a6_auxiliary,
+ /* a7 */ (const void *)&gLegacyMap_opcode_a7_dsize,
+ /* a8 */ (const void *)&gLegacyMap_opcode_a8_leaf,
+ /* a9 */ (const void *)&gLegacyMap_opcode_a9_leaf,
+ /* aa */ (const void *)&gLegacyMap_opcode_aa_auxiliary,
+ /* ab */ (const void *)&gLegacyMap_opcode_ab_dsize,
+ /* ac */ (const void *)&gLegacyMap_opcode_ac_auxiliary,
+ /* ad */ (const void *)&gLegacyMap_opcode_ad_dsize,
+ /* ae */ (const void *)&gLegacyMap_opcode_ae_auxiliary,
+ /* af */ (const void *)&gLegacyMap_opcode_af_dsize,
+ /* b0 */ (const void *)&gLegacyMap_opcode_b0_leaf,
+ /* b1 */ (const void *)&gLegacyMap_opcode_b1_leaf,
+ /* b2 */ (const void *)&gLegacyMap_opcode_b2_leaf,
+ /* b3 */ (const void *)&gLegacyMap_opcode_b3_leaf,
+ /* b4 */ (const void *)&gLegacyMap_opcode_b4_leaf,
+ /* b5 */ (const void *)&gLegacyMap_opcode_b5_leaf,
+ /* b6 */ (const void *)&gLegacyMap_opcode_b6_leaf,
+ /* b7 */ (const void *)&gLegacyMap_opcode_b7_leaf,
+ /* b8 */ (const void *)&gLegacyMap_opcode_b8_leaf,
+ /* b9 */ (const void *)&gLegacyMap_opcode_b9_leaf,
+ /* ba */ (const void *)&gLegacyMap_opcode_ba_leaf,
+ /* bb */ (const void *)&gLegacyMap_opcode_bb_leaf,
+ /* bc */ (const void *)&gLegacyMap_opcode_bc_leaf,
+ /* bd */ (const void *)&gLegacyMap_opcode_bd_leaf,
+ /* be */ (const void *)&gLegacyMap_opcode_be_leaf,
+ /* bf */ (const void *)&gLegacyMap_opcode_bf_leaf,
+ /* c0 */ (const void *)&gLegacyMap_opcode_c0_modrmreg,
+ /* c1 */ (const void *)&gLegacyMap_opcode_c1_modrmreg,
+ /* c2 */ (const void *)&gLegacyMap_opcode_c2_leaf,
+ /* c3 */ (const void *)&gLegacyMap_opcode_c3_leaf,
+ /* c4 */ (const void *)&gLegacyMap_opcode_c4_modrmmod,
+ /* c5 */ (const void *)&gLegacyMap_opcode_c5_modrmmod,
+ /* c6 */ (const void *)&gLegacyMap_opcode_c6_modrmreg,
+ /* c7 */ (const void *)&gLegacyMap_opcode_c7_modrmreg,
+ /* c8 */ (const void *)&gLegacyMap_opcode_c8_leaf,
+ /* c9 */ (const void *)&gLegacyMap_opcode_c9_leaf,
+ /* ca */ (const void *)&gLegacyMap_opcode_ca_leaf,
+ /* cb */ (const void *)&gLegacyMap_opcode_cb_leaf,
+ /* cc */ (const void *)&gLegacyMap_opcode_cc_leaf,
+ /* cd */ (const void *)&gLegacyMap_opcode_cd_leaf,
+ /* ce */ (const void *)&gLegacyMap_opcode_ce_leaf,
+ /* cf */ (const void *)&gLegacyMap_opcode_cf_dsize,
+ /* d0 */ (const void *)&gLegacyMap_opcode_d0_modrmreg,
+ /* d1 */ (const void *)&gLegacyMap_opcode_d1_modrmreg,
+ /* d2 */ (const void *)&gLegacyMap_opcode_d2_modrmreg,
+ /* d3 */ (const void *)&gLegacyMap_opcode_d3_modrmreg,
+ /* d4 */ (const void *)&gLegacyMap_opcode_d4_leaf,
+ /* d5 */ (const void *)&gLegacyMap_opcode_d5_leaf,
+ /* d6 */ (const void *)&gLegacyMap_opcode_d6_leaf,
+ /* d7 */ (const void *)&gLegacyMap_opcode_d7_leaf,
+ /* d8 */ (const void *)&gLegacyMap_opcode_d8_modrmreg,
+ /* d9 */ (const void *)&gLegacyMap_opcode_d9_modrmreg,
+ /* da */ (const void *)&gLegacyMap_opcode_da_modrmreg,
+ /* db */ (const void *)&gLegacyMap_opcode_db_modrmreg,
+ /* dc */ (const void *)&gLegacyMap_opcode_dc_modrmreg,
+ /* dd */ (const void *)&gLegacyMap_opcode_dd_modrmreg,
+ /* de */ (const void *)&gLegacyMap_opcode_de_modrmreg,
+ /* df */ (const void *)&gLegacyMap_opcode_df_modrmreg,
+ /* e0 */ (const void *)&gLegacyMap_opcode_e0_leaf,
+ /* e1 */ (const void *)&gLegacyMap_opcode_e1_leaf,
+ /* e2 */ (const void *)&gLegacyMap_opcode_e2_leaf,
+ /* e3 */ (const void *)&gLegacyMap_opcode_e3_asize,
+ /* e4 */ (const void *)&gLegacyMap_opcode_e4_leaf,
+ /* e5 */ (const void *)&gLegacyMap_opcode_e5_leaf,
+ /* e6 */ (const void *)&gLegacyMap_opcode_e6_leaf,
+ /* e7 */ (const void *)&gLegacyMap_opcode_e7_leaf,
+ /* e8 */ (const void *)&gLegacyMap_opcode_e8_leaf,
+ /* e9 */ (const void *)&gLegacyMap_opcode_e9_leaf,
+ /* ea */ (const void *)&gLegacyMap_opcode_ea_leaf,
+ /* eb */ (const void *)&gLegacyMap_opcode_eb_leaf,
+ /* ec */ (const void *)&gLegacyMap_opcode_ec_leaf,
+ /* ed */ (const void *)&gLegacyMap_opcode_ed_leaf,
+ /* ee */ (const void *)&gLegacyMap_opcode_ee_leaf,
+ /* ef */ (const void *)&gLegacyMap_opcode_ef_leaf,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)&gLegacyMap_opcode_f1_leaf,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)&gLegacyMap_opcode_f4_leaf,
+ /* f5 */ (const void *)&gLegacyMap_opcode_f5_leaf,
+ /* f6 */ (const void *)&gLegacyMap_opcode_f6_modrmreg,
+ /* f7 */ (const void *)&gLegacyMap_opcode_f7_modrmreg,
+ /* f8 */ (const void *)&gLegacyMap_opcode_f8_leaf,
+ /* f9 */ (const void *)&gLegacyMap_opcode_f9_leaf,
+ /* fa */ (const void *)&gLegacyMap_opcode_fa_leaf,
+ /* fb */ (const void *)&gLegacyMap_opcode_fb_leaf,
+ /* fc */ (const void *)&gLegacyMap_opcode_fc_leaf,
+ /* fd */ (const void *)&gLegacyMap_opcode_fd_leaf,
+ /* fe */ (const void *)&gLegacyMap_opcode_fe_modrmreg,
+ /* ff */ (const void *)&gLegacyMap_opcode_ff_modrmreg,
+ }
+};
+
+
+#endif
+
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_vex.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_vex.h
new file mode 100644
index 00000000000000..f1be108d9ccc82
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_vex.h
@@ -0,0 +1,14742 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_TABLE_VEX_H
+#define BDX86_TABLE_VEX_H
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2677] // URDMSR Rq,Id
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2681] // UWRMSR Id,Rq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_07_opcode_f8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg,
+ /* 03 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2080] // RDMSR Rq,Id
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4107] // WRMSRNS Id,Rq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_07_opcode_f6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_02_modrmreg,
+ /* 03 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp_03_modrmreg,
+ }
+};
+
+const ND_TABLE_OPCODE gVexMap_mmmmm_07_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)&gVexMap_mmmmm_07_opcode_f6_pp,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2618] // TDPBHF8PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2624] // TDPHBF8PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2625] // TDPHF8PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2617] // TDPBF8PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_05_opcode_fd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2599] // T2RPNTLVWZ1RST1 rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2595] // T2RPNTLVWZ0RST1 rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_05_opcode_f9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2598] // T2RPNTLVWZ1RS rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2594] // T2RPNTLVWZ0RS rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_05_opcode_f8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gVexMap_mmmmm_05_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)&gVexMap_mmmmm_05_opcode_f8_pp,
+ /* f9 */ (const void *)&gVexMap_mmmmm_05_opcode_f9_pp,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)&gVexMap_mmmmm_05_opcode_fd_pp,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2187] // RORX Gy,Ey,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_f0_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_f0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2708] // VAESKEYGENASSIST Vdq,Wdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_df_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_df_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4046] // VSM3RNDS2 Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_de_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_de_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3201] // VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_cf_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_cf_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3203] // VGF2P8AFFINEQB Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_ce_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_ce_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3156] // VFNMSUBSD Vdq,Hdq,Ldq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3155] // VFNMSUBSD Vdq,Hdq,Wsd,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3158] // VFNMSUBSS Vdq,Hdq,Ldq,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3157] // VFNMSUBSS Vdq,Hdq,Wss,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3152] // VFNMSUBPD Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3151] // VFNMSUBPD Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3154] // VFNMSUBPS Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3153] // VFNMSUBPS Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3115] // VFNMADDSD Vdq,Hdq,Ldq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3114] // VFNMADDSD Vdq,Hdq,Wsd,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3117] // VFNMADDSS Vdq,Hdq,Ldq,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3116] // VFNMADDSS Vdq,Hdq,Wss,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3111] // VFNMADDPD Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3110] // VFNMADDPD Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_79_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_79_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3113] // VFNMADDPS Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3112] // VFNMADDPS Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_78_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_78_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3072] // VFMSUBSD Vdq,Hdq,Ldq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3071] // VFMSUBSD Vdq,Hdq,Wsd,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3074] // VFMSUBSS Vdq,Hdq,Ldq,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3073] // VFMSUBSS Vdq,Hdq,Wss,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3068] // VFMSUBPD Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3067] // VFMSUBPD Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3070] // VFMSUBPS Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3069] // VFMSUBPS Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2993] // VFMADDSD Vdq,Hdq,Ldq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2992] // VFMADDSD Vdq,Hdq,Wsd,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2995] // VFMADDSS Vdq,Hdq,Ldq,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2994] // VFMADDSS Vdq,Hdq,Wss,Ldq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2989] // VFMADDPD Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2988] // VFMADDPD Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_69_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_69_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2991] // VFMADDPS Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2990] // VFMADDPS Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_68_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_68_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3502] // VPCMPISTRI Vdq,Wdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_63_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_63_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3503] // VPCMPISTRM Vdq,Wdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_62_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_62_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3492] // VPCMPESTRI Vdq,Wdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_61_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_61_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3493] // VPCMPESTRM Vdq,Wdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_60_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_60_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3064] // VFMSUBADDPD Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3063] // VFMSUBADDPD Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3066] // VFMSUBADDPS Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3065] // VFMSUBADDPS Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3012] // VFMADDSUBPD Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3011] // VFMADDSUBPD Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3014] // VFMADDSUBPS Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3013] // VFMADDSUBPS Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3462] // VPBLENDVB Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2725] // VBLENDVPD Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2726] // VBLENDVPS Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3568] // VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3567] // VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_49_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_49_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3570] // VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3569] // VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_48_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_48_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3557] // VPERM2I128 Vqq,Hqq,Wqq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_46_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_46_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_44_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3479] // VPCLMULQDQ Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_44_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_42_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3385] // VMPSADBW Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_42_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2922] // VDPPD Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_41_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_41_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_40_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2924] // VDPPS Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_40_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2936] // VEXTRACTI128 Wdq,Vqq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_39_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_39_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3215] // VINSERTI128 Vqq,Hqq,Wdq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_38_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_38_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1278] // KSHIFTLQ rKq,mKq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1277] // KSHIFTLD rKd,mKd,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_33_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1279] // KSHIFTLW rKw,mKw,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1276] // KSHIFTLB rKb,mKb,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_32_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1282] // KSHIFTRQ rKq,mKq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1281] // KSHIFTRD rKd,mKd,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_31_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1283] // KSHIFTRW rKw,mKw,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1280] // KSHIFTRB rKb,mKb,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_30_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3655] // VPINSRQ Vdq,Hdq,Ey,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3653] // VPINSRD Vdq,Hdq,Ey,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_22_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_22_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3223] // VINSERTPS Vdq,Hdq,Udq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3222] // VINSERTPS Vdq,Hdq,Md,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_21_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3651] // VPINSRB Vdq,Hdq,Rd,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3650] // VPINSRB Vdq,Hdq,Mb,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_20_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2825] // VCVTPS2PH Wdq,Vqq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2824] // VCVTPS2PH Wq,Vdq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_1d_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_1d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2931] // VEXTRACTF128 Wdq,Vqq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_19_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_19_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3210] // VINSERTF128 Vqq,Hqq,Wdq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_18_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_18_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2944] // VEXTRACTPS Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2943] // VEXTRACTPS Md,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_17_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3611] // VPEXTRQ Ry,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3607] // VPEXTRD Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3610] // VPEXTRQ Mq,Vdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3606] // VPEXTRD Md,Vdq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_16_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3617] // VPEXTRW Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3616] // VPEXTRW Mw,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_15_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3603] // VPEXTRB Ry,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3602] // VPEXTRB Mb,Vdq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_14_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0f_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3446] // VPALIGNR Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0e_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3463] // VPBLENDW Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0d_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2723] // VBLENDPD Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2724] // VBLENDPS Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0b_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3999] // VROUNDSD Vsd,Hsd,Wsd,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0a_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4000] // VROUNDSS Vss,Hss,Wss,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_09_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3997] // VROUNDPD Vx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_09_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_08_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3998] // VROUNDPS Vx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_08_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3556] // VPERM2F128 Vqq,Hqq,Wqq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_06_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_06_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3574] // VPERMILPD Vx,Wx,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_05_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_05_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3578] // VPERMILPS Vx,Wx,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_04_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_04_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3457] // VPBLENDD Vx,Hx,Wx,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_02_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_02_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3582] // VPERMPD Vqq,Wqq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_01_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_01_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3588] // VPERMQ Vqq,Wqq,Ib
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_00_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_00_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gVexMap_mmmmm_03_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp,
+ /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp,
+ /* 02 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp,
+ /* 05 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp,
+ /* 06 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp,
+ /* 09 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp,
+ /* 0a */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp,
+ /* 0b */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp,
+ /* 0c */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp,
+ /* 0d */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp,
+ /* 0e */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp,
+ /* 0f */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp,
+ /* 15 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp,
+ /* 16 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp,
+ /* 17 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp,
+ /* 18 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp,
+ /* 19 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp,
+ /* 21 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp,
+ /* 22 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp,
+ /* 31 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp,
+ /* 32 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp,
+ /* 33 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp,
+ /* 39 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp,
+ /* 41 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp,
+ /* 42 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp,
+ /* 49 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp,
+ /* 4a */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp,
+ /* 4b */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp,
+ /* 4c */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp,
+ /* 5d */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp,
+ /* 5e */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp,
+ /* 5f */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp,
+ /* 60 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp,
+ /* 61 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp,
+ /* 62 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp,
+ /* 63 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp,
+ /* 69 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp,
+ /* 6a */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp,
+ /* 6b */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp,
+ /* 6c */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp,
+ /* 6d */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp,
+ /* 6e */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp,
+ /* 6f */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp,
+ /* 79 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp,
+ /* 7a */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp,
+ /* 7b */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp,
+ /* 7c */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp,
+ /* 7d */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp,
+ /* 7e */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp,
+ /* 7f */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp,
+ /* cf */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp,
+ /* df */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2495] // SHRX Gy,Ey,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2283] // SARX Gy,Ey,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2433] // SHLX Gy,Ey,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 188] // BEXTR Gy,Ey,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1486] // MULX Gy,By,Ey
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f6_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1713] // PDEP Gy,By,Ey
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1715] // PEXT Gy,By,Ey
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 239] // BZHI Gy,Ey,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 202] // BLSI By,Ey
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 206] // BLSMSK By,Ey
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 209] // BLSR By,Ey
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 176] // ANDN Gy,By,Ey
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f2_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 638] // CMPNLEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ef_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 630] // CMPLEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ee_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 640] // CMPNLXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ed_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 632] // CMPLXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ec_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 644] // CMPNPXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_eb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 654] // CMPPXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ea_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 646] // CMPNSXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 666] // CMPSXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 634] // CMPNBEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 626] // CMPBEXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 648] // CMPNZXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 672] // CMPZXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 636] // CMPNCXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 628] // CMPCXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 642] // CMPNOXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 650] // CMPOXADD My,Gy,By
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_df_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2702] // VAESDECLAST Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_df_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_df_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_de_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2700] // VAESDEC Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_de_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_de_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dd_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2706] // VAESENCLAST Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dd_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dc_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2704] // VAESENC Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dc_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2707] // VAESIMC Vdq,Wdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_db_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_db_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4050] // VSM4RNDS4 Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4048] // VSM4KEY4 Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4045] // VSM3MSG2 Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4044] // VSM3MSG1 Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_da_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3547] // VPDPWSUDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3551] // VPDPWUSDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3555] // VPDPWUUDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3545] // VPDPWSUD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3549] // VPDPWUSD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3553] // VPDPWUUD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3205] // VGF2P8MULB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cf_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cf_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4034] // VSHA512MSG2 Vqq,Uqq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4033] // VSHA512MSG1 Vqq,Udq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4035] // VSHA512RNDS2 Vqq,Hqq,Udq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3147] // VFNMSUB231SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3150] // VFNMSUB231SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bf_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bf_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3142] // VFNMSUB231PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3145] // VFNMSUB231PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_be_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_be_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3106] // VFNMADD231SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3109] // VFNMADD231SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bd_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3101] // VFNMADD231PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3104] // VFNMADD231PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bc_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3044] // VFMSUB231SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3047] // VFMSUB231SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bb_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3039] // VFMSUB231PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3042] // VFMSUB231PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ba_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ba_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2982] // VFMADD231SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2985] // VFMADD231SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b9_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2977] // VFMADD231PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2980] // VFMADD231PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b8_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3059] // VFMSUBADD231PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3062] // VFMSUBADD231PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b7_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3007] // VFMADDSUB231PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3010] // VFMADDSUB231PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3675] // VPMADD52HUQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b5_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3677] // VPMADD52LUQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b4_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2719] // VBCSTNEBF162PS Vx,Mw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2720] // VBCSTNESH2PS Vx,Mw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2786] // VCVTNEOBF162PS Vx,Mx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2784] // VCVTNEEBF162PS Vx,Mx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2785] // VCVTNEEPH2PS Vx,Mx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2787] // VCVTNEOPH2PS Vx,Mx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3136] // VFNMSUB213SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3139] // VFNMSUB213SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_af_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_af_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3131] // VFNMSUB213PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3134] // VFNMSUB213PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ae_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ae_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3095] // VFNMADD213SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3098] // VFNMADD213SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ad_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ad_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3090] // VFNMADD213PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3093] // VFNMADD213PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ac_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ac_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3033] // VFMSUB213SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3036] // VFMSUB213SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ab_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ab_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3028] // VFMSUB213PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3031] // VFMSUB213PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_aa_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_aa_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2971] // VFMADD213SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2974] // VFMADD213SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a9_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2966] // VFMADD213PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2969] // VFMADD213PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a8_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3054] // VFMSUBADD213PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3057] // VFMSUBADD213PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a7_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3002] // VFMADDSUB213PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3005] // VFMADDSUB213PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a6_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3125] // VFNMSUB132SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3128] // VFNMSUB132SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3120] // VFNMSUB132PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3123] // VFNMSUB132PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3084] // VFNMADD132SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3087] // VFNMADD132SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3079] // VFNMADD132PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3082] // VFNMADD132PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3022] // VFMSUB132SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3025] // VFMSUB132SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9b_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3017] // VFMSUB132PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3020] // VFMSUB132PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9a_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2960] // VFMADD132SD Vdq,Hdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2963] // VFMADD132SS Vdq,Hdq,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_99_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_99_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2955] // VFMADD132PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2958] // VFMADD132PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_98_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_98_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3049] // VFMSUBADD132PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3052] // VFMSUBADD132PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_97_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_97_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2997] // VFMADDSUB132PD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3000] // VFMADDSUB132PS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_96_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_96_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3183] // VGATHERQPD Vx,Mvm64n,Hx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3185] // VGATHERQPS Vdq,Mvm64n,Hdq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_93_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3171] // VGATHERDPD Vx,Mvm32h,Hx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3173] // VGATHERDPS Vx,Mvm32n,Hx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_92_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3625] // VPGATHERQQ Vx,Mvm64n,Hx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3623] // VPGATHERQD Vdq,Mvm64n,Hdq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_91_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3621] // VPGATHERDQ Vx,Mvm32h,Hx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3619] // VPGATHERDD Vx,Mvm32n,Hx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_90_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3685] // VPMASKMOVQ Mx,Hx,Vx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3683] // VPMASKMOVD Mx,Hx,Vx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3684] // VPMASKMOVQ Vx,Hx,Mx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3682] // VPMASKMOVD Vx,Hx,Mx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3477] // VPBROADCASTW Vx,Ww
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_79_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_79_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3466] // VPBROADCASTB Vx,Wb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_78_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_78_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2793] // VCVTNEPS2BF16 Vx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_72_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_72_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2600] // T2RPNTLVWZ1T1 rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2596] // T2RPNTLVWZ0T1 rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2597] // T2RPNTLVWZ1 rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2593] // T2RPNTLVWZ0 rTt+1,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2653] // TTDPFP16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2652] // TTDPBF16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2601] // TCMMIMFP16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2602] // TCMMRLFP16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2650] // TTCMMIMFP16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2651] // TTCMMRLFP16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2604] // TCONJTFP16 rTt,mTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2603] // TCONJTCMMIMFP16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2655] // TTRANSPOSED rTt,mTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2619] // TDPBSSD rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2620] // TDPBSUD rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2621] // TDPBUSD rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2622] // TDPBUUD rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2623] // TDPFP16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2616] // TDPBF16PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2733] // VBROADCASTI128 Vqq,Mdq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3474] // VPBROADCASTQ Vx,Wq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_59_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_59_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_59_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3469] // VPBROADCASTD Vx,Wd
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_58_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_58_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_58_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3543] // VPDPWSSDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_53_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_53_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_53_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3541] // VPDPWSSD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_52_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_52_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_52_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3527] // VPDPBSSDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3531] // VPDPBSUDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3535] // VPDPBUSDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3539] // VPDPBUUDS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_51_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_00_w,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_01_w,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_02_w,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3525] // VPDPBSSD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_03_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3529] // VPDPBSUD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_02_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3533] // VPDPBUSD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3537] // VPDPBUUD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_50_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_00_w,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_01_w,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_02_w,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_03_w,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2636] // TILELOADD rTt,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2645] // TILESTORED Mt,rTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2640] // TILELOADDT1 rTt,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_4b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2637] // TILELOADDRS rTt,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2638] // TILELOADDRST1 rTt,Mt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_4a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2646] // TILEZERO rTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_RM gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2527] // STTILECFG Moq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2643] // TILERELEASE
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_RM gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm =
+{
+ ND_ILUT_MODRM_RM,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1306] // LDTILECFG Moq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_49_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2648] // TMMULTF32PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2654] // TTMMULTF32PS rTt,mTt,vTt
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_48_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3881] // VPSLLVQ Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3879] // VPSLLVD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_47_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_47_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3894] // VPSRAVD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_46_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_46_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_46_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3914] // VPSRLVQ Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3912] // VPSRLVD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_45_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_45_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_41_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3641] // VPHMINPOSUW Vdq,Wdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_41_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_41_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_41_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_41_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_40_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3786] // VPMULLD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_40_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_40_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3f_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3696] // VPMAXUD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3f_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3e_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3699] // VPMAXUW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3e_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3d_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3689] // VPMAXSD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3d_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3687] // VPMAXSB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3c_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3b_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3710] // VPMINUD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3b_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3a_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3713] // VPMINUW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3a_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_39_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3703] // VPMINSD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_39_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_39_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_38_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3701] // VPMINSB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_38_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_38_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_37_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3499] // VPCMPGTQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_37_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_37_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3560] // VPERMD Vqq,Hqq,Wqq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_36_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_36_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3770] // VPMOVZXDQ Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3769] // VPMOVZXDQ Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_35_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_35_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3776] // VPMOVZXWQ Vqq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3775] // VPMOVZXWQ Vdq,Wd
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_34_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_34_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3773] // VPMOVZXWD Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3772] // VPMOVZXWD Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_33_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_33_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3764] // VPMOVZXBQ Vqq,Wd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3763] // VPMOVZXBQ Vdq,Ww
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_32_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_32_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3761] // VPMOVZXBD Vqq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3760] // VPMOVZXBD Vdq,Wd
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_31_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_31_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3767] // VPMOVZXBW Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3766] // VPMOVZXBW Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_30_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_30_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3228] // VMASKMOVPD Mx,Hx,Vx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3230] // VMASKMOVPS Mx,Hx,Vx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3227] // VMASKMOVPD Vx,Hx,Mx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3229] // VMASKMOVPS Vx,Hx,Mx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2b_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3426] // VPACKUSDW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2b_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3329] // VMOVNTDQA Vx,Mx
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_29_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3489] // VPCMPEQQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_29_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_29_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_28_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3778] // VPMULDQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_28_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_28_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3744] // VPMOVSXDQ Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3743] // VPMOVSXDQ Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_25_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_25_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3750] // VPMOVSXWQ Vqq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3749] // VPMOVSXWQ Vdq,Wd
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_24_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_24_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3747] // VPMOVSXWD Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3746] // VPMOVSXWD Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_23_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_23_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3738] // VPMOVSXBQ Vqq,Wd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3737] // VPMOVSXBQ Vdq,Ww
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_22_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_22_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3735] // VPMOVSXBD Vqq,Wq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3734] // VPMOVSXBD Vdq,Wd
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_21_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_21_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3741] // VPMOVSXBW Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3740] // VPMOVSXBW Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_20_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_20_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1e_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3417] // VPABSD Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1e_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1d_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3420] // VPABSW Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1d_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3415] // VPABSB Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1c_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2727] // VBROADCASTF128 Vqq,Mdq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2740] // VBROADCASTSD Vqq,Wsd
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_19_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_19_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_19_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2742] // VBROADCASTSS Vx,Wss
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_18_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_18_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_18_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_17_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3938] // VPTEST Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_17_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_17_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3585] // VPERMPS Vqq,Hqq,Wqq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_16_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_16_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2809] // VCVTPH2PS Vqq,Wdq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2808] // VCVTPH2PS Vdq,Wq
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_13_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_13_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0f_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4074] // VTESTPD Vx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0f_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0f_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0f_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0e_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4075] // VTESTPS Vx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0e_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0e_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0e_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0d_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3573] // VPERMILPD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0d_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0d_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0d_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3577] // VPERMILPS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0c_pp_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0c_pp_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0b_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3780] // VPMULHRSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0b_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0a_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3866] // VPSIGND Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0a_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_09_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3867] // VPSIGNW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_09_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_09_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_08_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3865] // VPSIGNB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_08_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_08_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_07_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3645] // VPHSUBSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_07_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_07_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_06_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3643] // VPHSUBD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_06_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_06_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_05_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3646] // VPHSUBW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_05_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_05_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_04_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3679] // VPMADDUBSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_04_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_04_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_03_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3631] // VPHADDSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_03_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_03_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_02_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3629] // VPHADDD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_02_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_02_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_01_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3638] // VPHADDW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_01_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_01_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_00_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3857] // VPSHUFB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_00_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_00_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_OPCODE gVexMap_mmmmm_02_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_00_pp,
+ /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_01_pp,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_02_pp,
+ /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_03_pp,
+ /* 04 */ (const void *)&gVexMap_mmmmm_02_opcode_04_pp,
+ /* 05 */ (const void *)&gVexMap_mmmmm_02_opcode_05_pp,
+ /* 06 */ (const void *)&gVexMap_mmmmm_02_opcode_06_pp,
+ /* 07 */ (const void *)&gVexMap_mmmmm_02_opcode_07_pp,
+ /* 08 */ (const void *)&gVexMap_mmmmm_02_opcode_08_pp,
+ /* 09 */ (const void *)&gVexMap_mmmmm_02_opcode_09_pp,
+ /* 0a */ (const void *)&gVexMap_mmmmm_02_opcode_0a_pp,
+ /* 0b */ (const void *)&gVexMap_mmmmm_02_opcode_0b_pp,
+ /* 0c */ (const void *)&gVexMap_mmmmm_02_opcode_0c_pp,
+ /* 0d */ (const void *)&gVexMap_mmmmm_02_opcode_0d_pp,
+ /* 0e */ (const void *)&gVexMap_mmmmm_02_opcode_0e_pp,
+ /* 0f */ (const void *)&gVexMap_mmmmm_02_opcode_0f_pp,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp,
+ /* 17 */ (const void *)&gVexMap_mmmmm_02_opcode_17_pp,
+ /* 18 */ (const void *)&gVexMap_mmmmm_02_opcode_18_pp,
+ /* 19 */ (const void *)&gVexMap_mmmmm_02_opcode_19_pp,
+ /* 1a */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)&gVexMap_mmmmm_02_opcode_1c_pp,
+ /* 1d */ (const void *)&gVexMap_mmmmm_02_opcode_1d_pp,
+ /* 1e */ (const void *)&gVexMap_mmmmm_02_opcode_1e_pp,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp,
+ /* 21 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp,
+ /* 22 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp,
+ /* 23 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp,
+ /* 24 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp,
+ /* 25 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)&gVexMap_mmmmm_02_opcode_28_pp,
+ /* 29 */ (const void *)&gVexMap_mmmmm_02_opcode_29_pp,
+ /* 2a */ (const void *)&gVexMap_mmmmm_02_opcode_2a_pp,
+ /* 2b */ (const void *)&gVexMap_mmmmm_02_opcode_2b_pp,
+ /* 2c */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp,
+ /* 2d */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp,
+ /* 2e */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp,
+ /* 2f */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp,
+ /* 30 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp,
+ /* 31 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp,
+ /* 32 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp,
+ /* 33 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp,
+ /* 34 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp,
+ /* 35 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp,
+ /* 36 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp,
+ /* 37 */ (const void *)&gVexMap_mmmmm_02_opcode_37_pp,
+ /* 38 */ (const void *)&gVexMap_mmmmm_02_opcode_38_pp,
+ /* 39 */ (const void *)&gVexMap_mmmmm_02_opcode_39_pp,
+ /* 3a */ (const void *)&gVexMap_mmmmm_02_opcode_3a_pp,
+ /* 3b */ (const void *)&gVexMap_mmmmm_02_opcode_3b_pp,
+ /* 3c */ (const void *)&gVexMap_mmmmm_02_opcode_3c_pp,
+ /* 3d */ (const void *)&gVexMap_mmmmm_02_opcode_3d_pp,
+ /* 3e */ (const void *)&gVexMap_mmmmm_02_opcode_3e_pp,
+ /* 3f */ (const void *)&gVexMap_mmmmm_02_opcode_3f_pp,
+ /* 40 */ (const void *)&gVexMap_mmmmm_02_opcode_40_pp,
+ /* 41 */ (const void *)&gVexMap_mmmmm_02_opcode_41_pp,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp,
+ /* 46 */ (const void *)&gVexMap_mmmmm_02_opcode_46_pp,
+ /* 47 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp,
+ /* 48 */ (const void *)&gVexMap_mmmmm_02_opcode_48_pp,
+ /* 49 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp,
+ /* 4a */ (const void *)&gVexMap_mmmmm_02_opcode_4a_pp,
+ /* 4b */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp,
+ /* 51 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp,
+ /* 52 */ (const void *)&gVexMap_mmmmm_02_opcode_52_pp,
+ /* 53 */ (const void *)&gVexMap_mmmmm_02_opcode_53_pp,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)&gVexMap_mmmmm_02_opcode_58_pp,
+ /* 59 */ (const void *)&gVexMap_mmmmm_02_opcode_59_pp,
+ /* 5a */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp,
+ /* 5f */ (const void *)&gVexMap_mmmmm_02_opcode_5f_pp,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)&gVexMap_mmmmm_02_opcode_6b_pp,
+ /* 6c */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)&gVexMap_mmmmm_02_opcode_6e_pp,
+ /* 6f */ (const void *)&gVexMap_mmmmm_02_opcode_6f_pp,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp,
+ /* 79 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp,
+ /* 91 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp,
+ /* 92 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp,
+ /* 93 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp,
+ /* 97 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp,
+ /* 98 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp,
+ /* 99 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp,
+ /* 9a */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp,
+ /* 9b */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp,
+ /* 9c */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp,
+ /* 9d */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp,
+ /* 9e */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp,
+ /* 9f */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp,
+ /* a7 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp,
+ /* a8 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp,
+ /* a9 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp,
+ /* aa */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp,
+ /* ab */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp,
+ /* ac */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp,
+ /* ad */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp,
+ /* ae */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp,
+ /* af */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp,
+ /* b0 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp,
+ /* b1 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp,
+ /* b5 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp,
+ /* b6 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp,
+ /* b7 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp,
+ /* b8 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp,
+ /* b9 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp,
+ /* ba */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp,
+ /* bb */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp,
+ /* bc */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp,
+ /* bd */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp,
+ /* be */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp,
+ /* bf */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp,
+ /* cc */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp,
+ /* cd */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp,
+ /* d3 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp,
+ /* db */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp,
+ /* dc */ (const void *)&gVexMap_mmmmm_02_opcode_dc_pp,
+ /* dd */ (const void *)&gVexMap_mmmmm_02_opcode_dd_pp,
+ /* de */ (const void *)&gVexMap_mmmmm_02_opcode_de_pp,
+ /* df */ (const void *)&gVexMap_mmmmm_02_opcode_df_pp,
+ /* e0 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp,
+ /* e1 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp,
+ /* e2 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp,
+ /* e3 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp,
+ /* e4 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp,
+ /* e5 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp,
+ /* e6 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp,
+ /* e7 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp,
+ /* e8 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp,
+ /* e9 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp,
+ /* ea */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp,
+ /* eb */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp,
+ /* ec */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp,
+ /* ed */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp,
+ /* ee */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp,
+ /* ef */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp,
+ /* f3 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp,
+ /* f6 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp,
+ /* f7 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fe_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3432] // VPADDD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fe_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fe_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fd_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3444] // VPADDW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fd_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fc_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3430] // VPADDB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fc_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fb_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3925] // VPSUBQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fb_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fa_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3923] // VPSUBD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fa_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fa_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f9_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3935] // VPSUBW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f9_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f8_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3921] // VPSUBB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f8_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3226] // VMASKMOVDQU Vdq,Udq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f6_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3823] // VPSADBW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f6_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f5_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3681] // VPMADDWD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f5_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f4_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3792] // VPMULUDQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f4_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f3_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3877] // VPSLLQ Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f3_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f2_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3871] // VPSLLD Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f2_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f1_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3886] // VPSLLW Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f1_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3224] // VLDDQU Vx,Mx
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ef_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3963] // VPXOR Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ef_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ef_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ee_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3692] // VPMAXSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ee_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ee_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ed_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3438] // VPADDSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ed_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ed_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ec_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3436] // VPADDSB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ec_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ec_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_eb_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3797] // VPOR Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_eb_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_eb_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ea_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3706] // VPMINSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ea_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ea_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e9_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3929] // VPSUBSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e9_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e8_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3927] // VPSUBSB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e8_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3327] // VMOVNTDQ Mx,Vx
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2795] // VCVTPD2DQ Vdq,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2772] // VCVTDQ2PD Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2771] // VCVTDQ2PD Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_e6_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_02_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_02_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2858] // VCVTTPD2DQ Vdq,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_02_l,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e5_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3784] // VPMULHW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e5_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e4_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3782] // VPMULHUW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e4_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e3_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3456] // VPAVGW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e3_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e2_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3890] // VPSRAD Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e2_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e1_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3900] // VPSRAW Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e1_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e0_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3454] // VPAVGB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e0_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_df_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3449] // VPANDN Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_df_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_df_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_de_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3694] // VPMAXUB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_de_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_de_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dd_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3442] // VPADDUSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dd_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_dd_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dc_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3440] // VPADDUSB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dc_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_dc_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_db_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3447] // VPAND Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_db_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_db_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_da_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3708] // VPMINUB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_da_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_da_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d9_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3933] // VPSUBUSW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d9_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d9_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d8_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3931] // VPSUBUSB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d8_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d8_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3722] // VPMOVMSKB Gy,Ux
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d7_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d6_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3341] // VMOVQ Wq,Vdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_d6_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_d6_pp_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d6_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d5_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3789] // VPMULLW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d5_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d4_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3434] // VPADDQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d4_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d3_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3910] // VPSRLQ Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d3_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d3_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d2_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3904] // VPSRLD Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d2_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d1_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3919] // VPSRLW Vx,Hx,Wdq
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d1_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d1_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2698] // VADDSUBPS Vps,Hps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2697] // VADDSUBPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d0_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d0_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_d0_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4041] // VSHUFPD Vpd,Hpd,Wpd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4043] // VSHUFPS Vps,Hps,Wps,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c6_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c6_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c6_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3615] // VPEXTRW Gy,Udq,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c5_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3659] // VPINSRW Vdq,Hdq,Rd,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3658] // VPINSRW Vdq,Hdq,Mw,Ib
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c4_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2750] // VCMPSD Vsd,Hsd,Wsd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2753] // VCMPSS Vss,Hss,Wss,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2745] // VCMPPD Vpd,Hpd,Wpd,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2748] // VCMPPS Vss,Hss,Wss,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c2_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 555] // CLEVICT0 M?
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2505] // SPFLT Ry
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 556] // CLEVICT1 M?
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 874] // DELAY Ry
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4062] // VSTMXCSR Md
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3225] // VLDMXCSR Md
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ae_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1285] // KTESTD rKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1284] // KTESTB rKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1286] // KTESTQ rKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1287] // KTESTW rKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_99_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1272] // KORTESTD rKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1271] // KORTESTB rKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1273] // KORTESTQ rKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1274] // KORTESTW rKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_98_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1253] // KMOVQ Gy,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1243] // KMOVD Gy,mKd
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1233] // KMOVB Gy,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1263] // KMOVW Gy,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_93_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1252] // KMOVQ rKq,Ry
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1242] // KMOVD rKd,Ry
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1232] // KMOVB rKb,Ry
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1262] // KMOVW rKw,Ry
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_92_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1241] // KMOVD Md,rKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1231] // KMOVB Mb,rKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1251] // KMOVQ Mq,rKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1261] // KMOVW Mw,rKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_91_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1240] // KMOVD rKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1230] // KMOVB rKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1239] // KMOVD rKd,Md
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1229] // KMOVB rKb,Mb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1250] // KMOVQ rKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1260] // KMOVW rKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1249] // KMOVQ rKq,Mq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1259] // KMOVW rKw,Mw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_90_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3295] // VMOVDQU Wx,Vx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3289] // VMOVDQA Wx,Vx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7f_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_7f_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_02_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3340] // VMOVQ Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_02_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_02_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3339] // VMOVQ Ey,Vq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3282] // VMOVD Ey,Vd
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_02_l,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3209] // VHSUBPS Vps,Hps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3208] // VHSUBPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7d_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_7d_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3207] // VHADDPS Vps,Hps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3206] // VHADDPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7c_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_7c_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4096] // VZEROALL
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4097] // VZEROUPPER
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_77_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp_00_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp_00_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_77_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_76_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3487] // VPCMPEQD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_76_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_76_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_75_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3491] // VPCMPEQW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_75_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_75_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_74_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3485] // VPCMPEQB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_74_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_74_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3873] // VPSLLDQ Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3876] // VPSLLQ Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3906] // VPSRLDQ Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3909] // VPSRLQ Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_73_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3870] // VPSLLD Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3889] // VPSRAD Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3903] // VPSRLD Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_72_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3885] // VPSLLW Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3899] // VPSRAW Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3918] // VPSRLW Hx,Ux,Ib
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_71_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3864] // VPSHUFLW Vx,Wx,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3862] // VPSHUFHW Vx,Wx,Ib
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3860] // VPSHUFD Vx,Wx,Ib
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_70_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3294] // VMOVDQU Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3288] // VMOVDQA Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6f_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_6f_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3338] // VMOVQ Vdq,Ey
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3281] // VMOVD Vdq,Ey
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi =
+{
+ ND_ILUT_EX_WI,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_6e_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6d_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3952] // VPUNPCKHQDQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6d_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3960] // VPUNPCKLQDQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6c_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6b_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3422] // VPACKSSDW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6b_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6a_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3950] // VPUNPCKHDQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6a_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_69_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3954] // VPUNPCKHWD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_69_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_69_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_68_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3948] // VPUNPCKHBW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_68_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_68_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_67_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3428] // VPACKUSWB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_67_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_67_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_66_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3497] // VPCMPGTD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_66_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_66_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_65_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3501] // VPCMPGTW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_65_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_65_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_64_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3495] // VPCMPGTB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_64_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_64_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_63_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3424] // VPACKSSWB Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_63_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_63_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_62_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3958] // VPUNPCKLDQ Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_62_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_62_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_61_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3962] // VPUNPCKLWD Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_61_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_61_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_60_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3956] // VPUNPCKLBW Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_60_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_60_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3238] // VMAXSD Vsd,Hsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3241] // VMAXSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3233] // VMAXPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3236] // VMAXPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2917] // VDIVSD Vsd,Hsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2920] // VDIVSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2912] // VDIVPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2915] // VDIVPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3261] // VMINSD Vsd,Hsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3264] // VMINSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3256] // VMINPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3259] // VMINPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4070] // VSUBSD Vsd,Hsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4073] // VSUBSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4065] // VSUBPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4068] // VSUBPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2875] // VCVTTPS2DQ Vps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2817] // VCVTPS2DQ Vps,Wps
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2775] // VCVTDQ2PS Vps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2837] // VCVTSD2SS Vss,Hx,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2850] // VCVTSS2SD Vsd,Hx,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2799] // VCVTPD2PS Vdq,Wqq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2798] // VCVTPD2PS Vdq,Wdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_01_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_01_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2822] // VCVTPS2PD Vqq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2821] // VCVTPS2PD Vpd,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_00_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_00_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_01_l,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3399] // VMULSD Vsd,Hsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3402] // VMULSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3394] // VMULPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3397] // VMULPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_59_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2693] // VADDSD Vsd,Hsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2696] // VADDSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2688] // VADDPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2691] // VADDPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_58_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4093] // VXORPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4095] // VXORPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_57_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_57_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_57_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3407] // VORPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3409] // VORPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_56_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_56_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_56_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2712] // VANDNPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2714] // VANDNPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_55_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_55_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_55_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2716] // VANDPD Vpd,Hpd,Wpd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2718] // VANDPS Vps,Hps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_54_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_54_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_54_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3982] // VRCPSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3980] // VRCPPS Vps,Wps
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_53_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_53_pp_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_53_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4013] // VRSQRTSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4011] // VRSQRTPS Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_52_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_52_pp_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_52_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4058] // VSQRTSD Vsd,Hsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4061] // VSQRTSS Vss,Hss,Wss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4053] // VSQRTPD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4056] // VSQRTPS Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_51_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3324] // VMOVMSKPD Gy,Ux
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3325] // VMOVMSKPS Gy,Ux
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_50_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1288] // KUNPCKBW rKw,vKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1289] // KUNPCKDQ rKq,vKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1290] // KUNPCKWD rKd,vKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_4b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1211] // KADDD rKd,vKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1210] // KADDB rKb,vKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1212] // KADDQ rKq,vKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1213] // KADDW rKw,vKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_4a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1223] // KMERGE2L1L rKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_49_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1222] // KMERGE2L1H rKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_48_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1296] // KXORD rKd,vKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1295] // KXORB rKb,vKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1297] // KXORQ rKq,vKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1298] // KXORW rKw,vKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_47_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1292] // KXNORD rKd,vKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1291] // KXNORB rKb,vKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1293] // KXNORQ rKq,vKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1294] // KXNORW rKw,vKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_46_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1269] // KORD rKd,vKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1268] // KORB rKb,vKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1270] // KORQ rKq,vKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1275] // KORW rKw,vKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_45_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1265] // KNOTD rKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1264] // KNOTB rKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1266] // KNOTQ rKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1267] // KNOTW rKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_44_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1217] // KANDND rKd,vKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1216] // KANDNB rKb,vKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1218] // KANDNQ rKq,vKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1219] // KANDNW rKw,vKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_42_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1215] // KANDD rKd,vKd,mKd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1214] // KANDB rKb,vKb,mKb
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1220] // KANDQ rKq,vKq,mKq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1221] // KANDW rKw,vKw,mKw
+};
+
+const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_01_leaf,
+ }
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_41_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2755] // VCOMISD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2758] // VCOMISS Vss,Wss
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2f_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2f_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_2f_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4077] // VUCOMISD Vsd,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4080] // VUCOMISS Vss,Wss
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2e_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2e_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_2e_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2835] // VCVTSD2SI Gy,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2853] // VCVTSS2SI Gy,Wss
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2d_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_2d_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_2d_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2886] // VCVTTSD2SI Gy,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2893] // VCVTTSS2SI Gy,Wss
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2c_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_2c_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_2c_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3331] // VMOVNTPD Mx,Vx
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3333] // VMOVNTPS Mx,Vx
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2b_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2845] // VCVTSI2SD Vsd,Hsd,Ey
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2848] // VCVTSI2SS Vss,Hss,Ey
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2a_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_2a_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_2a_pp_03_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3272] // VMOVAPD Wx,Vx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3276] // VMOVAPS Wx,Vx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_29_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_29_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_29_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3271] // VMOVAPD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3275] // VMOVAPS Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_28_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_28_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_28_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3309] // VMOVHPD Mq,Vdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3313] // VMOVHPS Mq,Vdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_17_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3359] // VMOVSHDUP Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3308] // VMOVHPD Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3315] // VMOVLHPS Vdq,Hdq,Udq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3312] // VMOVHPS Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_16_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_02_leaf,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4085] // VUNPCKHPD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4087] // VUNPCKHPS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_15_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_15_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_15_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4089] // VUNPCKLPD Vx,Hx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 4091] // VUNPCKLPS Vx,Hx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_14_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_14_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_14_pp_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3319] // VMOVLPD Mq,Vdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3323] // VMOVLPS Mq,Vdq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_13_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3287] // VMOVDDUP Vqq,Wqq
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3286] // VMOVDDUP Vdq,Wq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_03_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_03_l_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_03_l_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3361] // VMOVSLDUP Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3318] // VMOVLPD Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l,
+ /* 01 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3305] // VMOVHLPS Vdq,Hdq,Udq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3322] // VMOVLPS Vdq,Hdq,Mq
+};
+
+const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l =
+{
+ ND_ILUT_EX_L,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_leaf,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l,
+ }
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_12_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_02_leaf,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_03_l,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3352] // VMOVSD Usd,Hsd,Vsd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3353] // VMOVSD Mq,Vsd
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3368] // VMOVSS Uss,Hss,Vss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3369] // VMOVSS Md,Vss
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3373] // VMOVUPD Wx,Vx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3377] // VMOVUPS Wx,Vx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_11_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3350] // VMOVSD Vdq,Hdq,Usd
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3351] // VMOVSD Vdq,Mq
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3366] // VMOVSS Vdq,Hdq,Uss
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3367] // VMOVSS Vdq,Md
+};
+
+const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3372] // VMOVUPD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3376] // VMOVUPS Vx,Wx
+};
+
+const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_10_pp =
+{
+ ND_ILUT_EX_PP,
+ {
+ /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_00_leaf,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_01_leaf,
+ /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod,
+ /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod,
+ }
+};
+
+const ND_TABLE_OPCODE gVexMap_mmmmm_01_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp,
+ /* 11 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp,
+ /* 12 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp,
+ /* 13 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp,
+ /* 14 */ (const void *)&gVexMap_mmmmm_01_opcode_14_pp,
+ /* 15 */ (const void *)&gVexMap_mmmmm_01_opcode_15_pp,
+ /* 16 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp,
+ /* 17 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)&gVexMap_mmmmm_01_opcode_28_pp,
+ /* 29 */ (const void *)&gVexMap_mmmmm_01_opcode_29_pp,
+ /* 2a */ (const void *)&gVexMap_mmmmm_01_opcode_2a_pp,
+ /* 2b */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp,
+ /* 2c */ (const void *)&gVexMap_mmmmm_01_opcode_2c_pp,
+ /* 2d */ (const void *)&gVexMap_mmmmm_01_opcode_2d_pp,
+ /* 2e */ (const void *)&gVexMap_mmmmm_01_opcode_2e_pp,
+ /* 2f */ (const void *)&gVexMap_mmmmm_01_opcode_2f_pp,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp,
+ /* 42 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp,
+ /* 45 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp,
+ /* 46 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp,
+ /* 47 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp,
+ /* 48 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp,
+ /* 49 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp,
+ /* 4a */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp,
+ /* 4b */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp,
+ /* 51 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp,
+ /* 52 */ (const void *)&gVexMap_mmmmm_01_opcode_52_pp,
+ /* 53 */ (const void *)&gVexMap_mmmmm_01_opcode_53_pp,
+ /* 54 */ (const void *)&gVexMap_mmmmm_01_opcode_54_pp,
+ /* 55 */ (const void *)&gVexMap_mmmmm_01_opcode_55_pp,
+ /* 56 */ (const void *)&gVexMap_mmmmm_01_opcode_56_pp,
+ /* 57 */ (const void *)&gVexMap_mmmmm_01_opcode_57_pp,
+ /* 58 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp,
+ /* 59 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp,
+ /* 5a */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp,
+ /* 5b */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp,
+ /* 5c */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp,
+ /* 5d */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp,
+ /* 5e */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp,
+ /* 5f */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp,
+ /* 60 */ (const void *)&gVexMap_mmmmm_01_opcode_60_pp,
+ /* 61 */ (const void *)&gVexMap_mmmmm_01_opcode_61_pp,
+ /* 62 */ (const void *)&gVexMap_mmmmm_01_opcode_62_pp,
+ /* 63 */ (const void *)&gVexMap_mmmmm_01_opcode_63_pp,
+ /* 64 */ (const void *)&gVexMap_mmmmm_01_opcode_64_pp,
+ /* 65 */ (const void *)&gVexMap_mmmmm_01_opcode_65_pp,
+ /* 66 */ (const void *)&gVexMap_mmmmm_01_opcode_66_pp,
+ /* 67 */ (const void *)&gVexMap_mmmmm_01_opcode_67_pp,
+ /* 68 */ (const void *)&gVexMap_mmmmm_01_opcode_68_pp,
+ /* 69 */ (const void *)&gVexMap_mmmmm_01_opcode_69_pp,
+ /* 6a */ (const void *)&gVexMap_mmmmm_01_opcode_6a_pp,
+ /* 6b */ (const void *)&gVexMap_mmmmm_01_opcode_6b_pp,
+ /* 6c */ (const void *)&gVexMap_mmmmm_01_opcode_6c_pp,
+ /* 6d */ (const void *)&gVexMap_mmmmm_01_opcode_6d_pp,
+ /* 6e */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp,
+ /* 6f */ (const void *)&gVexMap_mmmmm_01_opcode_6f_pp,
+ /* 70 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp,
+ /* 71 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp,
+ /* 72 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp,
+ /* 73 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp,
+ /* 74 */ (const void *)&gVexMap_mmmmm_01_opcode_74_pp,
+ /* 75 */ (const void *)&gVexMap_mmmmm_01_opcode_75_pp,
+ /* 76 */ (const void *)&gVexMap_mmmmm_01_opcode_76_pp,
+ /* 77 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)&gVexMap_mmmmm_01_opcode_7c_pp,
+ /* 7d */ (const void *)&gVexMap_mmmmm_01_opcode_7d_pp,
+ /* 7e */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp,
+ /* 7f */ (const void *)&gVexMap_mmmmm_01_opcode_7f_pp,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp,
+ /* 91 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp,
+ /* 92 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp,
+ /* 93 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp,
+ /* 99 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp,
+ /* c5 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp,
+ /* c6 */ (const void *)&gVexMap_mmmmm_01_opcode_c6_pp,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)&gVexMap_mmmmm_01_opcode_d0_pp,
+ /* d1 */ (const void *)&gVexMap_mmmmm_01_opcode_d1_pp,
+ /* d2 */ (const void *)&gVexMap_mmmmm_01_opcode_d2_pp,
+ /* d3 */ (const void *)&gVexMap_mmmmm_01_opcode_d3_pp,
+ /* d4 */ (const void *)&gVexMap_mmmmm_01_opcode_d4_pp,
+ /* d5 */ (const void *)&gVexMap_mmmmm_01_opcode_d5_pp,
+ /* d6 */ (const void *)&gVexMap_mmmmm_01_opcode_d6_pp,
+ /* d7 */ (const void *)&gVexMap_mmmmm_01_opcode_d7_pp,
+ /* d8 */ (const void *)&gVexMap_mmmmm_01_opcode_d8_pp,
+ /* d9 */ (const void *)&gVexMap_mmmmm_01_opcode_d9_pp,
+ /* da */ (const void *)&gVexMap_mmmmm_01_opcode_da_pp,
+ /* db */ (const void *)&gVexMap_mmmmm_01_opcode_db_pp,
+ /* dc */ (const void *)&gVexMap_mmmmm_01_opcode_dc_pp,
+ /* dd */ (const void *)&gVexMap_mmmmm_01_opcode_dd_pp,
+ /* de */ (const void *)&gVexMap_mmmmm_01_opcode_de_pp,
+ /* df */ (const void *)&gVexMap_mmmmm_01_opcode_df_pp,
+ /* e0 */ (const void *)&gVexMap_mmmmm_01_opcode_e0_pp,
+ /* e1 */ (const void *)&gVexMap_mmmmm_01_opcode_e1_pp,
+ /* e2 */ (const void *)&gVexMap_mmmmm_01_opcode_e2_pp,
+ /* e3 */ (const void *)&gVexMap_mmmmm_01_opcode_e3_pp,
+ /* e4 */ (const void *)&gVexMap_mmmmm_01_opcode_e4_pp,
+ /* e5 */ (const void *)&gVexMap_mmmmm_01_opcode_e5_pp,
+ /* e6 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp,
+ /* e7 */ (const void *)&gVexMap_mmmmm_01_opcode_e7_pp,
+ /* e8 */ (const void *)&gVexMap_mmmmm_01_opcode_e8_pp,
+ /* e9 */ (const void *)&gVexMap_mmmmm_01_opcode_e9_pp,
+ /* ea */ (const void *)&gVexMap_mmmmm_01_opcode_ea_pp,
+ /* eb */ (const void *)&gVexMap_mmmmm_01_opcode_eb_pp,
+ /* ec */ (const void *)&gVexMap_mmmmm_01_opcode_ec_pp,
+ /* ed */ (const void *)&gVexMap_mmmmm_01_opcode_ed_pp,
+ /* ee */ (const void *)&gVexMap_mmmmm_01_opcode_ee_pp,
+ /* ef */ (const void *)&gVexMap_mmmmm_01_opcode_ef_pp,
+ /* f0 */ (const void *)&gVexMap_mmmmm_01_opcode_f0_pp,
+ /* f1 */ (const void *)&gVexMap_mmmmm_01_opcode_f1_pp,
+ /* f2 */ (const void *)&gVexMap_mmmmm_01_opcode_f2_pp,
+ /* f3 */ (const void *)&gVexMap_mmmmm_01_opcode_f3_pp,
+ /* f4 */ (const void *)&gVexMap_mmmmm_01_opcode_f4_pp,
+ /* f5 */ (const void *)&gVexMap_mmmmm_01_opcode_f5_pp,
+ /* f6 */ (const void *)&gVexMap_mmmmm_01_opcode_f6_pp,
+ /* f7 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp,
+ /* f8 */ (const void *)&gVexMap_mmmmm_01_opcode_f8_pp,
+ /* f9 */ (const void *)&gVexMap_mmmmm_01_opcode_f9_pp,
+ /* fa */ (const void *)&gVexMap_mmmmm_01_opcode_fa_pp,
+ /* fb */ (const void *)&gVexMap_mmmmm_01_opcode_fb_pp,
+ /* fc */ (const void *)&gVexMap_mmmmm_01_opcode_fc_pp,
+ /* fd */ (const void *)&gVexMap_mmmmm_01_opcode_fd_pp,
+ /* fe */ (const void *)&gVexMap_mmmmm_01_opcode_fe_pp,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_M gVexMap_mmmmm =
+{
+ ND_ILUT_EX_M,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode,
+ /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode,
+ /* 03 */ (const void *)&gVexMap_mmmmm_03_opcode,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)&gVexMap_mmmmm_05_opcode,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)&gVexMap_mmmmm_07_opcode,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ }
+};
+
+
+#endif
+
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_xop.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_xop.h
new file mode 100644
index 00000000000000..80445c8594c3f3
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_table_xop.h
@@ -0,0 +1,1557 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_TABLE_XOP_H
+#define BDX86_TABLE_XOP_H
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1337] // LWPVAL By,Ed,Id
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1336] // LWPINS By,Ed,Id
+};
+
+const ND_TABLE_MODRM_REG gXopMap_mmmmm_0a_opcode_12_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_0a_opcode_12_modrmreg_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_0a_opcode_12_modrmreg_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_10_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 189] // BEXTR Gy,Ey,Id
+};
+
+const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)&gXopMap_mmmmm_0a_opcode_10_leaf,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)&gXopMap_mmmmm_0a_opcode_12_modrmreg,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)ND_NULL,
+ /* 96 */ (const void *)ND_NULL,
+ /* 97 */ (const void *)ND_NULL,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)ND_NULL,
+ /* c2 */ (const void *)ND_NULL,
+ /* c3 */ (const void *)ND_NULL,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3644] // VPHSUBDQ Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3647] // VPHSUBWD Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3642] // VPHSUBBW Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_db_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3635] // VPHADDUDQ Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3637] // VPHADDUWQ Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3636] // VPHADDUWD Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3633] // VPHADDUBQ Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3632] // VPHADDUBD Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3634] // VPHADDUBW Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_cb_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3630] // VPHADDDQ Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c7_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3640] // VPHADDWQ Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3639] // VPHADDWD Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3627] // VPHADDBQ Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3626] // VPHADDBD Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3628] // VPHADDBW Vdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3833] // VPSHAQ Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3832] // VPSHAQ Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_9b_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_9b_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3831] // VPSHAD Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3830] // VPSHAD Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_9a_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_9a_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3835] // VPSHAW Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3834] // VPSHAW Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_99_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_99_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3829] // VPSHAB Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3828] // VPSHAB Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_98_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_98_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3848] // VPSHLQ Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3847] // VPSHLQ Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_97_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_97_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3839] // VPSHLB Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3840] // VPSHLD Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_96_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_96_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3838] // VPSHLB Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3849] // VPSHLW Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_95_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_95_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3837] // VPSHLB Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3836] // VPSHLB Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_94_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_94_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3818] // VPROTQ Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3817] // VPROTQ Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_93_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_93_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3815] // VPROTD Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3814] // VPROTD Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_92_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_92_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3821] // VPROTW Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3820] // VPROTW Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_91_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_91_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3812] // VPROTB Vdq,Hdq,Wdq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3811] // VPROTB Vdq,Wdq,Hdq
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_90_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_90_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_83_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3168] // VFRCZSD Vdq,Wsd
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_82_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3169] // VFRCZSS Vdq,Wss
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_81_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3166] // VFRCZPD Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_80_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3167] // VFRCZPS Vx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2502] // SLWPCB Ry
+};
+
+const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 1318] // LLWPCB Ry
+};
+
+const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod =
+{
+ ND_ILUT_MODRM_MOD,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod_01_leaf,
+ }
+};
+
+const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_12_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 191] // BLCI By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 193] // BLCMSK By,Ey
+};
+
+const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_02_modrmreg_01_leaf,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)&gXopMap_mmmmm_09_opcode_02_modrmreg_06_leaf,
+ /* 07 */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2592] // T1MSKC By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 203] // BLSIC By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 192] // BLCIC By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 2661] // TZMSK By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 194] // BLCS By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_02_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 199] // BLSFILL By,Ey
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 190] // BLCFILL By,Ey
+};
+
+const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_01_modrmreg =
+{
+ ND_ILUT_MODRM_REG,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_01_leaf,
+ /* 02 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_02_leaf,
+ /* 03 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf,
+ /* 04 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf,
+ /* 05 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf,
+ /* 06 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf,
+ /* 07 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf,
+ }
+};
+
+const ND_TABLE_OPCODE gXopMap_mmmmm_09_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg,
+ /* 02 */ (const void *)&gXopMap_mmmmm_09_opcode_02_modrmreg,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)&gXopMap_mmmmm_09_opcode_80_leaf,
+ /* 81 */ (const void *)&gXopMap_mmmmm_09_opcode_81_leaf,
+ /* 82 */ (const void *)&gXopMap_mmmmm_09_opcode_82_leaf,
+ /* 83 */ (const void *)&gXopMap_mmmmm_09_opcode_83_leaf,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)ND_NULL,
+ /* 86 */ (const void *)ND_NULL,
+ /* 87 */ (const void *)ND_NULL,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)ND_NULL,
+ /* 8f */ (const void *)ND_NULL,
+ /* 90 */ (const void *)&gXopMap_mmmmm_09_opcode_90_w,
+ /* 91 */ (const void *)&gXopMap_mmmmm_09_opcode_91_w,
+ /* 92 */ (const void *)&gXopMap_mmmmm_09_opcode_92_w,
+ /* 93 */ (const void *)&gXopMap_mmmmm_09_opcode_93_w,
+ /* 94 */ (const void *)&gXopMap_mmmmm_09_opcode_94_w,
+ /* 95 */ (const void *)&gXopMap_mmmmm_09_opcode_95_w,
+ /* 96 */ (const void *)&gXopMap_mmmmm_09_opcode_96_w,
+ /* 97 */ (const void *)&gXopMap_mmmmm_09_opcode_97_w,
+ /* 98 */ (const void *)&gXopMap_mmmmm_09_opcode_98_w,
+ /* 99 */ (const void *)&gXopMap_mmmmm_09_opcode_99_w,
+ /* 9a */ (const void *)&gXopMap_mmmmm_09_opcode_9a_w,
+ /* 9b */ (const void *)&gXopMap_mmmmm_09_opcode_9b_w,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)ND_NULL,
+ /* 9f */ (const void *)ND_NULL,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)ND_NULL,
+ /* a3 */ (const void *)ND_NULL,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)ND_NULL,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)ND_NULL,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)ND_NULL,
+ /* c1 */ (const void *)&gXopMap_mmmmm_09_opcode_c1_leaf,
+ /* c2 */ (const void *)&gXopMap_mmmmm_09_opcode_c2_leaf,
+ /* c3 */ (const void *)&gXopMap_mmmmm_09_opcode_c3_leaf,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)&gXopMap_mmmmm_09_opcode_c6_leaf,
+ /* c7 */ (const void *)&gXopMap_mmmmm_09_opcode_c7_leaf,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)&gXopMap_mmmmm_09_opcode_cb_leaf,
+ /* cc */ (const void *)ND_NULL,
+ /* cd */ (const void *)ND_NULL,
+ /* ce */ (const void *)ND_NULL,
+ /* cf */ (const void *)ND_NULL,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)&gXopMap_mmmmm_09_opcode_d1_leaf,
+ /* d2 */ (const void *)&gXopMap_mmmmm_09_opcode_d2_leaf,
+ /* d3 */ (const void *)&gXopMap_mmmmm_09_opcode_d3_leaf,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)&gXopMap_mmmmm_09_opcode_d6_leaf,
+ /* d7 */ (const void *)&gXopMap_mmmmm_09_opcode_d7_leaf,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)&gXopMap_mmmmm_09_opcode_db_leaf,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)&gXopMap_mmmmm_09_opcode_e1_leaf,
+ /* e2 */ (const void *)&gXopMap_mmmmm_09_opcode_e2_leaf,
+ /* e3 */ (const void *)&gXopMap_mmmmm_09_opcode_e3_leaf,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)ND_NULL,
+ /* ed */ (const void *)ND_NULL,
+ /* ee */ (const void *)ND_NULL,
+ /* ef */ (const void *)ND_NULL,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ef_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3519] // VPCOMUQ Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ee_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3518] // VPCOMUD Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ed_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3520] // VPCOMUW Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ec_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3517] // VPCOMUB Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cf_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3516] // VPCOMQ Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ce_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3511] // VPCOMD Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cd_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3521] // VPCOMW Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cc_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3510] // VPCOMB Vdq,Hdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c3_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3816] // VPROTQ Vdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c2_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3813] // VPROTD Vdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c1_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3819] // VPROTW Vdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c0_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3810] // VPROTB Vdq,Wdq,Ib
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_b6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3673] // VPMADCSWD Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a6_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3672] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3801] // VPPERM Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3800] // VPPERM Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_08_opcode_a3_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_08_opcode_a3_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_01_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3481] // VPCMOV Vx,Hx,Lx,Wx
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_00_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3480] // VPCMOV Vx,Hx,Wx,Lx
+};
+
+const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w =
+{
+ ND_ILUT_EX_W,
+ {
+ /* 00 */ (const void *)&gXopMap_mmmmm_08_opcode_a2_w_00_leaf,
+ /* 01 */ (const void *)&gXopMap_mmmmm_08_opcode_a2_w_01_leaf,
+ }
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3663] // VPMACSDQH Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3662] // VPMACSDD Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_97_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3664] // VPMACSDQL Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_96_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3670] // VPMACSWD Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_95_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3671] // VPMACSWW Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8f_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3666] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8e_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3665] // VPMACSSDD Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_87_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3667] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_86_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3668] // VPMACSSWD Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_85_leaf =
+{
+ ND_ILUT_INSTRUCTION,
+ (const void *)&gInstructions[ 3669] // VPMACSSWW Vdq,Hdq,Wdq,Ldq
+};
+
+const ND_TABLE_OPCODE gXopMap_mmmmm_08_opcode =
+{
+ ND_ILUT_OPCODE,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)ND_NULL,
+ /* 09 */ (const void *)ND_NULL,
+ /* 0a */ (const void *)ND_NULL,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ /* 20 */ (const void *)ND_NULL,
+ /* 21 */ (const void *)ND_NULL,
+ /* 22 */ (const void *)ND_NULL,
+ /* 23 */ (const void *)ND_NULL,
+ /* 24 */ (const void *)ND_NULL,
+ /* 25 */ (const void *)ND_NULL,
+ /* 26 */ (const void *)ND_NULL,
+ /* 27 */ (const void *)ND_NULL,
+ /* 28 */ (const void *)ND_NULL,
+ /* 29 */ (const void *)ND_NULL,
+ /* 2a */ (const void *)ND_NULL,
+ /* 2b */ (const void *)ND_NULL,
+ /* 2c */ (const void *)ND_NULL,
+ /* 2d */ (const void *)ND_NULL,
+ /* 2e */ (const void *)ND_NULL,
+ /* 2f */ (const void *)ND_NULL,
+ /* 30 */ (const void *)ND_NULL,
+ /* 31 */ (const void *)ND_NULL,
+ /* 32 */ (const void *)ND_NULL,
+ /* 33 */ (const void *)ND_NULL,
+ /* 34 */ (const void *)ND_NULL,
+ /* 35 */ (const void *)ND_NULL,
+ /* 36 */ (const void *)ND_NULL,
+ /* 37 */ (const void *)ND_NULL,
+ /* 38 */ (const void *)ND_NULL,
+ /* 39 */ (const void *)ND_NULL,
+ /* 3a */ (const void *)ND_NULL,
+ /* 3b */ (const void *)ND_NULL,
+ /* 3c */ (const void *)ND_NULL,
+ /* 3d */ (const void *)ND_NULL,
+ /* 3e */ (const void *)ND_NULL,
+ /* 3f */ (const void *)ND_NULL,
+ /* 40 */ (const void *)ND_NULL,
+ /* 41 */ (const void *)ND_NULL,
+ /* 42 */ (const void *)ND_NULL,
+ /* 43 */ (const void *)ND_NULL,
+ /* 44 */ (const void *)ND_NULL,
+ /* 45 */ (const void *)ND_NULL,
+ /* 46 */ (const void *)ND_NULL,
+ /* 47 */ (const void *)ND_NULL,
+ /* 48 */ (const void *)ND_NULL,
+ /* 49 */ (const void *)ND_NULL,
+ /* 4a */ (const void *)ND_NULL,
+ /* 4b */ (const void *)ND_NULL,
+ /* 4c */ (const void *)ND_NULL,
+ /* 4d */ (const void *)ND_NULL,
+ /* 4e */ (const void *)ND_NULL,
+ /* 4f */ (const void *)ND_NULL,
+ /* 50 */ (const void *)ND_NULL,
+ /* 51 */ (const void *)ND_NULL,
+ /* 52 */ (const void *)ND_NULL,
+ /* 53 */ (const void *)ND_NULL,
+ /* 54 */ (const void *)ND_NULL,
+ /* 55 */ (const void *)ND_NULL,
+ /* 56 */ (const void *)ND_NULL,
+ /* 57 */ (const void *)ND_NULL,
+ /* 58 */ (const void *)ND_NULL,
+ /* 59 */ (const void *)ND_NULL,
+ /* 5a */ (const void *)ND_NULL,
+ /* 5b */ (const void *)ND_NULL,
+ /* 5c */ (const void *)ND_NULL,
+ /* 5d */ (const void *)ND_NULL,
+ /* 5e */ (const void *)ND_NULL,
+ /* 5f */ (const void *)ND_NULL,
+ /* 60 */ (const void *)ND_NULL,
+ /* 61 */ (const void *)ND_NULL,
+ /* 62 */ (const void *)ND_NULL,
+ /* 63 */ (const void *)ND_NULL,
+ /* 64 */ (const void *)ND_NULL,
+ /* 65 */ (const void *)ND_NULL,
+ /* 66 */ (const void *)ND_NULL,
+ /* 67 */ (const void *)ND_NULL,
+ /* 68 */ (const void *)ND_NULL,
+ /* 69 */ (const void *)ND_NULL,
+ /* 6a */ (const void *)ND_NULL,
+ /* 6b */ (const void *)ND_NULL,
+ /* 6c */ (const void *)ND_NULL,
+ /* 6d */ (const void *)ND_NULL,
+ /* 6e */ (const void *)ND_NULL,
+ /* 6f */ (const void *)ND_NULL,
+ /* 70 */ (const void *)ND_NULL,
+ /* 71 */ (const void *)ND_NULL,
+ /* 72 */ (const void *)ND_NULL,
+ /* 73 */ (const void *)ND_NULL,
+ /* 74 */ (const void *)ND_NULL,
+ /* 75 */ (const void *)ND_NULL,
+ /* 76 */ (const void *)ND_NULL,
+ /* 77 */ (const void *)ND_NULL,
+ /* 78 */ (const void *)ND_NULL,
+ /* 79 */ (const void *)ND_NULL,
+ /* 7a */ (const void *)ND_NULL,
+ /* 7b */ (const void *)ND_NULL,
+ /* 7c */ (const void *)ND_NULL,
+ /* 7d */ (const void *)ND_NULL,
+ /* 7e */ (const void *)ND_NULL,
+ /* 7f */ (const void *)ND_NULL,
+ /* 80 */ (const void *)ND_NULL,
+ /* 81 */ (const void *)ND_NULL,
+ /* 82 */ (const void *)ND_NULL,
+ /* 83 */ (const void *)ND_NULL,
+ /* 84 */ (const void *)ND_NULL,
+ /* 85 */ (const void *)&gXopMap_mmmmm_08_opcode_85_leaf,
+ /* 86 */ (const void *)&gXopMap_mmmmm_08_opcode_86_leaf,
+ /* 87 */ (const void *)&gXopMap_mmmmm_08_opcode_87_leaf,
+ /* 88 */ (const void *)ND_NULL,
+ /* 89 */ (const void *)ND_NULL,
+ /* 8a */ (const void *)ND_NULL,
+ /* 8b */ (const void *)ND_NULL,
+ /* 8c */ (const void *)ND_NULL,
+ /* 8d */ (const void *)ND_NULL,
+ /* 8e */ (const void *)&gXopMap_mmmmm_08_opcode_8e_leaf,
+ /* 8f */ (const void *)&gXopMap_mmmmm_08_opcode_8f_leaf,
+ /* 90 */ (const void *)ND_NULL,
+ /* 91 */ (const void *)ND_NULL,
+ /* 92 */ (const void *)ND_NULL,
+ /* 93 */ (const void *)ND_NULL,
+ /* 94 */ (const void *)ND_NULL,
+ /* 95 */ (const void *)&gXopMap_mmmmm_08_opcode_95_leaf,
+ /* 96 */ (const void *)&gXopMap_mmmmm_08_opcode_96_leaf,
+ /* 97 */ (const void *)&gXopMap_mmmmm_08_opcode_97_leaf,
+ /* 98 */ (const void *)ND_NULL,
+ /* 99 */ (const void *)ND_NULL,
+ /* 9a */ (const void *)ND_NULL,
+ /* 9b */ (const void *)ND_NULL,
+ /* 9c */ (const void *)ND_NULL,
+ /* 9d */ (const void *)ND_NULL,
+ /* 9e */ (const void *)&gXopMap_mmmmm_08_opcode_9e_leaf,
+ /* 9f */ (const void *)&gXopMap_mmmmm_08_opcode_9f_leaf,
+ /* a0 */ (const void *)ND_NULL,
+ /* a1 */ (const void *)ND_NULL,
+ /* a2 */ (const void *)&gXopMap_mmmmm_08_opcode_a2_w,
+ /* a3 */ (const void *)&gXopMap_mmmmm_08_opcode_a3_w,
+ /* a4 */ (const void *)ND_NULL,
+ /* a5 */ (const void *)ND_NULL,
+ /* a6 */ (const void *)&gXopMap_mmmmm_08_opcode_a6_leaf,
+ /* a7 */ (const void *)ND_NULL,
+ /* a8 */ (const void *)ND_NULL,
+ /* a9 */ (const void *)ND_NULL,
+ /* aa */ (const void *)ND_NULL,
+ /* ab */ (const void *)ND_NULL,
+ /* ac */ (const void *)ND_NULL,
+ /* ad */ (const void *)ND_NULL,
+ /* ae */ (const void *)ND_NULL,
+ /* af */ (const void *)ND_NULL,
+ /* b0 */ (const void *)ND_NULL,
+ /* b1 */ (const void *)ND_NULL,
+ /* b2 */ (const void *)ND_NULL,
+ /* b3 */ (const void *)ND_NULL,
+ /* b4 */ (const void *)ND_NULL,
+ /* b5 */ (const void *)ND_NULL,
+ /* b6 */ (const void *)&gXopMap_mmmmm_08_opcode_b6_leaf,
+ /* b7 */ (const void *)ND_NULL,
+ /* b8 */ (const void *)ND_NULL,
+ /* b9 */ (const void *)ND_NULL,
+ /* ba */ (const void *)ND_NULL,
+ /* bb */ (const void *)ND_NULL,
+ /* bc */ (const void *)ND_NULL,
+ /* bd */ (const void *)ND_NULL,
+ /* be */ (const void *)ND_NULL,
+ /* bf */ (const void *)ND_NULL,
+ /* c0 */ (const void *)&gXopMap_mmmmm_08_opcode_c0_leaf,
+ /* c1 */ (const void *)&gXopMap_mmmmm_08_opcode_c1_leaf,
+ /* c2 */ (const void *)&gXopMap_mmmmm_08_opcode_c2_leaf,
+ /* c3 */ (const void *)&gXopMap_mmmmm_08_opcode_c3_leaf,
+ /* c4 */ (const void *)ND_NULL,
+ /* c5 */ (const void *)ND_NULL,
+ /* c6 */ (const void *)ND_NULL,
+ /* c7 */ (const void *)ND_NULL,
+ /* c8 */ (const void *)ND_NULL,
+ /* c9 */ (const void *)ND_NULL,
+ /* ca */ (const void *)ND_NULL,
+ /* cb */ (const void *)ND_NULL,
+ /* cc */ (const void *)&gXopMap_mmmmm_08_opcode_cc_leaf,
+ /* cd */ (const void *)&gXopMap_mmmmm_08_opcode_cd_leaf,
+ /* ce */ (const void *)&gXopMap_mmmmm_08_opcode_ce_leaf,
+ /* cf */ (const void *)&gXopMap_mmmmm_08_opcode_cf_leaf,
+ /* d0 */ (const void *)ND_NULL,
+ /* d1 */ (const void *)ND_NULL,
+ /* d2 */ (const void *)ND_NULL,
+ /* d3 */ (const void *)ND_NULL,
+ /* d4 */ (const void *)ND_NULL,
+ /* d5 */ (const void *)ND_NULL,
+ /* d6 */ (const void *)ND_NULL,
+ /* d7 */ (const void *)ND_NULL,
+ /* d8 */ (const void *)ND_NULL,
+ /* d9 */ (const void *)ND_NULL,
+ /* da */ (const void *)ND_NULL,
+ /* db */ (const void *)ND_NULL,
+ /* dc */ (const void *)ND_NULL,
+ /* dd */ (const void *)ND_NULL,
+ /* de */ (const void *)ND_NULL,
+ /* df */ (const void *)ND_NULL,
+ /* e0 */ (const void *)ND_NULL,
+ /* e1 */ (const void *)ND_NULL,
+ /* e2 */ (const void *)ND_NULL,
+ /* e3 */ (const void *)ND_NULL,
+ /* e4 */ (const void *)ND_NULL,
+ /* e5 */ (const void *)ND_NULL,
+ /* e6 */ (const void *)ND_NULL,
+ /* e7 */ (const void *)ND_NULL,
+ /* e8 */ (const void *)ND_NULL,
+ /* e9 */ (const void *)ND_NULL,
+ /* ea */ (const void *)ND_NULL,
+ /* eb */ (const void *)ND_NULL,
+ /* ec */ (const void *)&gXopMap_mmmmm_08_opcode_ec_leaf,
+ /* ed */ (const void *)&gXopMap_mmmmm_08_opcode_ed_leaf,
+ /* ee */ (const void *)&gXopMap_mmmmm_08_opcode_ee_leaf,
+ /* ef */ (const void *)&gXopMap_mmmmm_08_opcode_ef_leaf,
+ /* f0 */ (const void *)ND_NULL,
+ /* f1 */ (const void *)ND_NULL,
+ /* f2 */ (const void *)ND_NULL,
+ /* f3 */ (const void *)ND_NULL,
+ /* f4 */ (const void *)ND_NULL,
+ /* f5 */ (const void *)ND_NULL,
+ /* f6 */ (const void *)ND_NULL,
+ /* f7 */ (const void *)ND_NULL,
+ /* f8 */ (const void *)ND_NULL,
+ /* f9 */ (const void *)ND_NULL,
+ /* fa */ (const void *)ND_NULL,
+ /* fb */ (const void *)ND_NULL,
+ /* fc */ (const void *)ND_NULL,
+ /* fd */ (const void *)ND_NULL,
+ /* fe */ (const void *)ND_NULL,
+ /* ff */ (const void *)ND_NULL,
+ }
+};
+
+const ND_TABLE_EX_M gXopMap_mmmmm =
+{
+ ND_ILUT_EX_M,
+ {
+ /* 00 */ (const void *)ND_NULL,
+ /* 01 */ (const void *)ND_NULL,
+ /* 02 */ (const void *)ND_NULL,
+ /* 03 */ (const void *)ND_NULL,
+ /* 04 */ (const void *)ND_NULL,
+ /* 05 */ (const void *)ND_NULL,
+ /* 06 */ (const void *)ND_NULL,
+ /* 07 */ (const void *)ND_NULL,
+ /* 08 */ (const void *)&gXopMap_mmmmm_08_opcode,
+ /* 09 */ (const void *)&gXopMap_mmmmm_09_opcode,
+ /* 0a */ (const void *)&gXopMap_mmmmm_0a_opcode,
+ /* 0b */ (const void *)ND_NULL,
+ /* 0c */ (const void *)ND_NULL,
+ /* 0d */ (const void *)ND_NULL,
+ /* 0e */ (const void *)ND_NULL,
+ /* 0f */ (const void *)ND_NULL,
+ /* 10 */ (const void *)ND_NULL,
+ /* 11 */ (const void *)ND_NULL,
+ /* 12 */ (const void *)ND_NULL,
+ /* 13 */ (const void *)ND_NULL,
+ /* 14 */ (const void *)ND_NULL,
+ /* 15 */ (const void *)ND_NULL,
+ /* 16 */ (const void *)ND_NULL,
+ /* 17 */ (const void *)ND_NULL,
+ /* 18 */ (const void *)ND_NULL,
+ /* 19 */ (const void *)ND_NULL,
+ /* 1a */ (const void *)ND_NULL,
+ /* 1b */ (const void *)ND_NULL,
+ /* 1c */ (const void *)ND_NULL,
+ /* 1d */ (const void *)ND_NULL,
+ /* 1e */ (const void *)ND_NULL,
+ /* 1f */ (const void *)ND_NULL,
+ }
+};
+
+
+#endif
+
diff --git a/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_tabledefs.h b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_tabledefs.h
new file mode 100644
index 00000000000000..d786443463a0c9
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/bddisasm/include/bdx86_tabledefs.h
@@ -0,0 +1,550 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDX86_TABLEDEFS_H
+#define BDX86_TABLEDEFS_H
+
+#include "/home/bernhard/data/entwicklung/2024/llvm-mingw/2024-10-18/llvm-mingw/llvm-project/compiler-rt/lib/interception/bddisasm/inc/bddisasm_types.h"
+
+//
+// Types of tables.
+//
+typedef enum _ND_ILUT_TYPE
+{
+ ND_ILUT_INSTRUCTION = 0,// Table contains one entry that directly points to an instruction.
+ ND_ILUT_OPCODE, // Table contains 256 entries. Next entry is selected using an opcode.
+ ND_ILUT_OPCODE_LAST, // Table contains 256 entries. Next entry is selected using an opcode, but the
+ // opcode follows the instruction as the last byte.
+ ND_ILUT_MODRM_REG, // Table contains 8 entries. Next entry is selected using modrm.reg.
+ ND_ILUT_MODRM_MOD, // Table contains 2 entries. Next entry is selected using modrm.mod (0 - mem, 1 - reg)
+ ND_ILUT_MODRM_RM, // Table contains 8 entries. Next entry is selected using modrm.rm.
+ ND_ILUT_MAN_PREFIX, // Table contains 4 entries. Next entry is 0 (no prefix), 1 (0x66), 2 (0xF3), 3 (0xF2).
+ ND_ILUT_MODE, // Table contains 4 entries. Next entry is 0 (16 bit mode), 1 (32 bit mode), 2 (64 bit mode).
+ ND_ILUT_DSIZE, // Table contains 4 entries. Next entry is 0 (16 bit size), 1 (32 bit size), 2 (64 bit size).
+ // This DOES NOT take into consideration forced/default sizes.
+ ND_ILUT_ASIZE, // Default addressing mode is used to transition
+ ND_ILUT_AUXILIARY, // Table contains 10 entries. Next entry is 0 (no prefix), 1 (rex), 2 (rex.w), etc.
+ ND_ILUT_VENDOR, // Preferred vendor is used to transition. Default is entry 0. Otherwise, preferred
+ // vendor selects an alternate entry.
+ ND_ILUT_FEATURE, // Some instructions are mapped onto wide NOP space. They will be decoded only if the
+ // associated feature is set during decoding.
+ ND_ILUT_EX_M, // Table contains 32 entries. Next entry is vex/xop/evex.mmmmm
+ ND_ILUT_EX_PP, // Table contains 4 entries. Next entry is vex/xop/evex.pp
+ ND_ILUT_EX_L, // Table contains 4 entries. Next entry is vex/xop.l or evex.l'l
+ ND_ILUT_EX_W, // Table contains 2 entries. Next entry is vex/xop/evex.w
+ ND_ILUT_EX_WI, // Table contains 2 entries. Next entry is vex/xop/evex.w. If not in 64 bit, next entry is 0.
+ ND_ILUT_EX_ND, // Table contains 2 entries. Next entry is evex.ND.
+ ND_ILUT_EX_NF, // Table contains 2 entries. Next entry is evex.NF.
+ ND_ILUT_EX_SC, // Table contains 16 entries. Next entry is evex.SC.
+} ND_ILUT_TYPE;
+
+
+// Index definitions
+#define ND_ILUT_INDEX_MOD_MEM 0
+#define ND_ILUT_INDEX_MOD_REG 1
+
+// Mandatory prefixes.
+#define ND_ILUT_INDEX_MAN_PREF_NP 0
+#define ND_ILUT_INDEX_MAN_PREF_66 1
+#define ND_ILUT_INDEX_MAN_PREF_F3 2
+#define ND_ILUT_INDEX_MAN_PREF_F2 3
+
+// Operating mode.
+#define ND_ILUT_INDEX_MODE_NONE 0
+#define ND_ILUT_INDEX_MODE_16 1
+#define ND_ILUT_INDEX_MODE_32 2
+#define ND_ILUT_INDEX_MODE_64 3
+
+// Operand size.
+#define ND_ILUT_INDEX_DSIZE_NONE 0
+#define ND_ILUT_INDEX_DSIZE_16 1
+#define ND_ILUT_INDEX_DSIZE_32 2
+#define ND_ILUT_INDEX_DSIZE_64 3
+#define ND_ILUT_INDEX_DSIZE_DEF64 4
+#define ND_ILUT_INDEX_DSIZE_F64 5
+
+// Address size.
+#define ND_ILUT_INDEX_ASIZE_NONE 0
+#define ND_ILUT_INDEX_ASIZE_16 1
+#define ND_ILUT_INDEX_ASIZE_32 2
+#define ND_ILUT_INDEX_ASIZE_64 3
+
+// Misc conditions.
+#define ND_ILUT_INDEX_AUX_NONE 0
+#define ND_ILUT_INDEX_AUX_REXB 1
+#define ND_ILUT_INDEX_AUX_REXW 2
+#define ND_ILUT_INDEX_AUX_MO64 3
+#define ND_ILUT_INDEX_AUX_REPZ 4
+#define ND_ILUT_INDEX_AUX_REP 5
+#define ND_ILUT_INDEX_AUX_RIPREL 6
+#define ND_ILUT_INDEX_AUX_REX2 7
+#define ND_ILUT_INDEX_AUX_REX2W 8
+
+// Specific features for instructions that map on the wide NOP space.
+#define ND_ILUT_FEATURE_NONE 0
+#define ND_ILUT_FEATURE_MPX 1
+#define ND_ILUT_FEATURE_CET 2
+#define ND_ILUT_FEATURE_CLDEMOTE 3
+#define ND_ILUT_FEATURE_PITI 4
+
+
+typedef struct _ND_TABLE
+{
+ ND_UINT32 Type;
+ const void *Table[1];
+} ND_TABLE, *PND_TABLE;
+
+typedef struct _ND_TABLE_INSTRUCTION
+{
+ ND_UINT32 Type;
+ const void *Instruction;
+} ND_TABLE_INSTRUCTION, *PND_TABLE_INSTRUCTION;
+
+typedef struct _ND_TABLE_OPCODE
+{
+ ND_UINT32 Type;
+ const void *Table[256];
+} ND_TABLE_OPCODE, *PND_TABLE_OPCODE;
+
+typedef struct _ND_TABLE_MODRM_MOD
+{
+ ND_UINT32 Type;
+ const void *Table[2];
+} ND_TABLE_MODRM_MOD, *PND_TABLE_MODRM_MOD;
+
+typedef struct _ND_TABLE_MODRM_REG
+{
+ ND_UINT32 Type;
+ const void *Table[8];
+} ND_TABLE_MODRM_REG, *PND_TABLE_MODRM_REG;
+
+typedef struct _ND_TABLE_MODRM_RM
+{
+ ND_UINT32 Type;
+ const void *Table[8];
+} ND_TABLE_MODRM_RM, *PND_TABLE_MODRM_RM;
+
+typedef struct _ND_TABLE_MPREFIX
+{
+ ND_UINT32 Type;
+ const void *Table[4];
+} ND_TABLE_MPREFIX, *PND_TABLE_MPREFIX;
+
+typedef struct _ND_TABLE_AUXILIARY
+{
+ ND_UINT32 Type;
+ const void *Table[10];
+} ND_TABLE_AUXILIARY, *PND_TABLE_AUXILIARY;
+
+typedef struct _ND_TABLE_VENDOR
+{
+ ND_UINT32 Type;
+ const void *Table[6];
+} ND_TABLE_VENDOR;
+
+typedef struct _ND_TABLE_FEATURE
+{
+ ND_UINT32 Type;
+ const void *Table[8];
+} ND_TABLE_FEATURE;
+
+typedef struct _ND_TABLE_DSIZE
+{
+ ND_UINT32 Type;
+ const void *Table[6];
+} ND_TABLE_DSIZE, *PND_TABLE_DSIZE;
+
+typedef struct _ND_TABLE_ASIZE
+{
+ ND_UINT32 Type;
+ const void *Table[4];
+} ND_TABLE_ASIZE, *PND_TABLE_ASIZE;
+
+typedef struct _ND_TABLE_MODE
+{
+ ND_UINT32 Type;
+ const void *Table[4];
+} ND_TABLE_MODE, *PND_TABLE_MODE;
+
+typedef struct _ND_TABLE_EX_M
+{
+ ND_UINT32 Type;
+ const void *Table[32];
+} ND_TABLE_EX_M, *PND_TABLE_EX_M;
+
+typedef struct _ND_TABLE_EX_PP
+{
+ ND_UINT32 Type;
+ const void *Table[4];
+} ND_TABLE_EX_PP, *PND_TABLE_EX_PP;
+
+typedef struct _ND_TABLE_EX_L
+{
+ ND_UINT32 Type;
+ const void *Table[4];
+} ND_TABLE_EX_L, *PND_TABLE_EX_L;
+
+typedef struct _ND_TABLE_EX_W
+{
+ ND_UINT32 Type;
+ const void *Table[2];
+} ND_TABLE_EX_W, *PND_TABLE_EX_W;
+
+typedef struct _ND_TABLE_EX_ND
+{
+ ND_UINT32 Type;
+ const void *Table[2];
+} ND_TABLE_EX_ND, *PND_TABLE_EX_ND;
+
+typedef struct _ND_TABLE_EX_NF
+{
+ ND_UINT32 Type;
+ const void *Table[2];
+} ND_TABLE_EX_NF, *PND_TABLE_EX_NF;
+
+typedef struct _ND_TABLE_EX_SC
+{
+ ND_UINT32 Type;
+ const void *Table[16];
+} ND_TABLE_EX_SC, *PND_TABLE_EX_SC;
+
+
+//
+// One instruction database entry.
+//
+typedef struct _ND_IDBE
+{
+ ND_UINT16 Instruction; // Instruction identifier. Check ND_INS_CLASS definitions.
+ ND_UINT8 Category; // Instruction category. Check ND_INS_TYPE.
+ ND_UINT8 IsaSet; // Instruction set. Check ND_INS_SET.
+ ND_UINT16 Mnemonic; // Mnemonic (index inside the global mnemonic table).
+ ND_UINT16 ValidPrefixes; // Accepted prefixes.
+ ND_UINT32 ValidModes; // Valid operating modes for the instruction.
+ ND_UINT8 ValidDecorators;// Accepted decorators (valid for EVEX instructions).
+ ND_UINT8 OpsCount; // Low 4 bits: explicit operands count; high 4 bits: implicit ops count.
+ ND_UINT8 TupleType; // EVEX tuple type.
+ ND_UINT8 ExcType; // SSE/VEX/EVEX/OPMASK/AMX/APX exception type.
+ ND_UINT8 FpuFlags; // FPU status word C0, C1, C2 & C3 access type.
+ ND_UINT8 EvexMode; // EVEX prefix extension type.
+ ND_UINT8 SimdExc; // SIMD Floating-Point Exceptions.
+
+ // Per-flag access. Undefined flags will have their bit set in both the "Set" and "Cleared" mask, since a flag
+ // cannot be both cleared and set.
+ ND_UINT32 TestedFlags; // Tested flags.
+ ND_UINT32 ModifiedFlags; // Modified flags.
+ ND_UINT32 SetFlags; // Flags that are always set to 1.
+ ND_UINT32 ClearedFlags; // Flags that are always cleared.
+
+ ND_UINT64 Attributes; // Instruction attributes.
+ ND_UINT64 CpuidFlag; // Required CPUID feature flag.
+
+ // List of operands. Up to 10 implicit and explicit operands stored in DB.
+ ND_UINT64 Operands[10];
+
+} ND_IDBE, *PND_IDBE;
+
+
+//
+// The following definitions are per-operand specific.
+//
+// Packed operand structure:
+// Byte 0: operand type
+// Byte 1: operand size
+// Byte 2: operand flags
+// Byte 3: operand access
+// Byte 4: operand decorators
+// Byte 5: operand block addressing mode - 0 if not block addressing
+//
+#define ND_OP(type, size, flags, acc, dec, block) (((ND_UINT64)((type) & 0xFF) << 0) | \
+ ((ND_UINT64)((size) & 0xFF) << 8) | \
+ ((ND_UINT64)((flags) & 0xFF) << 16) | \
+ ((ND_UINT64)((acc) & 0xFF) << 24) | \
+ ((ND_UINT64)((dec) & 0xFF) << 32) | \
+ ((ND_UINT64)((block) & 0xFF) << 40))
+
+#define OP ND_OP
+
+#define ND_OPS_CNT(expo, impo) ((expo) | ((impo) << 4))
+#define ND_EXP_OPS_CNT(cnt) ((cnt) & 0xF)
+#define ND_IMP_OPS_CNT(cnt) ((cnt) >> 4)
+
+#define ND_OP_TYPE(op) ((op) & 0xFF)
+#define ND_OP_SIZE(op) (((op) >> 8) & 0xFF)
+#define ND_OP_FLAGS(op) (((op) >> 16) & 0xFF)
+#define ND_OP_ACCESS(op) (((op) >> 24) & 0xFF)
+#define ND_OP_DECORATORS(op) (((op) >> 32) & 0xFF)
+#define ND_OP_BLOCK(op) (((op) >> 40) & 0xFF)
+
+
+
+
+//
+// Operand size descriptors. These are internal and stored inside the specifier. They must be interpreted
+// accordingly to extract the actual size used in the instruction. These should not be used by anyone using
+// the disassembler. Use the "Size" and "RawSize" fields inside the operand instead.
+//
+// For info on what each enum means, check out the valid_opsize field inside disasmlib.py.
+//
+typedef enum _ND_OPERAND_SIZE_SPEC
+{
+ ND_OPS_none = 0,
+ ND_OPS_0,
+ ND_OPS_asz,
+ ND_OPS_ssz,
+ ND_OPS_a,
+ ND_OPS_c,
+ ND_OPS_b,
+ ND_OPS_w,
+ ND_OPS_d,
+ ND_OPS_q,
+ ND_OPS_dq,
+ ND_OPS_qq,
+ ND_OPS_oq,
+ ND_OPS_v,
+ ND_OPS_y,
+ ND_OPS_yf,
+ ND_OPS_z,
+ ND_OPS_s,
+ ND_OPS_p,
+ ND_OPS_fa,
+ ND_OPS_fw,
+ ND_OPS_fd,
+ ND_OPS_fq,
+ ND_OPS_ft,
+ ND_OPS_fe,
+ ND_OPS_fs,
+ ND_OPS_l,
+ ND_OPS_rx,
+ ND_OPS_cl,
+ ND_OPS_sd,
+ ND_OPS_ss,
+ ND_OPS_sh,
+ ND_OPS_ps,
+ ND_OPS_pd,
+ ND_OPS_ph,
+ ND_OPS_ev,
+ ND_OPS_qv,
+ ND_OPS_hv,
+ ND_OPS_x,
+ ND_OPS_uv,
+ ND_OPS_fv,
+ ND_OPS_t, // Tile register size, can be up to 1K.
+ ND_OPS_384, // 384 bit Key Locker handle.
+ ND_OPS_512, // 512 bit Key Locker handle.
+ ND_OPS_4096, // 4096 bit MSR address/value table, used by RDMSRLIST/WRMSRLIST.
+ // Stack sizes - indicates number of words. Also, hybrid sizes - sizes where from a large register (say 32 bit GPR)
+ // only a smaller amount of data is used (for example, 8 bit).
+ ND_OPS_v2,
+ ND_OPS_v3,
+ ND_OPS_v4,
+ ND_OPS_v5,
+ ND_OPS_v8,
+ // 4 + 8 bytes accessed on the shadow stack by the SAVPREVSSP instruction.
+ ND_OPS_12,
+ // MIB
+ ND_OPS_mib,
+ // VSIB sizes (for both the index and the accessed data).
+ ND_OPS_vm32x,
+ ND_OPS_vm32y,
+ ND_OPS_vm32z,
+ ND_OPS_vm32h,
+ ND_OPS_vm32n,
+ ND_OPS_vm64x,
+ ND_OPS_vm64y,
+ ND_OPS_vm64z,
+ ND_OPS_vm64h,
+ ND_OPS_vm64n,
+ // Used for arbitrary sized buffers.
+ ND_OPS_unknown,
+
+} ND_OPERAND_SIZE_SPEC;
+
+
+//
+// Operand types. These definitions are internal and have to be interpreted in order to find out what each
+// operand represents. These should not be used by anyone using the disassembler. Use the "Type" field inside
+// the operand structure instead.
+//
+// For more info on what each operand type means, please check out the valid_optype field inside disasmlib.py.
+//
+typedef enum _ND_OPERAND_TYPE_SPEC
+{
+ ND_OPT_A,
+ ND_OPT_B,
+ ND_OPT_C,
+ ND_OPT_D,
+ ND_OPT_E,
+ ND_OPT_F,
+ ND_OPT_G,
+ ND_OPT_H,
+ ND_OPT_I,
+ ND_OPT_J,
+ ND_OPT_K,
+ ND_OPT_L,
+ ND_OPT_M,
+ ND_OPT_N,
+ ND_OPT_O,
+ ND_OPT_P,
+ ND_OPT_Q,
+ ND_OPT_R,
+ ND_OPT_S,
+ ND_OPT_T,
+ ND_OPT_U,
+ ND_OPT_V,
+ ND_OPT_W,
+ ND_OPT_X,
+ ND_OPT_Y,
+ ND_OPT_Z,
+ ND_OPT_rB,
+ ND_OPT_mB,
+ ND_OPT_rK,
+ ND_OPT_vK,
+ ND_OPT_mK,
+ ND_OPT_aK,
+ ND_OPT_rM,
+ ND_OPT_mM,
+ ND_OPT_rT,
+ ND_OPT_mT,
+ ND_OPT_vT,
+ ND_OPT_dfv,
+ ND_OPT_1,
+
+ // These are implicit arguments inside instructions.
+
+ // Special registers.
+ ND_OPT_rIP,
+ ND_OPT_MXCSR,
+ ND_OPT_PKRU,
+ ND_OPT_SSP,
+ ND_OPT_UIF,
+
+ // General Purpose Registers.
+ ND_OPT_AH,
+ ND_OPT_rAX,
+ ND_OPT_rCX,
+ ND_OPT_rDX,
+ ND_OPT_rBX,
+ ND_OPT_rSP,
+ ND_OPT_rBP,
+ ND_OPT_rSI,
+ ND_OPT_rDI,
+ ND_OPT_rR8,
+ ND_OPT_rR9,
+ ND_OPT_rR11,
+
+ // Segment registers.
+ ND_OPT_CS,
+ ND_OPT_SS,
+ ND_OPT_DS,
+ ND_OPT_ES,
+ ND_OPT_FS,
+ ND_OPT_GS,
+
+ // FPU registers.
+ ND_OPT_ST0,
+ ND_OPT_STi,
+
+ // SSE registers.
+ ND_OPT_XMM0,
+ ND_OPT_XMM1,
+ ND_OPT_XMM2,
+ ND_OPT_XMM3,
+ ND_OPT_XMM4,
+ ND_OPT_XMM5,
+ ND_OPT_XMM6,
+ ND_OPT_XMM7,
+
+ // Implicit memory operands.
+ ND_OPT_pAX, // [rAX]
+ ND_OPT_pCX, // [rCX]
+ ND_OPT_pBXAL, // [rBX + AL]
+ ND_OPT_pDI, // [rDI]
+ ND_OPT_pBP, // [rBP]
+ ND_OPT_SHS, // Shadow stack.
+ ND_OPT_SHSP, // Shadow stack pointed by the SSP.
+ ND_OPT_SHS0, // Shadow stack pointed by the SSP.
+ ND_OPT_SMT, // Source MSR table, encoded in [RSI].
+ ND_OPT_DMT, // Destination MSR table, encoded in [RDI].
+
+ // Special immediates.
+ ND_OPT_m2zI,
+
+ // Misc CR/XCR/MSR/SYS registers.
+ ND_OPT_CR0,
+ ND_OPT_IDTR,
+ ND_OPT_GDTR,
+ ND_OPT_LDTR,
+ ND_OPT_TR,
+ ND_OPT_X87CONTROL,
+ ND_OPT_X87TAG,
+ ND_OPT_X87STATUS,
+ ND_OPT_MSR,
+ ND_OPT_XCR,
+ ND_OPT_TSC,
+ ND_OPT_TSCAUX,
+ ND_OPT_SEIP,
+ ND_OPT_SESP,
+ ND_OPT_SCS,
+ ND_OPT_STAR,
+ ND_OPT_LSTAR,
+ ND_OPT_FMASK,
+ ND_OPT_FSBASE,
+ ND_OPT_GSBASE,
+ ND_OPT_KGSBASE,
+ ND_OPT_XCR0,
+ ND_OPT_BANK,
+
+} ND_OPERAND_TYPE_SPEC;
+
+
+//
+// Operand flags.
+//
+#define ND_OPF_OPDEF 0x01 // The operand is default, no need to show it in disassembly.
+#define ND_OPF_OPSIGNEXO1 0x02 // The operand is sign-extended to the first operands' size.
+#define ND_OPF_OPSIGNEXDW 0x04 // The operand is sign-extended to the default word size.
+
+
+//
+// Operand access.
+//
+#define ND_OPA_N 0x00 // The operand is not accessed.
+#define ND_OPA_R 0x01 // The operand is read.
+#define ND_OPA_W 0x02 // The operand is written.
+#define ND_OPA_CR 0x04 // The operand is read conditionally.
+#define ND_OPA_CW 0x08 // The operand is written conditionally.
+#define ND_OPA_RW 0x03 // Read-Write access.
+#define ND_OPA_RCW 0x09 // Read-Conditional Write access.
+#define ND_OPA_CRW 0X06 // Conditional Read-Write access.
+#define ND_OPA_CRCW 0x0C // Conditional Read-Conditional Write access.
+#define ND_OPA_P 0x10 // The operand is memory, and it is prefetched.
+
+
+//
+// Operand decorator flags.
+//
+#define ND_OPD_MASK 0x01 // Mask accepted.
+#define ND_OPD_ZERO 0x02 // Zeroing accepted.
+#define ND_OPD_B32 0x04 // 32 bit broadcast supported.
+#define ND_OPD_B64 0x08 // 64 bit broadcast supported.
+#define ND_OPD_SAE 0x10 // Suppress all exceptions supported.
+#define ND_OPD_ER 0x20 // Embedded rounding supported.
+#define ND_OPD_B16 0x40 // 16 bit broadcast supported.
+
+#define ND_OPD_BCAST (ND_OPD_B16 | ND_OPD_B32 | ND_OPD_B64)
+
+
+//
+// Include auto-generated stuff.
+//
+#include "../../inc/bdx86_constants.h"
+#include "bdx86_mnemonics.h"
+#include "bdx86_instructions.h"
+#include "bdx86_prefixes.h"
+#include "bdx86_table_root.h"
+#include "bdx86_table_xop.h"
+#include "bdx86_table_vex.h"
+#include "bdx86_table_evex.h"
+
+#endif // BDX86_TABLEDEFS_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bddisasm.h b/compiler-rt/lib/interception/bddisasm/inc/bddisasm.h
new file mode 100644
index 00000000000000..e71970b5b35e92
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bddisasm.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDDISASM_H
+#define BDDISASM_H
+
+#include "bdx86_core.h"
+
+#endif // BDDISASM_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bddisasm_status.h b/compiler-rt/lib/interception/bddisasm/inc/bddisasm_status.h
new file mode 100644
index 00000000000000..ecc18f22116ae8
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bddisasm_status.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDDISASM_STATUS_H
+#define BDDISASM_STATUS_H
+
+//
+// Return statuses.
+//
+typedef ND_UINT32 NDSTATUS;
+
+// Success codes are all < 0x80000000.
+#define ND_STATUS_SUCCESS 0x00000000 // All good.
+
+// Hint/success codes.
+#define ND_STATUS_HINT_OPERAND_NOT_USED 0x00000001
+
+// Error codes are all > 0x80000000.
+#define ND_STATUS_BUFFER_TOO_SMALL 0x80000001 // The provided input buffer is too small.
+#define ND_STATUS_INVALID_ENCODING 0x80000002 // Invalid encoding/instruction.
+#define ND_STATUS_INSTRUCTION_TOO_LONG 0x80000003 // Instruction exceeds the maximum 15 bytes.
+#define ND_STATUS_INVALID_PREFIX_SEQUENCE 0x80000004 // Invalid prefix sequence is present.
+#define ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION 0x80000005 // The instruction uses an invalid register.
+#define ND_STATUS_XOP_WITH_PREFIX 0x80000006 // XOP is present, but also a legacy prefix.
+#define ND_STATUS_VEX_WITH_PREFIX 0x80000007 // VEX is present, but also a legacy prefix.
+#define ND_STATUS_EVEX_WITH_PREFIX 0x80000008 // EVEX is present, but also a legacy prefix.
+#define ND_STATUS_INVALID_ENCODING_IN_MODE 0x80000009 // Invalid encoding/instruction.
+#define ND_STATUS_BAD_LOCK_PREFIX 0x8000000A // Invalid usage of LOCK.
+#define ND_STATUS_CS_LOAD 0x8000000B // An attempt to load the CS register.
+#define ND_STATUS_66_NOT_ACCEPTED 0x8000000C // 0x66 prefix is not accepted.
+#define ND_STATUS_16_BIT_ADDRESSING_NOT_SUPPORTED 0x8000000D // 16 bit addressing mode not supported.
+#define ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED 0x8000000E // RIP-relative addressing not supported.
+
+// VEX/EVEX specific errors.
+#define ND_STATUS_VSIB_WITHOUT_SIB 0x80000030 // Instruction uses VSIB, but SIB is not present.
+#define ND_STATUS_INVALID_VSIB_REGS 0x80000031 // VSIB addressing, same vector reg used more than once.
+#define ND_STATUS_VEX_VVVV_MUST_BE_ZERO 0x80000032 // VEX.VVVV field must be zero.
+#define ND_STATUS_MASK_NOT_SUPPORTED 0x80000033 // Masking is not supported.
+#define ND_STATUS_MASK_REQUIRED 0x80000034 // Masking is mandatory.
+#define ND_STATUS_ER_SAE_NOT_SUPPORTED 0x80000035 // Embedded rounding/SAE not supported.
+#define ND_STATUS_ZEROING_NOT_SUPPORTED 0x80000036 // Zeroing not supported.
+#define ND_STATUS_ZEROING_ON_MEMORY 0x80000037 // Zeroing on memory.
+#define ND_STATUS_ZEROING_NO_MASK 0x80000038 // Zeroing without masking.
+#define ND_STATUS_BROADCAST_NOT_SUPPORTED 0x80000039 // Broadcast not supported.
+#define ND_STATUS_BAD_EVEX_V_PRIME 0x80000040 // EVEX.V' field must be one (negated 0).
+#define ND_STATUS_BAD_EVEX_LL 0x80000041 // EVEX.L'L field is invalid for the instruction.
+#define ND_STATUS_SIBMEM_WITHOUT_SIB 0x80000042 // Instruction uses SIBMEM, but SIB is not present.
+#define ND_STATUS_INVALID_TILE_REGS 0x80000043 // Tile registers are not unique.
+#define ND_STATUS_INVALID_DEST_REGS 0x80000044 // Destination register is not unique (used as src).
+#define ND_STATUS_INVALID_EVEX_BYTE3 0x80000045 // EVEX payload byte 3 is invalid.
+#define ND_STATUS_BAD_EVEX_U 0x80000046 // EVEX.U field is invalid.
+
+
+// Not encoding specific.
+#define ND_STATUS_INVALID_PARAMETER 0x80000100 // An invalid parameter was provided.
+#define ND_STATUS_INVALID_INSTRUX 0x80000101 // The INSTRUX contains unexpected values.
+#define ND_STATUS_BUFFER_OVERFLOW 0x80000103 // Not enough space is available to format textual disasm.
+
+#define ND_STATUS_INTERNAL_ERROR 0x80000200 // Internal error occurred.
+
+
+#define ND_SUCCESS(status) (status < 0x80000000)
+
+#endif // BDDISASM_STATUS_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bddisasm_types.h b/compiler-rt/lib/interception/bddisasm/inc/bddisasm_types.h
new file mode 100644
index 00000000000000..101de894b069be
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bddisasm_types.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDDISASM_TYPES_H
+#define BDDISASM_TYPES_H
+
+
+#if defined(_MSC_VER) || defined(__ICC) || defined(__INTEL_COMPILER)
+
+// Microsoft VC compiler.
+
+typedef unsigned __int8 ND_UINT8;
+typedef unsigned __int16 ND_UINT16;
+typedef unsigned __int32 ND_UINT32;
+typedef unsigned __int64 ND_UINT64;
+typedef signed __int8 ND_SINT8;
+typedef signed __int16 ND_SINT16;
+typedef signed __int32 ND_SINT32;
+typedef signed __int64 ND_SINT64;
+
+#elif defined(__GNUC__) || defined(__GNUG__) || defined(__clang__)
+
+// clang/GCC compiler.
+
+typedef __UINT8_TYPE__ ND_UINT8;
+typedef __UINT16_TYPE__ ND_UINT16;
+typedef __UINT32_TYPE__ ND_UINT32;
+typedef __UINT64_TYPE__ ND_UINT64;
+typedef __INT8_TYPE__ ND_SINT8;
+typedef __INT16_TYPE__ ND_SINT16;
+typedef __INT32_TYPE__ ND_SINT32;
+typedef __INT64_TYPE__ ND_SINT64;
+
+#else
+
+// other compilers, assume stdint is present.
+
+#include <stdint.h>
+
+typedef uint8_t ND_UINT8;
+typedef uint16_t ND_UINT16;
+typedef uint32_t ND_UINT32;
+typedef uint64_t ND_UINT64;
+typedef int8_t ND_SINT8;
+typedef int16_t ND_SINT16;
+typedef int32_t ND_SINT32;
+typedef int64_t ND_SINT64;
+
+#endif
+
+
+
+#if defined(_M_AMD64) || defined(__x86_64__)
+
+#define ND_ARCH_X64
+
+#elif defined(_M_IX86) || defined(__i386__)
+
+#define ND_ARCH_X86
+#define ND_ARCH_IA32
+
+#elif defined(_M_ARM64) || defined(__aarch64__)
+
+#define ND_ARCH_AARCH64
+#define ND_ARCH_A64
+
+#elif defined(_M_ARM) || defined(__arm__)
+
+#define ND_ARCH_ARM
+#define ND_ARCH_A32
+
+#else
+
+#error "Unknown architecture!"
+
+#endif
+
+
+// Handle architecture definitions.
+#if defined(ND_ARCH_X64) || defined(ND_ARCH_A64)
+
+typedef ND_UINT64 ND_SIZET;
+
+#elif defined(ND_ARCH_X86) || defined(ND_ARCH_A32)
+
+typedef ND_UINT32 ND_SIZET;
+
+#else
+
+#error "Unknown architecture!"
+
+#endif
+
+
+// Common definitions.
+typedef ND_UINT8 ND_BOOL;
+
+#if defined(__cplusplus)
+#define ND_NULL nullptr
+#else
+#define ND_NULL ((void *)(0))
+#endif
+#define ND_TRUE (1)
+#define ND_FALSE (0)
+
+
+#endif // BDDISASM_TYPES_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bddisasm_version.h b/compiler-rt/lib/interception/bddisasm/inc/bddisasm_version.h
new file mode 100644
index 00000000000000..2963b8e3348330
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bddisasm_version.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDDISASM_VERSION_H
+#define BDDISASM_VERSION_H
+
+#define DISASM_VERSION_MAJOR 2
+#define DISASM_VERSION_MINOR 3
+#define DISASM_VERSION_REVISION 0
+
+#define SHEMU_VERSION_MAJOR DISASM_VERSION_MAJOR
+#define SHEMU_VERSION_MINOR DISASM_VERSION_MINOR
+#define SHEMU_VERSION_REVISION DISASM_VERSION_REVISION
+
+#endif // BDDISASM_VERSION_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bdshemu.h b/compiler-rt/lib/interception/bddisasm/inc/bdshemu.h
new file mode 100644
index 00000000000000..c78f85036d47b5
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bdshemu.h
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDSHEMU_H
+#define BDSHEMU_H
+
+
+#include "bddisasm.h"
+#include "bdshemu_x86.h"
+
+
+//
+// Print function. Used to log emulation traces.
+//
+typedef void
+(*ShemuPrint)(
+ char *Data, // Data to be printed.
+ void *Context // Optional, caller-defined, context.
+ );
+
+
+//
+// Access memory function. Simply return true if the access was handled, or false if it wasn't.
+// If the function is not provided in SHEMU_CONTEXT, or if it returns false, the emulation will be terminated.
+// Note that the integrator is free to handle external memory access as it pleases.
+// Loads could always yield the same value (0), a random value or they could return actual memory values.
+// Stores could be discarded, or they could be buffered in a store-buffer like structure.
+// Note that by using the ShemuContext, the integrator knows whether the access is user or supervisor (the Ring field
+// inside ShemuContext), and he knows whether it is 16/32/64 bit mode (Mode field inside ShemuContext).
+//
+typedef ND_BOOL
+(*ShemuMemAccess)(
+ void *ShemuContext, // Shemu emulation context.
+ ND_UINT64 Gla, // Linear address to be accessed.
+ ND_SIZET Size, // Number of bytes to access.
+ ND_UINT8 *Buffer, // Contains the read content (if Store is false), or the value to be stored at Gla.
+ ND_BOOL Store // If false, read content at Gla. Otherwise, write content at Gla.
+ );
+
+
+typedef enum _SHEMU_ARCH_TYPE
+{
+ SHEMU_ARCH_TYPE_NONE = 0,
+
+ // X86 includes both IA-32 and x86-64.
+ // All SHEMU flags are supported.
+ SHEMU_ARCH_TYPE_X86,
+
+} SHEMU_ARCH_TYPE;
+
+
+typedef struct _SHEMU_X86_CTX
+{
+ // Current instruction. Doesn't have to be provided; it always contains the currently emulated instruction.
+ // When #ShemuEmulate returns, this will contain the last emulated instruction. In case of an emulation failure,
+ // it can be inspected, to gather more info about what went wrong.
+ INSTRUX Instruction;
+
+ // General purpose registers state. On input, the initial state. Will be updated after each emulated instruction.
+ SHEMU_X86_GPR_REGS Registers;
+
+ // Segment registers state. On input, the initial state. May be updated after some instructions.
+ SHEMU_X86_SEG_REGS Segments;
+
+ // MMX register state. 8 x 8 bytes = 64 bytes for the MMX registers. Can be provided on input, if needed.
+ ND_UINT64 MmxRegisters[ND_MAX_MMX_REGS];
+
+ // SSE registers state. 32 x 64 bytes = 2048 bytes for the SSE registers. Can be provided on input, if needed.
+ ND_UINT8 SseRegisters[ND_MAX_SSE_REGS][ND_MAX_REGISTER_SIZE];
+
+ // General purpose registers write bitmap. After the first write, a register will be marked dirty in here.
+ // Should be 0 on input.
+ ND_UINT8 GprTracker[ND_MAX_GPR_REGS];
+
+ // Operating mode (ND_CODE_16, ND_CODE_32 or ND_CODE_64). Must be provided as input.
+ ND_UINT8 Mode;
+
+ // Operating ring (0, 1, 2, 3). Must be provided as input.
+ ND_UINT8 Ring;
+
+} SHEMU_X86_CTX;
+
+
+#define SHEMU_ICACHE_SIZE 0x100
+
+typedef struct SHEMU_ICACHE
+{
+ // Instruction cache.
+ ND_UINT8 Icache[SHEMU_ICACHE_SIZE];
+
+ // The first address that is cached.
+ ND_UINT64 Address;
+
+ // Number of valid bytes inside the cache. Maximum SHEMU_ICACHE_SIZE.
+ ND_UINT64 Size;
+} SHEMU_ICACHE;
+
+
+typedef struct SHEMU_LOOP_TRACK
+{
+ // The address of the loop instruction. The loop instruction can be any taken conditional or unconditional
+ // branch that goes backwards.
+ ND_UINT64 Address;
+
+ // The target of the loop instructions (the first instruction of the loop).
+ ND_UINT64 Target;
+
+ // The current iteration number.
+ ND_UINT64 Iteration;
+
+ // ND_TRUE whether tracking is active, and we are inside a loop.
+ ND_BOOL Active;
+
+} SHEMU_LOOP_TRACK;
+
+
+//
+// Emulation context. All of these fields must be provided as input, although most of them can be 0.
+//
+typedef struct _SHEMU_CONTEXT
+{
+ union
+ {
+ // Used when ArchType is SHEMU_ARCH_TYPE_X86.
+ SHEMU_X86_CTX X86;
+
+ } Arch;
+
+ // Indicates architecture mode. Must be provided as input.
+ SHEMU_ARCH_TYPE ArchType;
+
+ // Instruction cache. Note that this caches instruction bytes, not decoded instructions.
+ SHEMU_ICACHE Icache;
+
+ // Tracks emulated loops.
+ SHEMU_LOOP_TRACK LoopTrack;
+
+ // The suspicious code to be emulated. Must be provided as input, as follows:
+ // - This buffer must be allocated by the caller, and it must be writeable. It should NOT point to process memory,
+ // as it will be modified by shemu in case of self-modifying code.
+ // - However, if the SHEMU_OPT_DIRECT_MAPPED_SHELL option is used, this field can point directly to process memory,
+ // but the AccessShellcode callback must also be provided. In this case, the buffer will NOT be modified by
+ // shemu.
+ ND_UINT8 *Shellcode;
+
+ // Virtual stack. RSP will point somewhere inside. Must be allocated as input, and it can be initialized with
+ // actual stack contents. Can also be 0-filled.
+ // This buffer must be allocated by the caller, and it must be writeable. It should not point to process memory,
+ // as it will be modified by shemu.
+ ND_UINT8 *Stack;
+
+ // Internal use. Must be at least the size of the shell + stack. Needs not be initialized, but must be allocated
+ // and accessible on input.
+ ND_UINT8 *Intbuf;
+
+ // Shellcode base address (the address the shellcode would see). Must be provided as input.
+ ND_UINT64 ShellcodeBase;
+
+ // Stack base address (the stack the shellcode would see). Must be provided as input.
+ ND_UINT64 StackBase;
+
+ // Shellcode size. Must be provided as input. Usually just a page in size, but can be larger.
+ ND_UINT64 ShellcodeSize;
+
+ // Stack size. Must be provided as input. Minimum two pages.
+ ND_UINT64 StackSize;
+
+ // Internal buffer size. Must be provided as input. Must be at least the size of the shell + stack.
+ ND_UINT64 IntbufSize;
+
+ // Number of consecutive NOPs encountered at the beginning of the code. Should be 0 on input.
+ ND_UINT64 NopCount;
+
+ // Number of '00 00' (ADD [rax], al) instructions encountered. Should be 0 on input.
+ ND_UINT64 NullCount;
+
+ // The length of the string constructed on the stack, if any. Should be 0 on input.
+ ND_UINT64 StrLength;
+
+ // Number of external memory access (outside stack/shellcode). Should be 0 on input.
+ ND_UINT64 ExtMemAccess;
+
+ // Number of emulated instructions. Should be 0 on input. Once InstructionsCount reaches MaxInstructionsCount,
+ // emulation will stop.
+ ND_UINT64 InstructionsCount;
+
+ // Number of distinct addresses executed. Will be less than or equal to InstructionsCount. In case of an infinite
+ // loop (JMP $), this field will be 1, but the InstructionsCount will be infinite. In case of two overlapping
+ // instructions, this field will be incremented twice (for example, JMP $+1).
+ ND_UINT64 UniqueCount;
+
+ // Max number of instructions that should be emulated. Once this limit has been reached, emulation will stop.
+ // Lower values will mean faster processing, but less chances of detection. Higher values mean low performance,
+ // but very high chances of yielding useful results. Must be provided as input.
+ ND_UINT64 MaxInstructionsCount;
+
+ // Base address of the Thread Information Block (the TIB the shellcode would normally see). Must be provided as
+ // input.
+ ND_UINT64 TibBase;
+
+ // Shellcode Flags (see SHEMU_FLAG_*). Should be 0 on input. Will be non-zero on output if a shellcode indicator
+ // has been met (check SHEMU_FLAG_* values for shellcode indicators).
+ // Note that this field should always be checked for detection. No matter the return value of the emulator,
+ // if this field is non-zero, a potential shellcode has been detected. This is valid even if
+ // SHEMU_OPT_STOP_ON_EXPLOIT is set: this option only guarantees that emulation will not continue once a shellcode
+ // has been encountered, but it does not guarantee that SHEMU_ABORT_SHELLCODE_DETECTED will be returned.
+ ND_UINT64 Flags;
+
+ // Emulation options. See SHEMU_OPT_* for possible options. Must be provided as input.
+ ND_UINT64 Options;
+
+ // Percent of NOPs (out of total instructions emulated) that trigger NOP sled detection. Must be provided as input.
+ // Defaults to SHEMU_DEFAULT_NOP_THRESHOLD.
+ ND_UINT32 NopThreshold;
+
+ // Stack string length threshold. Stack-constructed strings must be at least this long to trigger stack string
+ // detection. Must be provided as input. Defaults to SHEMU_DEFAULT_STR_THRESHOLD.
+ ND_UINT32 StrThreshold;
+
+ // Number of external mem accesses threshold. No more than this number of external accesses will be issued. Must
+ // be provided as input. Defaults to SHEMU_DEFAULT_MEM_THRESHOLD.
+ ND_UINT32 MemThreshold;
+
+ // Optional auxiliary data, provided by the integrator. Can be NULL, or can point to integrator specific data.
+ // Shemu will not use this data in any way, but callbacks that receive a SHEMU_CONTEXT pointer (such as
+ // #AccessMemory) can use it to reference integrator private information.
+ void *AuxData;
+
+ // If provided, will be used for tracing. Can be NULL.
+ ShemuPrint Log;
+
+ // If provided, will try to access additional memory. Can be NULL.
+ ShemuMemAccess AccessMemory;
+
+ // Must be provided if the the SHEMU_OPT_DIRECT_MAPPED_SHELL option is used. This callback will be used to proxy
+ // all accesses made to the shellcode memory, including fetches, loads & stores. The AccessMemory callback is
+ // used only for accesses to memory that are not part of the Shellcode or the Stack.
+ ShemuMemAccess AccessShellcode;
+
+ // Optional context to be passed to Log. Can be NULL.
+ void *LogContext;
+
+} SHEMU_CONTEXT, *PSHEMU_CONTEXT;
+
+
+typedef unsigned int SHEMU_STATUS;
+
+
+
+//
+// Emulation abort reasons.
+//
+#define SHEMU_SUCCESS 0 // Successfully emulated up to MaxInstructions.
+#define SHEMU_ABORT_GLA_OUTSIDE 1 // A load or store outside the shellcode or the stack.
+#define SHEMU_ABORT_RIP_OUTSIDE 2 // A part of the instruction lies outside the shellcode.
+#define SHEMU_ABORT_INSTRUX_NOT_SUPPORTED 3 // An unsupported instruction was encountered.
+#define SHEMU_ABORT_OPERAND_NOT_SUPPORTED 4 // An unsupported operand was encountered.
+#define SHEMU_ABORT_ADDRESSING_NOT_SUPPORTED 5 // An unsupported addressing scheme used (ie, VSIB).
+#define SHEMU_ABORT_REGISTER_NOT_SUPPORTED 6 // An unsupported register was used (ie, DR).
+#define SHEMU_ABORT_INVALID_PARAMETER 7 // An invalid parameter was supplied.
+#define SHEMU_ABORT_NO_PRIVILEGE 9 // A privileged instruction outside kernel mode.
+#define SHEMU_ABORT_CANT_EMULATE 10 // A valid, but only partially handled instruction.
+#define SHEMU_ABORT_INVALID_SELECTOR 11 // An invalid selector is loaded.
+#define SHEMU_ABORT_UNDEFINED 12 // Valid encoding, but undefined cominbation of bits.
+#define SHEMU_ABORT_UNPREDICTABLE 13 // Instruction behavior is unpredictable.
+#define SHEMU_ABORT_MISALIGNED_PC 14 // PC is not aligned to a word.
+#define SHEMU_ABORT_FETCH_ERROR 15 // Could not fetch instruction bytes.
+#define SHEMU_ABORT_DECODE_ERROR 16 // Could not decode the instruction.
+
+#define SHEMU_ABORT_SHELLCODE_DETECTED 0xFFFFFFFF // Shellcode criteria met (see the shellcode flags).
+ // Note that this status may be returned if and only if
+ // the SHEMU_OPT_STOP_ON_EXPLOIT is used.
+
+
+typedef enum SHEMU_FLAG_ID
+{
+ shemuFlagIdNopSled,
+ shemuFlagIdLoadRip,
+ shemuFlagIdWriteSelf,
+ shemuFlagIdTebAccessPeb,
+ shemuFlagIdSyscall,
+ shemuFlagIdStackStr,
+ shemuFlagIdTebAccessWow32,
+ shemuFlagIdHeavensGate,
+ shemuFlagIdStackPivot,
+ shemuFlagIdSudAccess,
+
+ // Kernel specific flags.
+ shemuFlagIdKpcrAccess = 32,
+ shemuFlagIdSwapgs,
+ shemuFlagIdSyscallMsrRead,
+ shemuFlagIdSyscallMsrWrite,
+ shemuFlagIdSidt,
+} SHEMU_FLAG_ID;
+
+#define SHEMU_FLAG(id) (1ull << (id))
+
+
+//
+// Shellcode flags.
+//
+
+// General and user-mode flags.
+
+// Long sequence of NOP instructions. Generally present before the actual shellcode. This flag will only be set if:
+// 1. Minimum MaxInstructions / 2 instructions have been emulated;
+// 2. Minimum NopThreshold fraction (percent) of the emulated instructions are NOPs;
+// 3. No other abort condition is met during emulation.
+#define SHEMU_FLAG_NOP_SLED SHEMU_FLAG(shemuFlagIdNopSled)
+
+// The code loads RIP (CALL/POP, FNSTENV/POP, etc.). Almost always used by shellcodes in order to determine their
+// position in memory. This flag will be set when the value of the instruction pointer is loaded into a general
+// purpose register by any means. Techniques covered include, but are not limited to:
+// 1. CALL + POP reg;
+// 2. FP instruction + FNSTENV + loading the saved RIP from the saved FPU state.
+// Loading the RIP via RIP relative addressing on x64 does not set this flag.
+#define SHEMU_FLAG_LOAD_RIP SHEMU_FLAG(shemuFlagIdLoadRip)
+
+// The code writes itself (decryption, unpacking, etc.). Commonly seen if the shellcode decrypts itself in memory.
+// This flag will only be set if previously written data is executed. This flag will not be set if, for example,
+// chunks of data are written within the shellcode but never executed.
+#define SHEMU_FLAG_WRITE_SELF SHEMU_FLAG(shemuFlagIdWriteSelf)
+
+// The code accesses the PEB field inside TEB. This is achieved via "FS:[0x30]" or "GS:[0x60]" accesses. Inside
+// bdshemu, accesses to the linear address inside TEB is detected no mater how obfuscated - for example, the
+// following instructions will all set this flag:
+// 1. MOV eax, gs:[0x30]
+// 2. MOV eax, 0x30; MOV eax, fs:[eax]
+// 3. MOV eax, 0; MOV eax, fs:[eax+0x30]
+#define SHEMU_FLAG_TIB_ACCESS SHEMU_FLAG(shemuFlagIdTebAccessPeb)
+#define SHEMU_FLAG_TIB_ACCESS_PEB SHEMU_FLAG_TIB_ACCESS
+
+// The code does a direct syscall/sysenter/int 0x2e|0x80. This should never happen outside the legitimate ntdll
+// module. However, payloads may issue direct system calls in order to avoid detection, or to simply avoid fixing
+// imports manually.
+// Note that this flag will be set when the SYSCALL, SYSENTER, INT 0x2E or INT 0x80 is executed, but only if
+// the EAX register contains a value that resembles a valid system call (< 0x1000).
+#define SHEMU_FLAG_SYSCALL SHEMU_FLAG(shemuFlagIdSyscall)
+
+// The code constructs & uses strings on the stack. The flag will be set only if:
+// 1. The length of the string constructed on the stack is at least StrThreshold bytes long (default 8);
+// 2. The constructed string is referenced by loading its address anywhere (including a register or memory).
+#define SHEMU_FLAG_STACK_STR SHEMU_FLAG(shemuFlagIdStackStr)
+
+// The code accesses the Wow32Reserved field inside TIB. This is generally used to issue system calls from Wow64.
+#define SHEMU_FLAG_TIB_ACCESS_WOW32 SHEMU_FLAG(shemuFlagIdTebAccessWow32)
+
+// The code uses Heaven's gate to switch into 64 bit mode. This can be abused by shellcodes in order to avoid
+// detection by switching from legacy 32 bit mode to 64 bit mode.
+#define SHEMU_FLAG_HEAVENS_GATE SHEMU_FLAG(shemuFlagIdHeavensGate)
+
+// The code switches the stack using XCHG esp, *. This is commonly executed by a shellcode once it receives
+// control after a stack pivot. By itself, this flag is FP prone, and should generally not be used alone.
+// This flag will only be set if several conditions are met:
+// 1. The XCHG instruction is used to load a new value in the RSP register
+// 2. The new value is naturally aligned (8 bytes in 64-bit mode, 4 bytes in 32-bit mode)
+// 3. The new value points either inside the shellcode or the stack area, and at least 64 bytes are valid
+#define SHEMU_FLAG_STACK_PIVOT SHEMU_FLAG(shemuFlagIdStackPivot)
+
+// The code accesses the KUSER_SHARED_DATA page. Commonly used by shellcodes which wish to issue direct system
+// cals or to access various data located inside the SharedUserData page. Only accesses to the following fields
+// will set this flag:
+// 1. KdDebuggerEnabled (offset 0x2D4)
+// 2. SystemCall (offset 0x308)
+// 3. Cookie (offset 0x300)
+#define SHEMU_FLAG_SUD_ACCESS SHEMU_FLAG(shemuFlagIdSudAccess)
+
+
+// Kernel specific flags.
+
+// KPCR current thread access via gs:[0x188]/fs:[0x124]. Commonly used by kernel shellcodes in order to get the
+// currently exeucting thread.
+#define SHEMU_FLAG_KPCR_ACCESS SHEMU_FLAG(shemuFlagIdKpcrAccess)
+
+// SWAPGS was executed. Shellcodes may use this if they intercept a low-level event such as the SYSCALL.
+#define SHEMU_FLAG_SWAPGS SHEMU_FLAG(shemuFlagIdSwapgs)
+
+// A SYSCALL/SYSENTER MSR was read. Commonly used to locate the nt image in order to manually fix imports.
+#define SHEMU_FLAG_SYSCALL_MSR_READ SHEMU_FLAG(shemuFlagIdSyscallMsrRead)
+
+// A SYSCALL/SYSENTER MSR was written. Commonly used to intercept events such as SYSCALLs.
+#define SHEMU_FLAG_SYSCALL_MSR_WRITE SHEMU_FLAG(shemuFlagIdSyscallMsrWrite)
+
+// SIDT was executed. Commonly used to locate the nt image in order to manually fix imports.
+#define SHEMU_FLAG_SIDT SHEMU_FLAG(shemuFlagIdSidt)
+
+
+
+//
+// Emulation thresholds.
+//
+
+// Percent of emulated instructions that must be NOP to consider a NOP sled is present.
+#define SHEMU_DEFAULT_NOP_THRESHOLD 75
+
+// Consecutive printable characters on stack to consider a stack string access.
+#define SHEMU_DEFAULT_STR_THRESHOLD 8
+
+// Will not emulate more than this number of external memory accesses. Once this threshold is exceeded, any external
+// access will abort the emulation.
+#define SHEMU_DEFAULT_MEM_THRESHOLD 0
+
+
+
+
+//
+// Emulation options.
+//
+
+// Trace each emulated instruction.
+#define SHEMU_OPT_TRACE_EMULATION 0x0000000000000001
+
+// When shellcode indications are confirmed, stop emulation. Note that this flag only guarantees that emulation
+// will stop once we set any flag, but it does not guarantee that SHEMU_ABORT_SHELLCODE_DETECTED will be returned,
+// as an emulation error may take place at any moment. Always check the Flags field of the SHEMU_CONTEXT structure
+// to determine whether a detection took place or not.
+#define SHEMU_OPT_STOP_ON_EXPLOIT 0x0000000000000002
+
+// When a shellcode self-modifies, the modification will not be committed. Use this when emulating an already
+// decoded shellcode, where emulating the decryption again will in fact scramble the shellcode and make it useless.
+#define SHEMU_OPT_BYPASS_SELF_WRITES 0x0000000000000004
+
+// Trace each memory access.
+#define SHEMU_OPT_TRACE_MEMORY 0x0000000000000008
+
+// Trace each identified dynamically constructed string.
+#define SHEMU_OPT_TRACE_STRINGS 0x0000000000000010
+
+// Shellcode is directly mapped, and it is not read in a dedicated buffer. No stores can be done to it. This
+// allows for arbitrarly sized shellcodes to be emulated without the need to allocate separate memory & do
+// copied of the target shellcode. Internally, pieces of the shellcode may still be cached.
+// The size of IntBuf must be equal only to the size of the stack plus one page, and no extra memory
+// needs to be allocated for the shellcode. When using this flag, the following features will not be available:
+// 1. UniqueCount - it will simply indicate the total number of instructions emulated, NOT the number of unique
+// instructions emulated
+// 2. WRITE_SELF - self-write detection will be disabled
+// Other features will work normally, as they don't require state tracking inside the IntBuf.
+// When using this option, the SHEMU_OPT_BYPASS_SELF_WRITES is forced as well.
+#define SHEMU_OPT_DIRECT_MAPPED_SHELL 0x0000000000000020
+
+// Trace each identified loop.
+#define SHEMU_OPT_TRACE_LOOPS 0x0000000000000080
+
+// Indicates that AES instructions are supported, and therefore, the AES intrinsics can be used to emulate
+// AES decryption.
+#define SHEMU_OPT_SUPPORT_AES 0x0000000100000000
+// Emulate with APX support enabled. If not provided, APX and REX2 prefixed instructions will cause emulation to
+// stop.
+#define SHEMU_OPT_SUPPORT_APX 0x0000000200000000
+
+
+
+
+//
+// At least this amount must be allocated for internal use.
+//
+#define SHEMU_INTERNAL_BUFFER_SIZE(ctx) ((ctx)->ShellcodeSize + (ctx)->StackSize)
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// API
+//
+SHEMU_STATUS
+ShemuX86Emulate(
+ SHEMU_CONTEXT *Context
+ );
+
+SHEMU_STATUS
+ShemuEmulate(
+ SHEMU_CONTEXT *Context
+ );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BDSHEMU_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bdshemu_x86.h b/compiler-rt/lib/interception/bddisasm/inc/bdshemu_x86.h
new file mode 100644
index 00000000000000..9a216106955094
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bdshemu_x86.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDSHEMU_X86_
+#define BDSHEMU_X86_
+
+#include "bddisasm_types.h"
+
+
+//
+// General purpose registers.
+//
+typedef struct _SHEMU_X86_GPR_REGS
+{
+ ND_UINT64 RegRax;
+ ND_UINT64 RegRcx;
+ ND_UINT64 RegRdx;
+ ND_UINT64 RegRbx;
+ ND_UINT64 RegRsp;
+ ND_UINT64 RegRbp;
+ ND_UINT64 RegRsi;
+ ND_UINT64 RegRdi;
+ ND_UINT64 RegR8;
+ ND_UINT64 RegR9;
+ ND_UINT64 RegR10;
+ ND_UINT64 RegR11;
+ ND_UINT64 RegR12;
+ ND_UINT64 RegR13;
+ ND_UINT64 RegR14;
+ ND_UINT64 RegR15;
+ ND_UINT64 RegR16;
+ ND_UINT64 RegR17;
+ ND_UINT64 RegR18;
+ ND_UINT64 RegR19;
+ ND_UINT64 RegR20;
+ ND_UINT64 RegR21;
+ ND_UINT64 RegR22;
+ ND_UINT64 RegR23;
+ ND_UINT64 RegR24;
+ ND_UINT64 RegR25;
+ ND_UINT64 RegR26;
+ ND_UINT64 RegR27;
+ ND_UINT64 RegR28;
+ ND_UINT64 RegR29;
+ ND_UINT64 RegR30;
+ ND_UINT64 RegR31;
+ ND_UINT64 RegCr2;
+ ND_UINT64 RegFlags;
+ ND_UINT64 RegDr7;
+ ND_UINT64 RegRip;
+ ND_UINT64 RegCr0;
+ ND_UINT64 RegCr4;
+ ND_UINT64 RegCr3;
+ ND_UINT64 RegCr8;
+ ND_UINT64 RegIdtBase;
+ ND_UINT64 RegIdtLimit;
+ ND_UINT64 RegGdtBase;
+ ND_UINT64 RegGdtLimit;
+ ND_UINT64 FpuRip;
+} SHEMU_X86_GPR_REGS, *PSHEMU_X86_GPR_REGS;
+
+
+//
+// Segment register (with its hidden part).
+//
+typedef struct _SHEMU_X86_SEG
+{
+ ND_UINT64 Base;
+ ND_UINT64 Limit;
+ ND_UINT64 Selector;
+ ND_UINT64 AccessRights;
+} SHEMU_X86_SEG, *PSHEMU_X86_SEG;
+
+
+//
+// The segment registers.
+//
+typedef struct _SHEMU_X86_SEG_REGS
+{
+ SHEMU_X86_SEG Es;
+ SHEMU_X86_SEG Cs;
+ SHEMU_X86_SEG Ss;
+ SHEMU_X86_SEG Ds;
+ SHEMU_X86_SEG Fs;
+ SHEMU_X86_SEG Gs;
+} SHEMU_X86_SEG_REGS, *PSHEMU_X86_SEG_REGS;
+
+#endif
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bdx86_constants.h b/compiler-rt/lib/interception/bddisasm/inc/bdx86_constants.h
new file mode 100644
index 00000000000000..4c94b4c04291a0
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bdx86_constants.h
@@ -0,0 +1,2044 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_CONSTANTS_H
+#define BDX86_CONSTANTS_H
+
+
+typedef enum _ND_INS_CLASS
+{
+ ND_INS_INVALID = 0,
+ ND_INS_AAA,
+ ND_INS_AAD,
+ ND_INS_AADD,
+ ND_INS_AAM,
+ ND_INS_AAND,
+ ND_INS_AAS,
+ ND_INS_ADC,
+ ND_INS_ADCX,
+ ND_INS_ADD,
+ ND_INS_ADDPD,
+ ND_INS_ADDPS,
+ ND_INS_ADDSD,
+ ND_INS_ADDSS,
+ ND_INS_ADDSUBPD,
+ ND_INS_ADDSUBPS,
+ ND_INS_ADOX,
+ ND_INS_AESDEC,
+ ND_INS_AESDEC128KL,
+ ND_INS_AESDEC256KL,
+ ND_INS_AESDECLAST,
+ ND_INS_AESDECWIDE128KL,
+ ND_INS_AESDECWIDE256KL,
+ ND_INS_AESENC,
+ ND_INS_AESENC128KL,
+ ND_INS_AESENC256KL,
+ ND_INS_AESENCLAST,
+ ND_INS_AESENCWIDE128KL,
+ ND_INS_AESENCWIDE256KL,
+ ND_INS_AESIMC,
+ ND_INS_AESKEYGENASSIST,
+ ND_INS_AND,
+ ND_INS_ANDN,
+ ND_INS_ANDNPD,
+ ND_INS_ANDNPS,
+ ND_INS_ANDPD,
+ ND_INS_ANDPS,
+ ND_INS_AOR,
+ ND_INS_ARPL,
+ ND_INS_AXOR,
+ ND_INS_BEXTR,
+ ND_INS_BLCFILL,
+ ND_INS_BLCI,
+ ND_INS_BLCIC,
+ ND_INS_BLCMSK,
+ ND_INS_BLCS,
+ ND_INS_BLENDPD,
+ ND_INS_BLENDPS,
+ ND_INS_BLENDVPD,
+ ND_INS_BLENDVPS,
+ ND_INS_BLSFILL,
+ ND_INS_BLSI,
+ ND_INS_BLSIC,
+ ND_INS_BLSMSK,
+ ND_INS_BLSR,
+ ND_INS_BNDCL,
+ ND_INS_BNDCN,
+ ND_INS_BNDCU,
+ ND_INS_BNDLDX,
+ ND_INS_BNDMK,
+ ND_INS_BNDMOV,
+ ND_INS_BNDSTX,
+ ND_INS_BOUND,
+ ND_INS_BSF,
+ ND_INS_BSR,
+ ND_INS_BSWAP,
+ ND_INS_BT,
+ ND_INS_BTC,
+ ND_INS_BTR,
+ ND_INS_BTS,
+ ND_INS_BZHI,
+ ND_INS_CALLFD,
+ ND_INS_CALLFI,
+ ND_INS_CALLNI,
+ ND_INS_CALLNR,
+ ND_INS_CBW,
+ ND_INS_CCMP,
+ ND_INS_CDQ,
+ ND_INS_CDQE,
+ ND_INS_CFCMOV,
+ ND_INS_CLAC,
+ ND_INS_CLC,
+ ND_INS_CLD,
+ ND_INS_CLDEMOTE,
+ ND_INS_CLEVICT0,
+ ND_INS_CLEVICT1,
+ ND_INS_CLFLUSH,
+ ND_INS_CLFLUSHOPT,
+ ND_INS_CLGI,
+ ND_INS_CLI,
+ ND_INS_CLRSSBSY,
+ ND_INS_CLTS,
+ ND_INS_CLUI,
+ ND_INS_CLWB,
+ ND_INS_CLZERO,
+ ND_INS_CMC,
+ ND_INS_CMOVcc,
+ ND_INS_CMP,
+ ND_INS_CMPBEXADD,
+ ND_INS_CMPCXADD,
+ ND_INS_CMPLEXADD,
+ ND_INS_CMPLXADD,
+ ND_INS_CMPNBEXADD,
+ ND_INS_CMPNCXADD,
+ ND_INS_CMPNLEXADD,
+ ND_INS_CMPNLXADD,
+ ND_INS_CMPNOXADD,
+ ND_INS_CMPNPXADD,
+ ND_INS_CMPNSXADD,
+ ND_INS_CMPNZXADD,
+ ND_INS_CMPOXADD,
+ ND_INS_CMPPD,
+ ND_INS_CMPPS,
+ ND_INS_CMPPXADD,
+ ND_INS_CMPS,
+ ND_INS_CMPSD,
+ ND_INS_CMPSS,
+ ND_INS_CMPSXADD,
+ ND_INS_CMPXCHG,
+ ND_INS_CMPXCHG16B,
+ ND_INS_CMPXCHG8B,
+ ND_INS_CMPZXADD,
+ ND_INS_COMISD,
+ ND_INS_COMISS,
+ ND_INS_CPUID,
+ ND_INS_CQO,
+ ND_INS_CRC32,
+ ND_INS_CTEST,
+ ND_INS_CVTDQ2PD,
+ ND_INS_CVTDQ2PS,
+ ND_INS_CVTPD2DQ,
+ ND_INS_CVTPD2PI,
+ ND_INS_CVTPD2PS,
+ ND_INS_CVTPI2PD,
+ ND_INS_CVTPI2PS,
+ ND_INS_CVTPS2DQ,
+ ND_INS_CVTPS2PD,
+ ND_INS_CVTPS2PI,
+ ND_INS_CVTSD2SI,
+ ND_INS_CVTSD2SS,
+ ND_INS_CVTSI2SD,
+ ND_INS_CVTSI2SS,
+ ND_INS_CVTSS2SD,
+ ND_INS_CVTSS2SI,
+ ND_INS_CVTTPD2DQ,
+ ND_INS_CVTTPD2PI,
+ ND_INS_CVTTPS2DQ,
+ ND_INS_CVTTPS2PI,
+ ND_INS_CVTTSD2SI,
+ ND_INS_CVTTSS2SI,
+ ND_INS_CWD,
+ ND_INS_CWDE,
+ ND_INS_DAA,
+ ND_INS_DAS,
+ ND_INS_DEC,
+ ND_INS_DELAY,
+ ND_INS_DIV,
+ ND_INS_DIVPD,
+ ND_INS_DIVPS,
+ ND_INS_DIVSD,
+ ND_INS_DIVSS,
+ ND_INS_DPPD,
+ ND_INS_DPPS,
+ ND_INS_EMMS,
+ ND_INS_ENCLS,
+ ND_INS_ENCLU,
+ ND_INS_ENCLV,
+ ND_INS_ENCODEKEY128,
+ ND_INS_ENCODEKEY256,
+ ND_INS_ENDBR,
+ ND_INS_ENQCMD,
+ ND_INS_ENQCMDS,
+ ND_INS_ENTER,
+ ND_INS_ERETS,
+ ND_INS_ERETU,
+ ND_INS_EXTRACTPS,
+ ND_INS_EXTRQ,
+ ND_INS_F2XM1,
+ ND_INS_FABS,
+ ND_INS_FADD,
+ ND_INS_FADDP,
+ ND_INS_FBLD,
+ ND_INS_FBSTP,
+ ND_INS_FCHS,
+ ND_INS_FCMOVB,
+ ND_INS_FCMOVBE,
+ ND_INS_FCMOVE,
+ ND_INS_FCMOVNB,
+ ND_INS_FCMOVNBE,
+ ND_INS_FCMOVNE,
+ ND_INS_FCMOVNU,
+ ND_INS_FCMOVU,
+ ND_INS_FCOM,
+ ND_INS_FCOMI,
+ ND_INS_FCOMIP,
+ ND_INS_FCOMP,
+ ND_INS_FCOMPP,
+ ND_INS_FCOS,
+ ND_INS_FDECSTP,
+ ND_INS_FDIV,
+ ND_INS_FDIVP,
+ ND_INS_FDIVR,
+ ND_INS_FDIVRP,
+ ND_INS_FEMMS,
+ ND_INS_FFREE,
+ ND_INS_FFREEP,
+ ND_INS_FIADD,
+ ND_INS_FICOM,
+ ND_INS_FICOMP,
+ ND_INS_FIDIV,
+ ND_INS_FIDIVR,
+ ND_INS_FILD,
+ ND_INS_FIMUL,
+ ND_INS_FINCSTP,
+ ND_INS_FIST,
+ ND_INS_FISTP,
+ ND_INS_FISTTP,
+ ND_INS_FISUB,
+ ND_INS_FISUBR,
+ ND_INS_FLD,
+ ND_INS_FLD1,
+ ND_INS_FLDCW,
+ ND_INS_FLDENV,
+ ND_INS_FLDL2E,
+ ND_INS_FLDL2T,
+ ND_INS_FLDLG2,
+ ND_INS_FLDLN2,
+ ND_INS_FLDPI,
+ ND_INS_FLDZ,
+ ND_INS_FMUL,
+ ND_INS_FMULP,
+ ND_INS_FNCLEX,
+ ND_INS_FNDISI,
+ ND_INS_FNINIT,
+ ND_INS_FNOP,
+ ND_INS_FNSAVE,
+ ND_INS_FNSTCW,
+ ND_INS_FNSTENV,
+ ND_INS_FNSTSW,
+ ND_INS_FPATAN,
+ ND_INS_FPREM,
+ ND_INS_FPREM1,
+ ND_INS_FPTAN,
+ ND_INS_FRINEAR,
+ ND_INS_FRNDINT,
+ ND_INS_FRSTOR,
+ ND_INS_FSCALE,
+ ND_INS_FSIN,
+ ND_INS_FSINCOS,
+ ND_INS_FSQRT,
+ ND_INS_FST,
+ ND_INS_FSTDW,
+ ND_INS_FSTP,
+ ND_INS_FSTPNCE,
+ ND_INS_FSTSG,
+ ND_INS_FSUB,
+ ND_INS_FSUBP,
+ ND_INS_FSUBR,
+ ND_INS_FSUBRP,
+ ND_INS_FTST,
+ ND_INS_FUCOM,
+ ND_INS_FUCOMI,
+ ND_INS_FUCOMIP,
+ ND_INS_FUCOMP,
+ ND_INS_FUCOMPP,
+ ND_INS_FXAM,
+ ND_INS_FXCH,
+ ND_INS_FXRSTOR,
+ ND_INS_FXRSTOR64,
+ ND_INS_FXSAVE,
+ ND_INS_FXSAVE64,
+ ND_INS_FXTRACT,
+ ND_INS_FYL2X,
+ ND_INS_FYL2XP1,
+ ND_INS_GETSEC,
+ ND_INS_GF2P8AFFINEINVQB,
+ ND_INS_GF2P8AFFINEQB,
+ ND_INS_GF2P8MULB,
+ ND_INS_HADDPD,
+ ND_INS_HADDPS,
+ ND_INS_HLT,
+ ND_INS_HRESET,
+ ND_INS_HSUBPD,
+ ND_INS_HSUBPS,
+ ND_INS_IDIV,
+ ND_INS_IMUL,
+ ND_INS_IN,
+ ND_INS_INC,
+ ND_INS_INCSSP,
+ ND_INS_INS,
+ ND_INS_INSERTPS,
+ ND_INS_INSERTQ,
+ ND_INS_INT,
+ ND_INS_INT1,
+ ND_INS_INT3,
+ ND_INS_INTO,
+ ND_INS_INVD,
+ ND_INS_INVEPT,
+ ND_INS_INVLPG,
+ ND_INS_INVLPGA,
+ ND_INS_INVLPGB,
+ ND_INS_INVPCID,
+ ND_INS_INVVPID,
+ ND_INS_IRET,
+ ND_INS_JMPABS,
+ ND_INS_JMPE,
+ ND_INS_JMPFD,
+ ND_INS_JMPFI,
+ ND_INS_JMPNI,
+ ND_INS_JMPNR,
+ ND_INS_Jcc,
+ ND_INS_JrCXZ,
+ ND_INS_KADD,
+ ND_INS_KAND,
+ ND_INS_KANDN,
+ ND_INS_KMERGE2L1H,
+ ND_INS_KMERGE2L1L,
+ ND_INS_KMOV,
+ ND_INS_KNOT,
+ ND_INS_KOR,
+ ND_INS_KORTEST,
+ ND_INS_KSHIFTL,
+ ND_INS_KSHIFTR,
+ ND_INS_KTEST,
+ ND_INS_KUNPCKBW,
+ ND_INS_KUNPCKDQ,
+ ND_INS_KUNPCKWD,
+ ND_INS_KXNOR,
+ ND_INS_KXOR,
+ ND_INS_LAHF,
+ ND_INS_LAR,
+ ND_INS_LDDQU,
+ ND_INS_LDMXCSR,
+ ND_INS_LDS,
+ ND_INS_LDTILECFG,
+ ND_INS_LEA,
+ ND_INS_LEAVE,
+ ND_INS_LES,
+ ND_INS_LFENCE,
+ ND_INS_LFS,
+ ND_INS_LGDT,
+ ND_INS_LGS,
+ ND_INS_LIDT,
+ ND_INS_LKGS,
+ ND_INS_LLDT,
+ ND_INS_LLWPCB,
+ ND_INS_LMSW,
+ ND_INS_LOADIWKEY,
+ ND_INS_LODS,
+ ND_INS_LOOP,
+ ND_INS_LOOPNZ,
+ ND_INS_LOOPZ,
+ ND_INS_LSL,
+ ND_INS_LSS,
+ ND_INS_LTR,
+ ND_INS_LWPINS,
+ ND_INS_LWPVAL,
+ ND_INS_LZCNT,
+ ND_INS_MASKMOVDQU,
+ ND_INS_MASKMOVQ,
+ ND_INS_MAXPD,
+ ND_INS_MAXPS,
+ ND_INS_MAXSD,
+ ND_INS_MAXSS,
+ ND_INS_MCOMMIT,
+ ND_INS_MFENCE,
+ ND_INS_MINPD,
+ ND_INS_MINPS,
+ ND_INS_MINSD,
+ ND_INS_MINSS,
+ ND_INS_MONITOR,
+ ND_INS_MONITORX,
+ ND_INS_MOV,
+ ND_INS_MOVAPD,
+ ND_INS_MOVAPS,
+ ND_INS_MOVBE,
+ ND_INS_MOVD,
+ ND_INS_MOVDDUP,
+ ND_INS_MOVDIR64B,
+ ND_INS_MOVDIRI,
+ ND_INS_MOVDQ2Q,
+ ND_INS_MOVDQA,
+ ND_INS_MOVDQU,
+ ND_INS_MOVHLPS,
+ ND_INS_MOVHPD,
+ ND_INS_MOVHPS,
+ ND_INS_MOVLHPS,
+ ND_INS_MOVLPD,
+ ND_INS_MOVLPS,
+ ND_INS_MOVMSKPD,
+ ND_INS_MOVMSKPS,
+ ND_INS_MOVNTDQ,
+ ND_INS_MOVNTDQA,
+ ND_INS_MOVNTI,
+ ND_INS_MOVNTPD,
+ ND_INS_MOVNTPS,
+ ND_INS_MOVNTQ,
+ ND_INS_MOVNTSD,
+ ND_INS_MOVNTSS,
+ ND_INS_MOVQ,
+ ND_INS_MOVQ2DQ,
+ ND_INS_MOVRS,
+ ND_INS_MOVS,
+ ND_INS_MOVSD,
+ ND_INS_MOVSHDUP,
+ ND_INS_MOVSLDUP,
+ ND_INS_MOVSS,
+ ND_INS_MOVSX,
+ ND_INS_MOVSXD,
+ ND_INS_MOVUPD,
+ ND_INS_MOVUPS,
+ ND_INS_MOVZX,
+ ND_INS_MOV_CR,
+ ND_INS_MOV_DR,
+ ND_INS_MOV_TR,
+ ND_INS_MPSADBW,
+ ND_INS_MUL,
+ ND_INS_MULPD,
+ ND_INS_MULPS,
+ ND_INS_MULSD,
+ ND_INS_MULSS,
+ ND_INS_MULX,
+ ND_INS_MWAIT,
+ ND_INS_MWAITX,
+ ND_INS_NEG,
+ ND_INS_NOP,
+ ND_INS_NOT,
+ ND_INS_OR,
+ ND_INS_ORPD,
+ ND_INS_ORPS,
+ ND_INS_OUT,
+ ND_INS_OUTS,
+ ND_INS_PABSB,
+ ND_INS_PABSD,
+ ND_INS_PABSW,
+ ND_INS_PACKSSDW,
+ ND_INS_PACKSSWB,
+ ND_INS_PACKUSDW,
+ ND_INS_PACKUSWB,
+ ND_INS_PADDB,
+ ND_INS_PADDD,
+ ND_INS_PADDQ,
+ ND_INS_PADDSB,
+ ND_INS_PADDSW,
+ ND_INS_PADDUSB,
+ ND_INS_PADDUSW,
+ ND_INS_PADDW,
+ ND_INS_PALIGNR,
+ ND_INS_PAND,
+ ND_INS_PANDN,
+ ND_INS_PAUSE,
+ ND_INS_PAVGB,
+ ND_INS_PAVGUSB,
+ ND_INS_PAVGW,
+ ND_INS_PBLENDVB,
+ ND_INS_PBLENDW,
+ ND_INS_PBNDKB,
+ ND_INS_PCLMULQDQ,
+ ND_INS_PCMPEQB,
+ ND_INS_PCMPEQD,
+ ND_INS_PCMPEQQ,
+ ND_INS_PCMPEQW,
+ ND_INS_PCMPESTRI,
+ ND_INS_PCMPESTRM,
+ ND_INS_PCMPGTB,
+ ND_INS_PCMPGTD,
+ ND_INS_PCMPGTQ,
+ ND_INS_PCMPGTW,
+ ND_INS_PCMPISTRI,
+ ND_INS_PCMPISTRM,
+ ND_INS_PCONFIG,
+ ND_INS_PDEP,
+ ND_INS_PEXT,
+ ND_INS_PEXTRB,
+ ND_INS_PEXTRD,
+ ND_INS_PEXTRQ,
+ ND_INS_PEXTRW,
+ ND_INS_PF2ID,
+ ND_INS_PF2IW,
+ ND_INS_PFACC,
+ ND_INS_PFADD,
+ ND_INS_PFCMPEQ,
+ ND_INS_PFCMPGE,
+ ND_INS_PFCMPGT,
+ ND_INS_PFMAX,
+ ND_INS_PFMIN,
+ ND_INS_PFMUL,
+ ND_INS_PFNACC,
+ ND_INS_PFPNACC,
+ ND_INS_PFRCP,
+ ND_INS_PFRCPIT1,
+ ND_INS_PFRCPIT2,
+ ND_INS_PFRCPV,
+ ND_INS_PFRSQIT1,
+ ND_INS_PFRSQRT,
+ ND_INS_PFRSQRTV,
+ ND_INS_PFSUB,
+ ND_INS_PFSUBR,
+ ND_INS_PHADDD,
+ ND_INS_PHADDSW,
+ ND_INS_PHADDW,
+ ND_INS_PHMINPOSUW,
+ ND_INS_PHSUBD,
+ ND_INS_PHSUBSW,
+ ND_INS_PHSUBW,
+ ND_INS_PI2FD,
+ ND_INS_PI2FW,
+ ND_INS_PINSRB,
+ ND_INS_PINSRD,
+ ND_INS_PINSRQ,
+ ND_INS_PINSRW,
+ ND_INS_PMADDUBSW,
+ ND_INS_PMADDWD,
+ ND_INS_PMAXSB,
+ ND_INS_PMAXSD,
+ ND_INS_PMAXSW,
+ ND_INS_PMAXUB,
+ ND_INS_PMAXUD,
+ ND_INS_PMAXUW,
+ ND_INS_PMINSB,
+ ND_INS_PMINSD,
+ ND_INS_PMINSW,
+ ND_INS_PMINUB,
+ ND_INS_PMINUD,
+ ND_INS_PMINUW,
+ ND_INS_PMOVMSKB,
+ ND_INS_PMOVSXBD,
+ ND_INS_PMOVSXBQ,
+ ND_INS_PMOVSXBW,
+ ND_INS_PMOVSXDQ,
+ ND_INS_PMOVSXWD,
+ ND_INS_PMOVSXWQ,
+ ND_INS_PMOVZXBD,
+ ND_INS_PMOVZXBQ,
+ ND_INS_PMOVZXBW,
+ ND_INS_PMOVZXDQ,
+ ND_INS_PMOVZXWD,
+ ND_INS_PMOVZXWQ,
+ ND_INS_PMULDQ,
+ ND_INS_PMULHRSW,
+ ND_INS_PMULHRW,
+ ND_INS_PMULHUW,
+ ND_INS_PMULHW,
+ ND_INS_PMULLD,
+ ND_INS_PMULLW,
+ ND_INS_PMULUDQ,
+ ND_INS_POP,
+ ND_INS_POP2,
+ ND_INS_POP2P,
+ ND_INS_POPA,
+ ND_INS_POPAD,
+ ND_INS_POPCNT,
+ ND_INS_POPF,
+ ND_INS_POPP,
+ ND_INS_POR,
+ ND_INS_PREFETCH,
+ ND_INS_PREFETCHE,
+ ND_INS_PREFETCHIT0,
+ ND_INS_PREFETCHIT1,
+ ND_INS_PREFETCHM,
+ ND_INS_PREFETCHNTA,
+ ND_INS_PREFETCHRST2,
+ ND_INS_PREFETCHT0,
+ ND_INS_PREFETCHT1,
+ ND_INS_PREFETCHT2,
+ ND_INS_PREFETCHW,
+ ND_INS_PREFETCHWT1,
+ ND_INS_PSADBW,
+ ND_INS_PSHUFB,
+ ND_INS_PSHUFD,
+ ND_INS_PSHUFHW,
+ ND_INS_PSHUFLW,
+ ND_INS_PSHUFW,
+ ND_INS_PSIGNB,
+ ND_INS_PSIGND,
+ ND_INS_PSIGNW,
+ ND_INS_PSLLD,
+ ND_INS_PSLLDQ,
+ ND_INS_PSLLQ,
+ ND_INS_PSLLW,
+ ND_INS_PSMASH,
+ ND_INS_PSRAD,
+ ND_INS_PSRAW,
+ ND_INS_PSRLD,
+ ND_INS_PSRLDQ,
+ ND_INS_PSRLQ,
+ ND_INS_PSRLW,
+ ND_INS_PSUBB,
+ ND_INS_PSUBD,
+ ND_INS_PSUBQ,
+ ND_INS_PSUBSB,
+ ND_INS_PSUBSW,
+ ND_INS_PSUBUSB,
+ ND_INS_PSUBUSW,
+ ND_INS_PSUBW,
+ ND_INS_PSWAPD,
+ ND_INS_PTEST,
+ ND_INS_PTWRITE,
+ ND_INS_PUNPCKHBW,
+ ND_INS_PUNPCKHDQ,
+ ND_INS_PUNPCKHQDQ,
+ ND_INS_PUNPCKHWD,
+ ND_INS_PUNPCKLBW,
+ ND_INS_PUNPCKLDQ,
+ ND_INS_PUNPCKLQDQ,
+ ND_INS_PUNPCKLWD,
+ ND_INS_PUSH,
+ ND_INS_PUSH2,
+ ND_INS_PUSH2P,
+ ND_INS_PUSHA,
+ ND_INS_PUSHAD,
+ ND_INS_PUSHF,
+ ND_INS_PUSHP,
+ ND_INS_PVALIDATE,
+ ND_INS_PXOR,
+ ND_INS_RCL,
+ ND_INS_RCPPS,
+ ND_INS_RCPSS,
+ ND_INS_RCR,
+ ND_INS_RDFSBASE,
+ ND_INS_RDGSBASE,
+ ND_INS_RDMSR,
+ ND_INS_RDMSRLIST,
+ ND_INS_RDPID,
+ ND_INS_RDPKRU,
+ ND_INS_RDPMC,
+ ND_INS_RDPRU,
+ ND_INS_RDRAND,
+ ND_INS_RDSEED,
+ ND_INS_RDTSC,
+ ND_INS_RDTSCP,
+ ND_INS_RETF,
+ ND_INS_RETN,
+ ND_INS_RMPADJUST,
+ ND_INS_RMPQUERY,
+ ND_INS_RMPREAD,
+ ND_INS_RMPUPDATE,
+ ND_INS_ROL,
+ ND_INS_ROR,
+ ND_INS_RORX,
+ ND_INS_ROUNDPD,
+ ND_INS_ROUNDPS,
+ ND_INS_ROUNDSD,
+ ND_INS_ROUNDSS,
+ ND_INS_RSM,
+ ND_INS_RSQRTPS,
+ ND_INS_RSQRTSS,
+ ND_INS_RSSSP,
+ ND_INS_RSTORSSP,
+ ND_INS_SAHF,
+ ND_INS_SAL,
+ ND_INS_SALC,
+ ND_INS_SAR,
+ ND_INS_SARX,
+ ND_INS_SAVEPREVSSP,
+ ND_INS_SBB,
+ ND_INS_SCAS,
+ ND_INS_SEAMCALL,
+ ND_INS_SEAMOPS,
+ ND_INS_SEAMRET,
+ ND_INS_SENDUIPI,
+ ND_INS_SERIALIZE,
+ ND_INS_SETSSBSY,
+ ND_INS_SETcc,
+ ND_INS_SFENCE,
+ ND_INS_SGDT,
+ ND_INS_SHA1MSG1,
+ ND_INS_SHA1MSG2,
+ ND_INS_SHA1NEXTE,
+ ND_INS_SHA1RNDS4,
+ ND_INS_SHA256MSG1,
+ ND_INS_SHA256MSG2,
+ ND_INS_SHA256RNDS2,
+ ND_INS_SHL,
+ ND_INS_SHLD,
+ ND_INS_SHLX,
+ ND_INS_SHR,
+ ND_INS_SHRD,
+ ND_INS_SHRX,
+ ND_INS_SHUFPD,
+ ND_INS_SHUFPS,
+ ND_INS_SIDT,
+ ND_INS_SKINIT,
+ ND_INS_SLDT,
+ ND_INS_SLWPCB,
+ ND_INS_SMSW,
+ ND_INS_SPFLT,
+ ND_INS_SQRTPD,
+ ND_INS_SQRTPS,
+ ND_INS_SQRTSD,
+ ND_INS_SQRTSS,
+ ND_INS_STAC,
+ ND_INS_STC,
+ ND_INS_STD,
+ ND_INS_STGI,
+ ND_INS_STI,
+ ND_INS_STMXCSR,
+ ND_INS_STOS,
+ ND_INS_STR,
+ ND_INS_STTILECFG,
+ ND_INS_STUI,
+ ND_INS_SUB,
+ ND_INS_SUBPD,
+ ND_INS_SUBPS,
+ ND_INS_SUBSD,
+ ND_INS_SUBSS,
+ ND_INS_SWAPGS,
+ ND_INS_SYSCALL,
+ ND_INS_SYSENTER,
+ ND_INS_SYSEXIT,
+ ND_INS_SYSRET,
+ ND_INS_T1MSKC,
+ ND_INS_T2RPNTLVWZ0,
+ ND_INS_T2RPNTLVWZ0RS,
+ ND_INS_T2RPNTLVWZ0RST1,
+ ND_INS_T2RPNTLVWZ0T1,
+ ND_INS_T2RPNTLVWZ1,
+ ND_INS_T2RPNTLVWZ1RS,
+ ND_INS_T2RPNTLVWZ1RST1,
+ ND_INS_T2RPNTLVWZ1T1,
+ ND_INS_TCMMIMFP16PS,
+ ND_INS_TCMMRLFP16PS,
+ ND_INS_TCONJTCMMIMFP16PS,
+ ND_INS_TCONJTFP16,
+ ND_INS_TCVTROWD2PS,
+ ND_INS_TCVTROWPS2PBF16H,
+ ND_INS_TCVTROWPS2PBF16L,
+ ND_INS_TCVTROWPS2PHH,
+ ND_INS_TCVTROWPS2PHL,
+ ND_INS_TDCALL,
+ ND_INS_TDPBF16PS,
+ ND_INS_TDPBF8PS,
+ ND_INS_TDPBHF8PS,
+ ND_INS_TDPBSSD,
+ ND_INS_TDPBSUD,
+ ND_INS_TDPBUSD,
+ ND_INS_TDPBUUD,
+ ND_INS_TDPFP16PS,
+ ND_INS_TDPHBF8PS,
+ ND_INS_TDPHF8PS,
+ ND_INS_TEST,
+ ND_INS_TESTUI,
+ ND_INS_TILELOADD,
+ ND_INS_TILELOADDRS,
+ ND_INS_TILELOADDRST1,
+ ND_INS_TILELOADDT1,
+ ND_INS_TILEMOVROW,
+ ND_INS_TILERELEASE,
+ ND_INS_TILESTORED,
+ ND_INS_TILEZERO,
+ ND_INS_TLBSYNC,
+ ND_INS_TMMULTF32PS,
+ ND_INS_TPAUSE,
+ ND_INS_TTCMMIMFP16PS,
+ ND_INS_TTCMMRLFP16PS,
+ ND_INS_TTDPBF16PS,
+ ND_INS_TTDPFP16PS,
+ ND_INS_TTMMULTF32PS,
+ ND_INS_TTRANSPOSED,
+ ND_INS_TZCNT,
+ ND_INS_TZMSK,
+ ND_INS_UCOMISD,
+ ND_INS_UCOMISS,
+ ND_INS_UD0,
+ ND_INS_UD1,
+ ND_INS_UD2,
+ ND_INS_UIRET,
+ ND_INS_UMONITOR,
+ ND_INS_UMWAIT,
+ ND_INS_UNPCKHPD,
+ ND_INS_UNPCKHPS,
+ ND_INS_UNPCKLPD,
+ ND_INS_UNPCKLPS,
+ ND_INS_URDMSR,
+ ND_INS_UWRMSR,
+ ND_INS_V4FMADDPS,
+ ND_INS_V4FMADDSS,
+ ND_INS_V4FNMADDPS,
+ ND_INS_V4FNMADDSS,
+ ND_INS_VADDNEPBF16,
+ ND_INS_VADDPD,
+ ND_INS_VADDPH,
+ ND_INS_VADDPS,
+ ND_INS_VADDSD,
+ ND_INS_VADDSH,
+ ND_INS_VADDSS,
+ ND_INS_VADDSUBPD,
+ ND_INS_VADDSUBPS,
+ ND_INS_VAESDEC,
+ ND_INS_VAESDECLAST,
+ ND_INS_VAESENC,
+ ND_INS_VAESENCLAST,
+ ND_INS_VAESIMC,
+ ND_INS_VAESKEYGENASSIST,
+ ND_INS_VALIGND,
+ ND_INS_VALIGNQ,
+ ND_INS_VANDNPD,
+ ND_INS_VANDNPS,
+ ND_INS_VANDPD,
+ ND_INS_VANDPS,
+ ND_INS_VBCSTNEBF162PS,
+ ND_INS_VBCSTNESH2PS,
+ ND_INS_VBLENDMPD,
+ ND_INS_VBLENDMPS,
+ ND_INS_VBLENDPD,
+ ND_INS_VBLENDPS,
+ ND_INS_VBLENDVPD,
+ ND_INS_VBLENDVPS,
+ ND_INS_VBROADCASTF128,
+ ND_INS_VBROADCASTF32X2,
+ ND_INS_VBROADCASTF32X4,
+ ND_INS_VBROADCASTF32X8,
+ ND_INS_VBROADCASTF64X2,
+ ND_INS_VBROADCASTF64X4,
+ ND_INS_VBROADCASTI128,
+ ND_INS_VBROADCASTI32X2,
+ ND_INS_VBROADCASTI32X4,
+ ND_INS_VBROADCASTI32X8,
+ ND_INS_VBROADCASTI64X2,
+ ND_INS_VBROADCASTI64X4,
+ ND_INS_VBROADCASTSD,
+ ND_INS_VBROADCASTSS,
+ ND_INS_VCMPPBF16,
+ ND_INS_VCMPPD,
+ ND_INS_VCMPPH,
+ ND_INS_VCMPPS,
+ ND_INS_VCMPSD,
+ ND_INS_VCMPSH,
+ ND_INS_VCMPSS,
+ ND_INS_VCOMISD,
+ ND_INS_VCOMISH,
+ ND_INS_VCOMISS,
+ ND_INS_VCOMPRESSPD,
+ ND_INS_VCOMPRESSPS,
+ ND_INS_VCOMSBF16,
+ ND_INS_VCOMXSD,
+ ND_INS_VCOMXSH,
+ ND_INS_VCOMXSS,
+ ND_INS_VCVT2PS2PHX,
+ ND_INS_VCVTBIASPH2BF8,
+ ND_INS_VCVTBIASPH2BF8S,
+ ND_INS_VCVTBIASPH2HF8,
+ ND_INS_VCVTBIASPH2HF8S,
+ ND_INS_VCVTDQ2PD,
+ ND_INS_VCVTDQ2PH,
+ ND_INS_VCVTDQ2PS,
+ ND_INS_VCVTHF82PH,
+ ND_INS_VCVTNE2PH2BF8,
+ ND_INS_VCVTNE2PH2BF8S,
+ ND_INS_VCVTNE2PH2HF8,
+ ND_INS_VCVTNE2PH2HF8S,
+ ND_INS_VCVTNE2PS2BF16,
+ ND_INS_VCVTNEBF162IBS,
+ ND_INS_VCVTNEBF162IUBS,
+ ND_INS_VCVTNEEBF162PS,
+ ND_INS_VCVTNEEPH2PS,
+ ND_INS_VCVTNEOBF162PS,
+ ND_INS_VCVTNEOPH2PS,
+ ND_INS_VCVTNEPH2BF8,
+ ND_INS_VCVTNEPH2BF8S,
+ ND_INS_VCVTNEPH2HF8,
+ ND_INS_VCVTNEPH2HF8S,
+ ND_INS_VCVTNEPS2BF16,
+ ND_INS_VCVTPD2DQ,
+ ND_INS_VCVTPD2PH,
+ ND_INS_VCVTPD2PS,
+ ND_INS_VCVTPD2QQ,
+ ND_INS_VCVTPD2UDQ,
+ ND_INS_VCVTPD2UQQ,
+ ND_INS_VCVTPH2DQ,
+ ND_INS_VCVTPH2IBS,
+ ND_INS_VCVTPH2IUBS,
+ ND_INS_VCVTPH2PD,
+ ND_INS_VCVTPH2PS,
+ ND_INS_VCVTPH2PSX,
+ ND_INS_VCVTPH2QQ,
+ ND_INS_VCVTPH2UDQ,
+ ND_INS_VCVTPH2UQQ,
+ ND_INS_VCVTPH2UW,
+ ND_INS_VCVTPH2W,
+ ND_INS_VCVTPS2DQ,
+ ND_INS_VCVTPS2IBS,
+ ND_INS_VCVTPS2IUBS,
+ ND_INS_VCVTPS2PD,
+ ND_INS_VCVTPS2PH,
+ ND_INS_VCVTPS2PHX,
+ ND_INS_VCVTPS2QQ,
+ ND_INS_VCVTPS2UDQ,
+ ND_INS_VCVTPS2UQQ,
+ ND_INS_VCVTQQ2PD,
+ ND_INS_VCVTQQ2PH,
+ ND_INS_VCVTQQ2PS,
+ ND_INS_VCVTSD2SH,
+ ND_INS_VCVTSD2SI,
+ ND_INS_VCVTSD2SS,
+ ND_INS_VCVTSD2USI,
+ ND_INS_VCVTSH2SD,
+ ND_INS_VCVTSH2SI,
+ ND_INS_VCVTSH2SS,
+ ND_INS_VCVTSH2USI,
+ ND_INS_VCVTSI2SD,
+ ND_INS_VCVTSI2SH,
+ ND_INS_VCVTSI2SS,
+ ND_INS_VCVTSS2SD,
+ ND_INS_VCVTSS2SH,
+ ND_INS_VCVTSS2SI,
+ ND_INS_VCVTSS2USI,
+ ND_INS_VCVTTNEBF162IBS,
+ ND_INS_VCVTTNEBF162IUBS,
+ ND_INS_VCVTTPD2DQ,
+ ND_INS_VCVTTPD2DQS,
+ ND_INS_VCVTTPD2QQ,
+ ND_INS_VCVTTPD2QQS,
+ ND_INS_VCVTTPD2UDQ,
+ ND_INS_VCVTTPD2UDQS,
+ ND_INS_VCVTTPD2UQQ,
+ ND_INS_VCVTTPD2UQQS,
+ ND_INS_VCVTTPH2DQ,
+ ND_INS_VCVTTPH2IBS,
+ ND_INS_VCVTTPH2IUBS,
+ ND_INS_VCVTTPH2QQ,
+ ND_INS_VCVTTPH2UDQ,
+ ND_INS_VCVTTPH2UQQ,
+ ND_INS_VCVTTPH2UW,
+ ND_INS_VCVTTPH2W,
+ ND_INS_VCVTTPS2DQ,
+ ND_INS_VCVTTPS2DQS,
+ ND_INS_VCVTTPS2IBS,
+ ND_INS_VCVTTPS2IUBS,
+ ND_INS_VCVTTPS2QQ,
+ ND_INS_VCVTTPS2QQS,
+ ND_INS_VCVTTPS2UDQ,
+ ND_INS_VCVTTPS2UDQS,
+ ND_INS_VCVTTPS2UQQ,
+ ND_INS_VCVTTPS2UQQS,
+ ND_INS_VCVTTSD2SI,
+ ND_INS_VCVTTSD2SIS,
+ ND_INS_VCVTTSD2USI,
+ ND_INS_VCVTTSD2USIS,
+ ND_INS_VCVTTSH2SI,
+ ND_INS_VCVTTSH2USI,
+ ND_INS_VCVTTSS2SI,
+ ND_INS_VCVTTSS2SIS,
+ ND_INS_VCVTTSS2USI,
+ ND_INS_VCVTTSS2USIS,
+ ND_INS_VCVTUDQ2PD,
+ ND_INS_VCVTUDQ2PH,
+ ND_INS_VCVTUDQ2PS,
+ ND_INS_VCVTUQQ2PD,
+ ND_INS_VCVTUQQ2PH,
+ ND_INS_VCVTUQQ2PS,
+ ND_INS_VCVTUSI2SD,
+ ND_INS_VCVTUSI2SH,
+ ND_INS_VCVTUSI2SS,
+ ND_INS_VCVTUW2PH,
+ ND_INS_VCVTW2PH,
+ ND_INS_VDBPSADBW,
+ ND_INS_VDIVNEPBF16,
+ ND_INS_VDIVPD,
+ ND_INS_VDIVPH,
+ ND_INS_VDIVPS,
+ ND_INS_VDIVSD,
+ ND_INS_VDIVSH,
+ ND_INS_VDIVSS,
+ ND_INS_VDPBF16PS,
+ ND_INS_VDPPD,
+ ND_INS_VDPPHPS,
+ ND_INS_VDPPS,
+ ND_INS_VERR,
+ ND_INS_VERW,
+ ND_INS_VEXP2PD,
+ ND_INS_VEXP2PS,
+ ND_INS_VEXPANDPD,
+ ND_INS_VEXPANDPS,
+ ND_INS_VEXTRACTF128,
+ ND_INS_VEXTRACTF32X4,
+ ND_INS_VEXTRACTF32X8,
+ ND_INS_VEXTRACTF64X2,
+ ND_INS_VEXTRACTF64X4,
+ ND_INS_VEXTRACTI128,
+ ND_INS_VEXTRACTI32X4,
+ ND_INS_VEXTRACTI32X8,
+ ND_INS_VEXTRACTI64X2,
+ ND_INS_VEXTRACTI64X4,
+ ND_INS_VEXTRACTPS,
+ ND_INS_VFCMADDCPH,
+ ND_INS_VFCMADDCSH,
+ ND_INS_VFCMULCPH,
+ ND_INS_VFCMULCSH,
+ ND_INS_VFIXUPIMMPD,
+ ND_INS_VFIXUPIMMPS,
+ ND_INS_VFIXUPIMMSD,
+ ND_INS_VFIXUPIMMSS,
+ ND_INS_VFMADD132NEPBF16,
+ ND_INS_VFMADD132PD,
+ ND_INS_VFMADD132PH,
+ ND_INS_VFMADD132PS,
+ ND_INS_VFMADD132SD,
+ ND_INS_VFMADD132SH,
+ ND_INS_VFMADD132SS,
+ ND_INS_VFMADD213NEPBF16,
+ ND_INS_VFMADD213PD,
+ ND_INS_VFMADD213PH,
+ ND_INS_VFMADD213PS,
+ ND_INS_VFMADD213SD,
+ ND_INS_VFMADD213SH,
+ ND_INS_VFMADD213SS,
+ ND_INS_VFMADD231NEPBF16,
+ ND_INS_VFMADD231PD,
+ ND_INS_VFMADD231PH,
+ ND_INS_VFMADD231PS,
+ ND_INS_VFMADD231SD,
+ ND_INS_VFMADD231SH,
+ ND_INS_VFMADD231SS,
+ ND_INS_VFMADDCPH,
+ ND_INS_VFMADDCSH,
+ ND_INS_VFMADDPD,
+ ND_INS_VFMADDPS,
+ ND_INS_VFMADDSD,
+ ND_INS_VFMADDSS,
+ ND_INS_VFMADDSUB132PD,
+ ND_INS_VFMADDSUB132PH,
+ ND_INS_VFMADDSUB132PS,
+ ND_INS_VFMADDSUB213PD,
+ ND_INS_VFMADDSUB213PH,
+ ND_INS_VFMADDSUB213PS,
+ ND_INS_VFMADDSUB231PD,
+ ND_INS_VFMADDSUB231PH,
+ ND_INS_VFMADDSUB231PS,
+ ND_INS_VFMADDSUBPD,
+ ND_INS_VFMADDSUBPS,
+ ND_INS_VFMSUB132NEPBF16,
+ ND_INS_VFMSUB132PD,
+ ND_INS_VFMSUB132PH,
+ ND_INS_VFMSUB132PS,
+ ND_INS_VFMSUB132SD,
+ ND_INS_VFMSUB132SH,
+ ND_INS_VFMSUB132SS,
+ ND_INS_VFMSUB213NEPBF16,
+ ND_INS_VFMSUB213PD,
+ ND_INS_VFMSUB213PH,
+ ND_INS_VFMSUB213PS,
+ ND_INS_VFMSUB213SD,
+ ND_INS_VFMSUB213SH,
+ ND_INS_VFMSUB213SS,
+ ND_INS_VFMSUB231NEPBF16,
+ ND_INS_VFMSUB231PD,
+ ND_INS_VFMSUB231PH,
+ ND_INS_VFMSUB231PS,
+ ND_INS_VFMSUB231SD,
+ ND_INS_VFMSUB231SH,
+ ND_INS_VFMSUB231SS,
+ ND_INS_VFMSUBADD132PD,
+ ND_INS_VFMSUBADD132PH,
+ ND_INS_VFMSUBADD132PS,
+ ND_INS_VFMSUBADD213PD,
+ ND_INS_VFMSUBADD213PH,
+ ND_INS_VFMSUBADD213PS,
+ ND_INS_VFMSUBADD231PD,
+ ND_INS_VFMSUBADD231PH,
+ ND_INS_VFMSUBADD231PS,
+ ND_INS_VFMSUBADDPD,
+ ND_INS_VFMSUBADDPS,
+ ND_INS_VFMSUBPD,
+ ND_INS_VFMSUBPS,
+ ND_INS_VFMSUBSD,
+ ND_INS_VFMSUBSS,
+ ND_INS_VFMULCPH,
+ ND_INS_VFMULCSH,
+ ND_INS_VFNMADD132NEPBF16,
+ ND_INS_VFNMADD132PD,
+ ND_INS_VFNMADD132PH,
+ ND_INS_VFNMADD132PS,
+ ND_INS_VFNMADD132SD,
+ ND_INS_VFNMADD132SH,
+ ND_INS_VFNMADD132SS,
+ ND_INS_VFNMADD213NEPBF16,
+ ND_INS_VFNMADD213PD,
+ ND_INS_VFNMADD213PH,
+ ND_INS_VFNMADD213PS,
+ ND_INS_VFNMADD213SD,
+ ND_INS_VFNMADD213SH,
+ ND_INS_VFNMADD213SS,
+ ND_INS_VFNMADD231NEPBF16,
+ ND_INS_VFNMADD231PD,
+ ND_INS_VFNMADD231PH,
+ ND_INS_VFNMADD231PS,
+ ND_INS_VFNMADD231SD,
+ ND_INS_VFNMADD231SH,
+ ND_INS_VFNMADD231SS,
+ ND_INS_VFNMADDPD,
+ ND_INS_VFNMADDPS,
+ ND_INS_VFNMADDSD,
+ ND_INS_VFNMADDSS,
+ ND_INS_VFNMSUB132NEPBF16,
+ ND_INS_VFNMSUB132PD,
+ ND_INS_VFNMSUB132PH,
+ ND_INS_VFNMSUB132PS,
+ ND_INS_VFNMSUB132SD,
+ ND_INS_VFNMSUB132SH,
+ ND_INS_VFNMSUB132SS,
+ ND_INS_VFNMSUB213NEPBF16,
+ ND_INS_VFNMSUB213PD,
+ ND_INS_VFNMSUB213PH,
+ ND_INS_VFNMSUB213PS,
+ ND_INS_VFNMSUB213SD,
+ ND_INS_VFNMSUB213SH,
+ ND_INS_VFNMSUB213SS,
+ ND_INS_VFNMSUB231NEPBF16,
+ ND_INS_VFNMSUB231PD,
+ ND_INS_VFNMSUB231PH,
+ ND_INS_VFNMSUB231PS,
+ ND_INS_VFNMSUB231SD,
+ ND_INS_VFNMSUB231SH,
+ ND_INS_VFNMSUB231SS,
+ ND_INS_VFNMSUBPD,
+ ND_INS_VFNMSUBPS,
+ ND_INS_VFNMSUBSD,
+ ND_INS_VFNMSUBSS,
+ ND_INS_VFPCLASSPBF16,
+ ND_INS_VFPCLASSPD,
+ ND_INS_VFPCLASSPH,
+ ND_INS_VFPCLASSPS,
+ ND_INS_VFPCLASSSD,
+ ND_INS_VFPCLASSSH,
+ ND_INS_VFPCLASSSS,
+ ND_INS_VFRCZPD,
+ ND_INS_VFRCZPS,
+ ND_INS_VFRCZSD,
+ ND_INS_VFRCZSS,
+ ND_INS_VGATHERDPD,
+ ND_INS_VGATHERDPS,
+ ND_INS_VGATHERPF0DPD,
+ ND_INS_VGATHERPF0DPS,
+ ND_INS_VGATHERPF0QPD,
+ ND_INS_VGATHERPF0QPS,
+ ND_INS_VGATHERPF1DPD,
+ ND_INS_VGATHERPF1DPS,
+ ND_INS_VGATHERPF1QPD,
+ ND_INS_VGATHERPF1QPS,
+ ND_INS_VGATHERQPD,
+ ND_INS_VGATHERQPS,
+ ND_INS_VGETEXPPBF16,
+ ND_INS_VGETEXPPD,
+ ND_INS_VGETEXPPH,
+ ND_INS_VGETEXPPS,
+ ND_INS_VGETEXPSD,
+ ND_INS_VGETEXPSH,
+ ND_INS_VGETEXPSS,
+ ND_INS_VGETMANTPBF16,
+ ND_INS_VGETMANTPD,
+ ND_INS_VGETMANTPH,
+ ND_INS_VGETMANTPS,
+ ND_INS_VGETMANTSD,
+ ND_INS_VGETMANTSH,
+ ND_INS_VGETMANTSS,
+ ND_INS_VGF2P8AFFINEINVQB,
+ ND_INS_VGF2P8AFFINEQB,
+ ND_INS_VGF2P8MULB,
+ ND_INS_VHADDPD,
+ ND_INS_VHADDPS,
+ ND_INS_VHSUBPD,
+ ND_INS_VHSUBPS,
+ ND_INS_VINSERTF128,
+ ND_INS_VINSERTF32X4,
+ ND_INS_VINSERTF32X8,
+ ND_INS_VINSERTF64X2,
+ ND_INS_VINSERTF64X4,
+ ND_INS_VINSERTI128,
+ ND_INS_VINSERTI32X4,
+ ND_INS_VINSERTI32X8,
+ ND_INS_VINSERTI64X2,
+ ND_INS_VINSERTI64X4,
+ ND_INS_VINSERTPS,
+ ND_INS_VLDDQU,
+ ND_INS_VLDMXCSR,
+ ND_INS_VMASKMOVDQU,
+ ND_INS_VMASKMOVPD,
+ ND_INS_VMASKMOVPS,
+ ND_INS_VMAXPBF16,
+ ND_INS_VMAXPD,
+ ND_INS_VMAXPH,
+ ND_INS_VMAXPS,
+ ND_INS_VMAXSD,
+ ND_INS_VMAXSH,
+ ND_INS_VMAXSS,
+ ND_INS_VMCALL,
+ ND_INS_VMCLEAR,
+ ND_INS_VMFUNC,
+ ND_INS_VMGEXIT,
+ ND_INS_VMINMAXNEPBF16,
+ ND_INS_VMINMAXPD,
+ ND_INS_VMINMAXPH,
+ ND_INS_VMINMAXPS,
+ ND_INS_VMINMAXSD,
+ ND_INS_VMINMAXSH,
+ ND_INS_VMINMAXSS,
+ ND_INS_VMINPBF16,
+ ND_INS_VMINPD,
+ ND_INS_VMINPH,
+ ND_INS_VMINPS,
+ ND_INS_VMINSD,
+ ND_INS_VMINSH,
+ ND_INS_VMINSS,
+ ND_INS_VMLAUNCH,
+ ND_INS_VMLOAD,
+ ND_INS_VMMCALL,
+ ND_INS_VMOVAPD,
+ ND_INS_VMOVAPS,
+ ND_INS_VMOVD,
+ ND_INS_VMOVDDUP,
+ ND_INS_VMOVDQA,
+ ND_INS_VMOVDQA32,
+ ND_INS_VMOVDQA64,
+ ND_INS_VMOVDQU,
+ ND_INS_VMOVDQU16,
+ ND_INS_VMOVDQU32,
+ ND_INS_VMOVDQU64,
+ ND_INS_VMOVDQU8,
+ ND_INS_VMOVHLPS,
+ ND_INS_VMOVHPD,
+ ND_INS_VMOVHPS,
+ ND_INS_VMOVLHPS,
+ ND_INS_VMOVLPD,
+ ND_INS_VMOVLPS,
+ ND_INS_VMOVMSKPD,
+ ND_INS_VMOVMSKPS,
+ ND_INS_VMOVNTDQ,
+ ND_INS_VMOVNTDQA,
+ ND_INS_VMOVNTPD,
+ ND_INS_VMOVNTPS,
+ ND_INS_VMOVQ,
+ ND_INS_VMOVRSB,
+ ND_INS_VMOVRSD,
+ ND_INS_VMOVRSQ,
+ ND_INS_VMOVRSW,
+ ND_INS_VMOVSD,
+ ND_INS_VMOVSH,
+ ND_INS_VMOVSHDUP,
+ ND_INS_VMOVSLDUP,
+ ND_INS_VMOVSS,
+ ND_INS_VMOVUPD,
+ ND_INS_VMOVUPS,
+ ND_INS_VMOVW,
+ ND_INS_VMPSADBW,
+ ND_INS_VMPTRLD,
+ ND_INS_VMPTRST,
+ ND_INS_VMREAD,
+ ND_INS_VMRESUME,
+ ND_INS_VMRUN,
+ ND_INS_VMSAVE,
+ ND_INS_VMULNEPBF16,
+ ND_INS_VMULPD,
+ ND_INS_VMULPH,
+ ND_INS_VMULPS,
+ ND_INS_VMULSD,
+ ND_INS_VMULSH,
+ ND_INS_VMULSS,
+ ND_INS_VMWRITE,
+ ND_INS_VMXOFF,
+ ND_INS_VMXON,
+ ND_INS_VORPD,
+ ND_INS_VORPS,
+ ND_INS_VP2INTERSECTD,
+ ND_INS_VP2INTERSECTQ,
+ ND_INS_VP4DPWSSD,
+ ND_INS_VP4DPWSSDS,
+ ND_INS_VPABSB,
+ ND_INS_VPABSD,
+ ND_INS_VPABSQ,
+ ND_INS_VPABSW,
+ ND_INS_VPACKSSDW,
+ ND_INS_VPACKSSWB,
+ ND_INS_VPACKUSDW,
+ ND_INS_VPACKUSWB,
+ ND_INS_VPADDB,
+ ND_INS_VPADDD,
+ ND_INS_VPADDQ,
+ ND_INS_VPADDSB,
+ ND_INS_VPADDSW,
+ ND_INS_VPADDUSB,
+ ND_INS_VPADDUSW,
+ ND_INS_VPADDW,
+ ND_INS_VPALIGNR,
+ ND_INS_VPAND,
+ ND_INS_VPANDD,
+ ND_INS_VPANDN,
+ ND_INS_VPANDND,
+ ND_INS_VPANDNQ,
+ ND_INS_VPANDQ,
+ ND_INS_VPAVGB,
+ ND_INS_VPAVGW,
+ ND_INS_VPBLENDD,
+ ND_INS_VPBLENDMB,
+ ND_INS_VPBLENDMD,
+ ND_INS_VPBLENDMQ,
+ ND_INS_VPBLENDMW,
+ ND_INS_VPBLENDVB,
+ ND_INS_VPBLENDW,
+ ND_INS_VPBROADCASTB,
+ ND_INS_VPBROADCASTD,
+ ND_INS_VPBROADCASTMB2Q,
+ ND_INS_VPBROADCASTMW2D,
+ ND_INS_VPBROADCASTQ,
+ ND_INS_VPBROADCASTW,
+ ND_INS_VPCLMULQDQ,
+ ND_INS_VPCMOV,
+ ND_INS_VPCMPB,
+ ND_INS_VPCMPD,
+ ND_INS_VPCMPEQB,
+ ND_INS_VPCMPEQD,
+ ND_INS_VPCMPEQQ,
+ ND_INS_VPCMPEQW,
+ ND_INS_VPCMPESTRI,
+ ND_INS_VPCMPESTRM,
+ ND_INS_VPCMPGTB,
+ ND_INS_VPCMPGTD,
+ ND_INS_VPCMPGTQ,
+ ND_INS_VPCMPGTW,
+ ND_INS_VPCMPISTRI,
+ ND_INS_VPCMPISTRM,
+ ND_INS_VPCMPQ,
+ ND_INS_VPCMPUB,
+ ND_INS_VPCMPUD,
+ ND_INS_VPCMPUQ,
+ ND_INS_VPCMPUW,
+ ND_INS_VPCMPW,
+ ND_INS_VPCOMB,
+ ND_INS_VPCOMD,
+ ND_INS_VPCOMPRESSB,
+ ND_INS_VPCOMPRESSD,
+ ND_INS_VPCOMPRESSQ,
+ ND_INS_VPCOMPRESSW,
+ ND_INS_VPCOMQ,
+ ND_INS_VPCOMUB,
+ ND_INS_VPCOMUD,
+ ND_INS_VPCOMUQ,
+ ND_INS_VPCOMUW,
+ ND_INS_VPCOMW,
+ ND_INS_VPCONFLICTD,
+ ND_INS_VPCONFLICTQ,
+ ND_INS_VPDPBSSD,
+ ND_INS_VPDPBSSDS,
+ ND_INS_VPDPBSUD,
+ ND_INS_VPDPBSUDS,
+ ND_INS_VPDPBUSD,
+ ND_INS_VPDPBUSDS,
+ ND_INS_VPDPBUUD,
+ ND_INS_VPDPBUUDS,
+ ND_INS_VPDPWSSD,
+ ND_INS_VPDPWSSDS,
+ ND_INS_VPDPWSUD,
+ ND_INS_VPDPWSUDS,
+ ND_INS_VPDPWUSD,
+ ND_INS_VPDPWUSDS,
+ ND_INS_VPDPWUUD,
+ ND_INS_VPDPWUUDS,
+ ND_INS_VPERM2F128,
+ ND_INS_VPERM2I128,
+ ND_INS_VPERMB,
+ ND_INS_VPERMD,
+ ND_INS_VPERMI2B,
+ ND_INS_VPERMI2D,
+ ND_INS_VPERMI2PD,
+ ND_INS_VPERMI2PS,
+ ND_INS_VPERMI2Q,
+ ND_INS_VPERMI2W,
+ ND_INS_VPERMIL2PD,
+ ND_INS_VPERMIL2PS,
+ ND_INS_VPERMILPD,
+ ND_INS_VPERMILPS,
+ ND_INS_VPERMPD,
+ ND_INS_VPERMPS,
+ ND_INS_VPERMQ,
+ ND_INS_VPERMT2B,
+ ND_INS_VPERMT2D,
+ ND_INS_VPERMT2PD,
+ ND_INS_VPERMT2PS,
+ ND_INS_VPERMT2Q,
+ ND_INS_VPERMT2W,
+ ND_INS_VPERMW,
+ ND_INS_VPEXPANDB,
+ ND_INS_VPEXPANDD,
+ ND_INS_VPEXPANDQ,
+ ND_INS_VPEXPANDW,
+ ND_INS_VPEXTRB,
+ ND_INS_VPEXTRD,
+ ND_INS_VPEXTRQ,
+ ND_INS_VPEXTRW,
+ ND_INS_VPGATHERDD,
+ ND_INS_VPGATHERDQ,
+ ND_INS_VPGATHERQD,
+ ND_INS_VPGATHERQQ,
+ ND_INS_VPHADDBD,
+ ND_INS_VPHADDBQ,
+ ND_INS_VPHADDBW,
+ ND_INS_VPHADDD,
+ ND_INS_VPHADDDQ,
+ ND_INS_VPHADDSW,
+ ND_INS_VPHADDUBD,
+ ND_INS_VPHADDUBQ,
+ ND_INS_VPHADDUBW,
+ ND_INS_VPHADDUDQ,
+ ND_INS_VPHADDUWD,
+ ND_INS_VPHADDUWQ,
+ ND_INS_VPHADDW,
+ ND_INS_VPHADDWD,
+ ND_INS_VPHADDWQ,
+ ND_INS_VPHMINPOSUW,
+ ND_INS_VPHSUBBW,
+ ND_INS_VPHSUBD,
+ ND_INS_VPHSUBDQ,
+ ND_INS_VPHSUBSW,
+ ND_INS_VPHSUBW,
+ ND_INS_VPHSUBWD,
+ ND_INS_VPINSRB,
+ ND_INS_VPINSRD,
+ ND_INS_VPINSRQ,
+ ND_INS_VPINSRW,
+ ND_INS_VPLZCNTD,
+ ND_INS_VPLZCNTQ,
+ ND_INS_VPMACSDD,
+ ND_INS_VPMACSDQH,
+ ND_INS_VPMACSDQL,
+ ND_INS_VPMACSSDD,
+ ND_INS_VPMACSSDQH,
+ ND_INS_VPMACSSDQL,
+ ND_INS_VPMACSSWD,
+ ND_INS_VPMACSSWW,
+ ND_INS_VPMACSWD,
+ ND_INS_VPMACSWW,
+ ND_INS_VPMADCSSWD,
+ ND_INS_VPMADCSWD,
+ ND_INS_VPMADD52HUQ,
+ ND_INS_VPMADD52LUQ,
+ ND_INS_VPMADDUBSW,
+ ND_INS_VPMADDWD,
+ ND_INS_VPMASKMOVD,
+ ND_INS_VPMASKMOVQ,
+ ND_INS_VPMAXSB,
+ ND_INS_VPMAXSD,
+ ND_INS_VPMAXSQ,
+ ND_INS_VPMAXSW,
+ ND_INS_VPMAXUB,
+ ND_INS_VPMAXUD,
+ ND_INS_VPMAXUQ,
+ ND_INS_VPMAXUW,
+ ND_INS_VPMINSB,
+ ND_INS_VPMINSD,
+ ND_INS_VPMINSQ,
+ ND_INS_VPMINSW,
+ ND_INS_VPMINUB,
+ ND_INS_VPMINUD,
+ ND_INS_VPMINUQ,
+ ND_INS_VPMINUW,
+ ND_INS_VPMOVB2M,
+ ND_INS_VPMOVD2M,
+ ND_INS_VPMOVDB,
+ ND_INS_VPMOVDW,
+ ND_INS_VPMOVM2B,
+ ND_INS_VPMOVM2D,
+ ND_INS_VPMOVM2Q,
+ ND_INS_VPMOVM2W,
+ ND_INS_VPMOVMSKB,
+ ND_INS_VPMOVQ2M,
+ ND_INS_VPMOVQB,
+ ND_INS_VPMOVQD,
+ ND_INS_VPMOVQW,
+ ND_INS_VPMOVSDB,
+ ND_INS_VPMOVSDW,
+ ND_INS_VPMOVSQB,
+ ND_INS_VPMOVSQD,
+ ND_INS_VPMOVSQW,
+ ND_INS_VPMOVSWB,
+ ND_INS_VPMOVSXBD,
+ ND_INS_VPMOVSXBQ,
+ ND_INS_VPMOVSXBW,
+ ND_INS_VPMOVSXDQ,
+ ND_INS_VPMOVSXWD,
+ ND_INS_VPMOVSXWQ,
+ ND_INS_VPMOVUSDB,
+ ND_INS_VPMOVUSDW,
+ ND_INS_VPMOVUSQB,
+ ND_INS_VPMOVUSQD,
+ ND_INS_VPMOVUSQW,
+ ND_INS_VPMOVUSWB,
+ ND_INS_VPMOVW2M,
+ ND_INS_VPMOVWB,
+ ND_INS_VPMOVZXBD,
+ ND_INS_VPMOVZXBQ,
+ ND_INS_VPMOVZXBW,
+ ND_INS_VPMOVZXDQ,
+ ND_INS_VPMOVZXWD,
+ ND_INS_VPMOVZXWQ,
+ ND_INS_VPMULDQ,
+ ND_INS_VPMULHRSW,
+ ND_INS_VPMULHUW,
+ ND_INS_VPMULHW,
+ ND_INS_VPMULLD,
+ ND_INS_VPMULLQ,
+ ND_INS_VPMULLW,
+ ND_INS_VPMULTISHIFTQB,
+ ND_INS_VPMULUDQ,
+ ND_INS_VPOPCNTB,
+ ND_INS_VPOPCNTD,
+ ND_INS_VPOPCNTQ,
+ ND_INS_VPOPCNTW,
+ ND_INS_VPOR,
+ ND_INS_VPORD,
+ ND_INS_VPORQ,
+ ND_INS_VPPERM,
+ ND_INS_VPROLD,
+ ND_INS_VPROLQ,
+ ND_INS_VPROLVD,
+ ND_INS_VPROLVQ,
+ ND_INS_VPRORD,
+ ND_INS_VPRORQ,
+ ND_INS_VPRORVD,
+ ND_INS_VPRORVQ,
+ ND_INS_VPROTB,
+ ND_INS_VPROTD,
+ ND_INS_VPROTQ,
+ ND_INS_VPROTW,
+ ND_INS_VPSADBW,
+ ND_INS_VPSCATTERDD,
+ ND_INS_VPSCATTERDQ,
+ ND_INS_VPSCATTERQD,
+ ND_INS_VPSCATTERQQ,
+ ND_INS_VPSHAB,
+ ND_INS_VPSHAD,
+ ND_INS_VPSHAQ,
+ ND_INS_VPSHAW,
+ ND_INS_VPSHLB,
+ ND_INS_VPSHLD,
+ ND_INS_VPSHLDD,
+ ND_INS_VPSHLDQ,
+ ND_INS_VPSHLDVD,
+ ND_INS_VPSHLDVQ,
+ ND_INS_VPSHLDVW,
+ ND_INS_VPSHLDW,
+ ND_INS_VPSHLQ,
+ ND_INS_VPSHLW,
+ ND_INS_VPSHRDD,
+ ND_INS_VPSHRDQ,
+ ND_INS_VPSHRDVD,
+ ND_INS_VPSHRDVQ,
+ ND_INS_VPSHRDVW,
+ ND_INS_VPSHRDW,
+ ND_INS_VPSHUFB,
+ ND_INS_VPSHUFBITQMB,
+ ND_INS_VPSHUFD,
+ ND_INS_VPSHUFHW,
+ ND_INS_VPSHUFLW,
+ ND_INS_VPSIGNB,
+ ND_INS_VPSIGND,
+ ND_INS_VPSIGNW,
+ ND_INS_VPSLLD,
+ ND_INS_VPSLLDQ,
+ ND_INS_VPSLLQ,
+ ND_INS_VPSLLVD,
+ ND_INS_VPSLLVQ,
+ ND_INS_VPSLLVW,
+ ND_INS_VPSLLW,
+ ND_INS_VPSRAD,
+ ND_INS_VPSRAQ,
+ ND_INS_VPSRAVD,
+ ND_INS_VPSRAVQ,
+ ND_INS_VPSRAVW,
+ ND_INS_VPSRAW,
+ ND_INS_VPSRLD,
+ ND_INS_VPSRLDQ,
+ ND_INS_VPSRLQ,
+ ND_INS_VPSRLVD,
+ ND_INS_VPSRLVQ,
+ ND_INS_VPSRLVW,
+ ND_INS_VPSRLW,
+ ND_INS_VPSUBB,
+ ND_INS_VPSUBD,
+ ND_INS_VPSUBQ,
+ ND_INS_VPSUBSB,
+ ND_INS_VPSUBSW,
+ ND_INS_VPSUBUSB,
+ ND_INS_VPSUBUSW,
+ ND_INS_VPSUBW,
+ ND_INS_VPTERNLOGD,
+ ND_INS_VPTERNLOGQ,
+ ND_INS_VPTEST,
+ ND_INS_VPTESTMB,
+ ND_INS_VPTESTMD,
+ ND_INS_VPTESTMQ,
+ ND_INS_VPTESTMW,
+ ND_INS_VPTESTNMB,
+ ND_INS_VPTESTNMD,
+ ND_INS_VPTESTNMQ,
+ ND_INS_VPTESTNMW,
+ ND_INS_VPUNPCKHBW,
+ ND_INS_VPUNPCKHDQ,
+ ND_INS_VPUNPCKHQDQ,
+ ND_INS_VPUNPCKHWD,
+ ND_INS_VPUNPCKLBW,
+ ND_INS_VPUNPCKLDQ,
+ ND_INS_VPUNPCKLQDQ,
+ ND_INS_VPUNPCKLWD,
+ ND_INS_VPXOR,
+ ND_INS_VPXORD,
+ ND_INS_VPXORQ,
+ ND_INS_VRANGEPD,
+ ND_INS_VRANGEPS,
+ ND_INS_VRANGESD,
+ ND_INS_VRANGESS,
+ ND_INS_VRCP14PD,
+ ND_INS_VRCP14PS,
+ ND_INS_VRCP14SD,
+ ND_INS_VRCP14SS,
+ ND_INS_VRCP28PD,
+ ND_INS_VRCP28PS,
+ ND_INS_VRCP28SD,
+ ND_INS_VRCP28SS,
+ ND_INS_VRCPPBF16,
+ ND_INS_VRCPPH,
+ ND_INS_VRCPPS,
+ ND_INS_VRCPSH,
+ ND_INS_VRCPSS,
+ ND_INS_VREDUCENEPBF16,
+ ND_INS_VREDUCEPD,
+ ND_INS_VREDUCEPH,
+ ND_INS_VREDUCEPS,
+ ND_INS_VREDUCESD,
+ ND_INS_VREDUCESH,
+ ND_INS_VREDUCESS,
+ ND_INS_VRNDSCALENEPBF16,
+ ND_INS_VRNDSCALEPD,
+ ND_INS_VRNDSCALEPH,
+ ND_INS_VRNDSCALEPS,
+ ND_INS_VRNDSCALESD,
+ ND_INS_VRNDSCALESH,
+ ND_INS_VRNDSCALESS,
+ ND_INS_VROUNDPD,
+ ND_INS_VROUNDPS,
+ ND_INS_VROUNDSD,
+ ND_INS_VROUNDSS,
+ ND_INS_VRSQRT14PD,
+ ND_INS_VRSQRT14PS,
+ ND_INS_VRSQRT14SD,
+ ND_INS_VRSQRT14SS,
+ ND_INS_VRSQRT28PD,
+ ND_INS_VRSQRT28PS,
+ ND_INS_VRSQRT28SD,
+ ND_INS_VRSQRT28SS,
+ ND_INS_VRSQRTPBF16,
+ ND_INS_VRSQRTPH,
+ ND_INS_VRSQRTPS,
+ ND_INS_VRSQRTSH,
+ ND_INS_VRSQRTSS,
+ ND_INS_VSCALEFPBF16,
+ ND_INS_VSCALEFPD,
+ ND_INS_VSCALEFPH,
+ ND_INS_VSCALEFPS,
+ ND_INS_VSCALEFSD,
+ ND_INS_VSCALEFSH,
+ ND_INS_VSCALEFSS,
+ ND_INS_VSCATTERDPD,
+ ND_INS_VSCATTERDPS,
+ ND_INS_VSCATTERPF0DPD,
+ ND_INS_VSCATTERPF0DPS,
+ ND_INS_VSCATTERPF0QPD,
+ ND_INS_VSCATTERPF0QPS,
+ ND_INS_VSCATTERPF1DPD,
+ ND_INS_VSCATTERPF1DPS,
+ ND_INS_VSCATTERPF1QPD,
+ ND_INS_VSCATTERPF1QPS,
+ ND_INS_VSCATTERQPD,
+ ND_INS_VSCATTERQPS,
+ ND_INS_VSHA512MSG1,
+ ND_INS_VSHA512MSG2,
+ ND_INS_VSHA512RNDS2,
+ ND_INS_VSHUFF32X4,
+ ND_INS_VSHUFF64X2,
+ ND_INS_VSHUFI32X4,
+ ND_INS_VSHUFI64X2,
+ ND_INS_VSHUFPD,
+ ND_INS_VSHUFPS,
+ ND_INS_VSM3MSG1,
+ ND_INS_VSM3MSG2,
+ ND_INS_VSM3RNDS2,
+ ND_INS_VSM4KEY4,
+ ND_INS_VSM4RNDS4,
+ ND_INS_VSQRTNEPBF16,
+ ND_INS_VSQRTPD,
+ ND_INS_VSQRTPH,
+ ND_INS_VSQRTPS,
+ ND_INS_VSQRTSD,
+ ND_INS_VSQRTSH,
+ ND_INS_VSQRTSS,
+ ND_INS_VSTMXCSR,
+ ND_INS_VSUBNEPBF16,
+ ND_INS_VSUBPD,
+ ND_INS_VSUBPH,
+ ND_INS_VSUBPS,
+ ND_INS_VSUBSD,
+ ND_INS_VSUBSH,
+ ND_INS_VSUBSS,
+ ND_INS_VTESTPD,
+ ND_INS_VTESTPS,
+ ND_INS_VUCOMISD,
+ ND_INS_VUCOMISH,
+ ND_INS_VUCOMISS,
+ ND_INS_VUCOMXSD,
+ ND_INS_VUCOMXSH,
+ ND_INS_VUCOMXSS,
+ ND_INS_VUNPCKHPD,
+ ND_INS_VUNPCKHPS,
+ ND_INS_VUNPCKLPD,
+ ND_INS_VUNPCKLPS,
+ ND_INS_VXORPD,
+ ND_INS_VXORPS,
+ ND_INS_VZEROALL,
+ ND_INS_VZEROUPPER,
+ ND_INS_WAIT,
+ ND_INS_WBINVD,
+ ND_INS_WBNOINVD,
+ ND_INS_WRFSBASE,
+ ND_INS_WRGSBASE,
+ ND_INS_WRMSR,
+ ND_INS_WRMSRLIST,
+ ND_INS_WRMSRNS,
+ ND_INS_WRPKRU,
+ ND_INS_WRSS,
+ ND_INS_WRUSS,
+ ND_INS_XABORT,
+ ND_INS_XADD,
+ ND_INS_XBEGIN,
+ ND_INS_XCHG,
+ ND_INS_XEND,
+ ND_INS_XGETBV,
+ ND_INS_XLATB,
+ ND_INS_XOR,
+ ND_INS_XORPD,
+ ND_INS_XORPS,
+ ND_INS_XRESLDTRK,
+ ND_INS_XRSTOR,
+ ND_INS_XRSTORS,
+ ND_INS_XSAVE,
+ ND_INS_XSAVEC,
+ ND_INS_XSAVEOPT,
+ ND_INS_XSAVES,
+ ND_INS_XSETBV,
+ ND_INS_XSUSLDTRK,
+ ND_INS_XTEST,
+
+} ND_INS_CLASS;
+
+
+typedef enum _ND_INS_SET
+{
+ ND_SET_INVALID = 0,
+ ND_SET_3DNOW,
+ ND_SET_ADX,
+ ND_SET_AES,
+ ND_SET_AMD,
+ ND_SET_AMXAVX512,
+ ND_SET_AMXBF16,
+ ND_SET_AMXCOMPLEX,
+ ND_SET_AMXFP16,
+ ND_SET_AMXFP8,
+ ND_SET_AMXINT8,
+ ND_SET_AMXMOVRS,
+ ND_SET_AMXTF32,
+ ND_SET_AMXTILE,
+ ND_SET_AMXTRANSPOSE,
+ ND_SET_APX_F,
+ ND_SET_AVX,
+ ND_SET_AVX102,
+ ND_SET_AVX2,
+ ND_SET_AVX2GATHER,
+ ND_SET_AVX5124FMAPS,
+ ND_SET_AVX5124VNNIW,
+ ND_SET_AVX512BF16,
+ ND_SET_AVX512BITALG,
+ ND_SET_AVX512BW,
+ ND_SET_AVX512CD,
+ ND_SET_AVX512DQ,
+ ND_SET_AVX512ER,
+ ND_SET_AVX512F,
+ ND_SET_AVX512FP16,
+ ND_SET_AVX512IFMA,
+ ND_SET_AVX512PF,
+ ND_SET_AVX512VBMI,
+ ND_SET_AVX512VBMI2,
+ ND_SET_AVX512VNNI,
+ ND_SET_AVX512VP2INTERSECT,
+ ND_SET_AVX512VPOPCNTDQ,
+ ND_SET_AVXIFMA,
+ ND_SET_AVXNECONVERT,
+ ND_SET_AVXVNNI,
+ ND_SET_AVXVNNIINT16,
+ ND_SET_AVXVNNIINT8,
+ ND_SET_BMI1,
+ ND_SET_BMI2,
+ ND_SET_CET_IBT,
+ ND_SET_CET_SS,
+ ND_SET_CLDEMOTE,
+ ND_SET_CLFSH,
+ ND_SET_CLFSHOPT,
+ ND_SET_CLWB,
+ ND_SET_CLZERO,
+ ND_SET_CMPCCXADD,
+ ND_SET_CMPXCHG16B,
+ ND_SET_ENQCMD,
+ ND_SET_F16C,
+ ND_SET_FMA,
+ ND_SET_FMA4,
+ ND_SET_FRED,
+ ND_SET_FXSAVE,
+ ND_SET_GFNI,
+ ND_SET_HRESET,
+ ND_SET_I186,
+ ND_SET_I286PROT,
+ ND_SET_I286REAL,
+ ND_SET_I386,
+ ND_SET_I486,
+ ND_SET_I486REAL,
+ ND_SET_I64,
+ ND_SET_I86,
+ ND_SET_INVLPGB,
+ ND_SET_INVPCID,
+ ND_SET_KL,
+ ND_SET_LKGS,
+ ND_SET_LONGMODE,
+ ND_SET_LWP,
+ ND_SET_LZCNT,
+ ND_SET_MCOMMIT,
+ ND_SET_MMX,
+ ND_SET_MOVBE,
+ ND_SET_MOVDIR64B,
+ ND_SET_MOVDIRI,
+ ND_SET_MOVRS,
+ ND_SET_MPX,
+ ND_SET_MSRLIST,
+ ND_SET_MSR_IMM,
+ ND_SET_MWAITT,
+ ND_SET_PAUSE,
+ ND_SET_PCLMULQDQ,
+ ND_SET_PCONFIG,
+ ND_SET_PENTIUMREAL,
+ ND_SET_PKU,
+ ND_SET_POPCNT,
+ ND_SET_PPRO,
+ ND_SET_PREFETCHITI,
+ ND_SET_PREFETCH_NOP,
+ ND_SET_PTWRITE,
+ ND_SET_RAOINT,
+ ND_SET_RDPID,
+ ND_SET_RDPMC,
+ ND_SET_RDPRU,
+ ND_SET_RDRAND,
+ ND_SET_RDSEED,
+ ND_SET_RDTSCP,
+ ND_SET_RDWRFSGS,
+ ND_SET_SERIALIZE,
+ ND_SET_SGX,
+ ND_SET_SHA,
+ ND_SET_SHA512,
+ ND_SET_SM3,
+ ND_SET_SM4,
+ ND_SET_SMAP,
+ ND_SET_SMX,
+ ND_SET_SNP,
+ ND_SET_SSE,
+ ND_SET_SSE2,
+ ND_SET_SSE3,
+ ND_SET_SSE4,
+ ND_SET_SSE42,
+ ND_SET_SSE4A,
+ ND_SET_SSSE3,
+ ND_SET_SVM,
+ ND_SET_TBM,
+ ND_SET_TDX,
+ ND_SET_TSE,
+ ND_SET_TSX,
+ ND_SET_TSXLDTRK,
+ ND_SET_UD,
+ ND_SET_UINTR,
+ ND_SET_UNKNOWN,
+ ND_SET_USER_MSR,
+ ND_SET_VAES,
+ ND_SET_VPCLMULQDQ,
+ ND_SET_VTX,
+ ND_SET_WAITPKG,
+ ND_SET_WBNOINVD,
+ ND_SET_WRMSRNS,
+ ND_SET_X87,
+ ND_SET_XOP,
+ ND_SET_XSAVE,
+ ND_SET_XSAVEC,
+ ND_SET_XSAVES,
+
+} ND_INS_SET;
+
+
+typedef enum _ND_INS_TYPE
+{
+ ND_CAT_INVALID = 0,
+ ND_CAT_3DNOW,
+ ND_CAT_AES,
+ ND_CAT_AESKL,
+ ND_CAT_AMX,
+ ND_CAT_APX,
+ ND_CAT_ARITH,
+ ND_CAT_AVX,
+ ND_CAT_AVX10BF16,
+ ND_CAT_AVX10CMPSFP,
+ ND_CAT_AVX10CONVERT,
+ ND_CAT_AVX10INT,
+ ND_CAT_AVX10MINMAX,
+ ND_CAT_AVX10PARTCOPY,
+ ND_CAT_AVX10SCONVERT,
+ ND_CAT_AVX2,
+ ND_CAT_AVX2GATHER,
+ ND_CAT_AVX512,
+ ND_CAT_AVX512BF16,
+ ND_CAT_AVX512FP16,
+ ND_CAT_AVX512VBMI,
+ ND_CAT_AVX512VP2INTERSECT,
+ ND_CAT_AVXIFMA,
+ ND_CAT_AVXNECONVERT,
+ ND_CAT_AVXVNNI,
+ ND_CAT_AVXVNNIINT16,
+ ND_CAT_AVXVNNIINT8,
+ ND_CAT_BITBYTE,
+ ND_CAT_BLEND,
+ ND_CAT_BMI1,
+ ND_CAT_BMI2,
+ ND_CAT_BROADCAST,
+ ND_CAT_CALL,
+ ND_CAT_CET,
+ ND_CAT_CLDEMOTE,
+ ND_CAT_CMOV,
+ ND_CAT_CMPCCXADD,
+ ND_CAT_COMPRESS,
+ ND_CAT_COND_BR,
+ ND_CAT_CONFLICT,
+ ND_CAT_CONVERT,
+ ND_CAT_DATAXFER,
+ ND_CAT_DECIMAL,
+ ND_CAT_ENQCMD,
+ ND_CAT_EXPAND,
+ ND_CAT_FLAGOP,
+ ND_CAT_FMA4,
+ ND_CAT_GATHER,
+ ND_CAT_GFNI,
+ ND_CAT_HRESET,
+ ND_CAT_I386,
+ ND_CAT_IFMA,
+ ND_CAT_INTERRUPT,
+ ND_CAT_IO,
+ ND_CAT_IOSTRINGOP,
+ ND_CAT_KL,
+ ND_CAT_KMASK,
+ ND_CAT_KNL,
+ ND_CAT_LKGS,
+ ND_CAT_LOGIC,
+ ND_CAT_LOGICAL,
+ ND_CAT_LOGICAL_FP,
+ ND_CAT_LWP,
+ ND_CAT_LZCNT,
+ ND_CAT_MISC,
+ ND_CAT_MMX,
+ ND_CAT_MOVDIR64B,
+ ND_CAT_MOVDIRI,
+ ND_CAT_MPX,
+ ND_CAT_NOP,
+ ND_CAT_PCLMULQDQ,
+ ND_CAT_PCONFIG,
+ ND_CAT_POP,
+ ND_CAT_PREFETCH,
+ ND_CAT_PTWRITE,
+ ND_CAT_PUSH,
+ ND_CAT_RAOINT,
+ ND_CAT_RDPID,
+ ND_CAT_RDRAND,
+ ND_CAT_RDSEED,
+ ND_CAT_RDWRFSGS,
+ ND_CAT_RET,
+ ND_CAT_ROTATE,
+ ND_CAT_SCATTER,
+ ND_CAT_SEGOP,
+ ND_CAT_SEMAPHORE,
+ ND_CAT_SGX,
+ ND_CAT_SHA,
+ ND_CAT_SHA512,
+ ND_CAT_SHIFT,
+ ND_CAT_SM3,
+ ND_CAT_SM4,
+ ND_CAT_SMAP,
+ ND_CAT_SSE,
+ ND_CAT_SSE2,
+ ND_CAT_STRINGOP,
+ ND_CAT_STTNI,
+ ND_CAT_SYSCALL,
+ ND_CAT_SYSRET,
+ ND_CAT_SYSTEM,
+ ND_CAT_TDX,
+ ND_CAT_UD,
+ ND_CAT_UINTR,
+ ND_CAT_UNCOND_BR,
+ ND_CAT_UNKNOWN,
+ ND_CAT_USER_MSR,
+ ND_CAT_VAES,
+ ND_CAT_VFMA,
+ ND_CAT_VFMAPS,
+ ND_CAT_VNNI,
+ ND_CAT_VNNIW,
+ ND_CAT_VPCLMULQDQ,
+ ND_CAT_VPOPCNT,
+ ND_CAT_VTX,
+ ND_CAT_WAITPKG,
+ ND_CAT_WBNOINVD,
+ ND_CAT_WIDENOP,
+ ND_CAT_WIDE_KL,
+ ND_CAT_X87_ALU,
+ ND_CAT_XOP,
+ ND_CAT_XSAVE,
+
+} ND_INS_CATEGORY;
+
+
+
+#endif
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bdx86_core.h b/compiler-rt/lib/interception/bddisasm/inc/bdx86_core.h
new file mode 100644
index 00000000000000..80ff235a008564
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bdx86_core.h
@@ -0,0 +1,1720 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDX86_CORE_H
+#define BDX86_CORE_H
+
+#include "bddisasm_types.h"
+#include "bddisasm_status.h"
+#include "bddisasm_version.h"
+
+#include "bdx86_registers.h"
+#include "bdx86_constants.h"
+#include "bdx86_cpuidflags.h"
+
+
+#ifdef _MSC_VER
+#pragma warning(push)
+#pragma warning(disable: 4214) // Bitfield in type other than int.
+#pragma warning(disable: 4201) // Nonstandard extension used: nameless struct/union.
+#endif
+
+//
+// Preferred vendor; the disassembler will try to be smart and disassemble as much as it can, but if there are
+// encoding conflicts, than an alternate vendor can be selected. Note that this has effect only on conflicting
+// encodings.
+//
+#define ND_VEND_ANY 0 // Generic decode, include any vendor.
+#define ND_VEND_INTEL 1 // Prefer Intel.
+#define ND_VEND_AMD 2 // Prefer AMD.
+#define ND_VEND_MAX 2
+
+//
+// These control what instructions should be decoded if they map onto the wide NOP space (0F 1A and 0F 1B). Those are
+// tricky, because they might be NOP if the feature is disabled, but might be something else (even #UD) if the feature
+// is enabled. Ergo, we allow the user to select whether said feature is on or off, so that he controls whether he
+// sees the NOPs or the MPX/CET/CLDEMOTE/etc. instructions instead.
+//
+#define ND_FEAT_NONE 0x00 // No feature/mode enabled.
+#define ND_FEAT_MPX 0x01 // MPX support enabled.
+#define ND_FEAT_CET 0x02 // CET support enabled.
+#define ND_FEAT_CLDEMOTE 0x04 // CLDEMOTE support enabled.
+#define ND_FEAT_PITI 0x08 // PREFETCHITI support enabled.
+#define ND_FEAT_APX 0x10 // APX support enabled.
+#define ND_FEAT_ALL 0xFF // Decode as if all features are enabled. This is default.
+
+//
+// Code type
+//
+#define ND_CODE_16 0 // 16 bit decode mode.
+#define ND_CODE_32 1 // 32 bit decode mode.
+#define ND_CODE_64 2 // 64 bit decode mode.
+
+//
+// Data type
+//
+#define ND_DATA_16 0 // 16 bit data size.
+#define ND_DATA_32 1 // 32 bit data size.
+#define ND_DATA_64 2 // 64 bit data size.
+
+//
+// Stack type
+//
+#define ND_STACK_16 0 // 16 bit stack size.
+#define ND_STACK_32 1 // 32 bit stack size.
+#define ND_STACK_64 2 // 64 bit stack size.
+
+//
+// Addressing mode
+//
+#define ND_ADDR_16 0 // 16 bit addressing.
+#define ND_ADDR_32 1 // 32 bit addressing.
+#define ND_ADDR_64 2 // 64 bit addressing.
+
+//
+// Operand mode/size
+//
+#define ND_OPSZ_16 0 // 16 bit operand size.
+#define ND_OPSZ_32 1 // 32 bit operand size.
+#define ND_OPSZ_64 2 // 64 bit operand size.
+
+//
+// Vector mode/size
+//
+#define ND_VECM_128 0 // 128 bit vector size.
+#define ND_VECM_256 1 // 256 bit vector size.
+#define ND_VECM_512 2 // 512 bit vector size.
+
+//
+// Encoding mode
+//
+#define ND_ENCM_LEGACY 0 // Legacy encoded instruction.
+#define ND_ENCM_XOP 1 // XOP encoded instruction.
+#define ND_ENCM_VEX 2 // VEX (bot 2B or 3B) encoded instruction.
+#define ND_ENCM_EVEX 3 // EVEX encoded instruction.
+
+//
+// VEX mode
+//
+#define ND_VEXM_2B 0 // 2B VEX prefix (0xC5).
+#define ND_VEXM_3B 1 // 3B VEX prefix (0xC4).
+
+//
+// EVEX mode
+//
+#define ND_EVEXM_EVEX 0 // Regular EVEX.
+#define ND_EVEXM_VEX 1 // EVEX extension for VEX instructions.
+#define ND_EVEXM_LEGACY 2 // EVEX extension for legacy instructions.
+#define ND_EVEXM_COND 3 // EVEX extension for conditional instructions.
+
+
+//
+// Size definitions
+//
+#define ND_SIZE_8BIT 1 // 1 byte.
+#define ND_SIZE_16BIT 2 // 1 word or 2 bytes.
+#define ND_SIZE_32BIT 4 // 1 double word or 4 bytes.
+#define ND_SIZE_48BIT 6 // 1 fword or 6 bytes.
+#define ND_SIZE_64BIT 8 // 1 qword or 8 bytes.
+#define ND_SIZE_80BIT 10 // 1 fpu word or 10 bytes.
+#define ND_SIZE_112BIT 14 // FPU environment, 14 bytes.
+#define ND_SIZE_128BIT 16 // 1 xmm word or 16 bytes.
+#define ND_SIZE_224BIT 28 // FPU environment, 28 bytes.
+#define ND_SIZE_256BIT 32 // 1 ymm word or 32 bytes.
+#define ND_SIZE_384BIT 48 // 48 bytes, used for Key Locker handles.
+#define ND_SIZE_512BIT 64 // 1 zmm word or 64 bytes. Used also for Key Locker handles.
+#define ND_SIZE_752BIT 94 // FPU state, 94 bytes.
+#define ND_SIZE_864BIT 108 // FPU state, 108 bytes.
+#define ND_SIZE_4096BIT 512 // Extended state, 512 bytes.
+#define ND_SIZE_1KB 1024 // Tile register, 1KB.
+#define ND_SIZE_CACHE_LINE 0xFFFFFFFE // The size of a cache line.
+#define ND_SIZE_UNKNOWN 0xFFFFFFFF // Unknown/invalid size.
+
+
+typedef ND_UINT32 ND_OPERAND_SIZE;
+
+typedef ND_UINT32 ND_REG_SIZE;
+
+
+//
+// Prefix definitions
+//
+#define ND_PREFIX_G0_LOCK 0xF0 // LOCK prefix.
+#define ND_PREFIX_G1_REPNE_REPNZ 0xF2 // REPNE/REPNZ prefix.
+#define ND_PREFIX_G1_XACQUIRE 0xF2 // XACQUIRE prefix.
+#define ND_PREFIX_G1_REPE_REPZ 0xF3 // REPE/REPZ prefix.
+#define ND_PREFIX_G1_XRELEASE 0xF3 // XRELEASE prefix.
+#define ND_PREFIX_G1_BND 0xF2 // BND prefix.
+#define ND_PREFIX_G2_SEG_CS 0x2E // CS segment override.
+#define ND_PREFIX_G2_SEG_SS 0x36 // SS segment override.
+#define ND_PREFIX_G2_SEG_DS 0x3E // DS segment override.
+#define ND_PREFIX_G2_SEG_ES 0x26 // ES segment override.
+#define ND_PREFIX_G2_SEG_FS 0x64 // FS segment override.
+#define ND_PREFIX_G2_SEG_GS 0x65 // GS segment override.
+#define ND_PREFIX_G2_BR_NOT_TAKEN 0x2E // Branch not taken hint.
+#define ND_PREFIX_G2_BR_TAKEN 0x3E // Branch taken hint.
+#define ND_PREFIX_G2_BR_ALT 0x64 // Alternating branch hint.
+#define ND_PREFIX_G2_NO_TRACK 0x3E // Do not track prefix.
+#define ND_PREFIX_G3_OPERAND_SIZE 0x66 // Operand size override.
+#define ND_PREFIX_G4_ADDR_SIZE 0x67 // Address size override.
+
+#define ND_PREFIX_REX_MIN 0x40 // First REX prefix.
+#define ND_PREFIX_REX_MAX 0x4F // Last REX prefix.
+#define ND_PREFIX_VEX_2B 0xC5 // 2B VEX prefix.
+#define ND_PREFIX_VEX_3B 0xC4 // 3B VEX prefix.
+#define ND_PREFIX_XOP 0x8F // XOP prefix.
+#define ND_PREFIX_EVEX 0x62 // EVEX prefix.
+#define ND_PREFIX_REX2 0xD5 // REX2 prefix.
+
+
+//
+// Instruction attributes
+//
+#define ND_FLAG_MODRM 0x0000000000000001 // The instruction has modrm.
+#define ND_FLAG_F64 0x0000000000000002 // The operand is forced to 64 bit. Size changing prefix 0x66 is ignored.
+#define ND_FLAG_D64 0x0000000000000004 // The default operand size is 64 bit. Size changing prefix 0x66
+ // changes the size to 16 bit. No 32 bit version can be encoded.
+#define ND_FLAG_O64 0x0000000000000008 // The instruction is available only in 64 bit mode.
+#define ND_FLAG_I64 0x0000000000000010 // The instruction is invalid in 64 bit mode.
+#define ND_FLAG_COND 0x0000000000000020 // The instruction has a condition code encoded in low 4 bits of the opcode.
+#define ND_FLAG_RESERVED0 0x0000000000000040 // Reserved.
+#define ND_FLAG_VSIB 0x0000000000000080 // The instruction uses VSIB addressing mode.
+#define ND_FLAG_MIB 0x0000000000000100 // The instruction used MIB addressing mode.
+#define ND_FLAG_LIG 0x0000000000000200 // L flag inside XOP/VEX/EVEX is ignored.
+#define ND_FLAG_WIG 0x0000000000000400 // W flag inside XOP/VEX/EVEX is ignored.
+#define ND_FLAG_3DNOW 0x0000000000000800 // The instruction is 3DNow!. The opcode is the last byte.
+#define ND_FLAG_LOCKSP 0x0000000000001000 // MOV to/from CR in 16/32 bit, on AMD, extend the access to
+ // high 8 CRs via the LOCK prefix.
+#define ND_FLAG_LOCK_SPECIAL ND_FLAG_LOCKSP
+#define ND_FLAG_MMASK 0x0000000000002000 // The instruction #UDs if K0 (no mask) is used.
+#define ND_FLAG_NOMZ 0x0000000000004000 // The instruction #UDs if zeroing is used on memory.
+#define ND_FLAG_NOL0 0x0000000000008000 // The instruction #UDs if vector length 128 is used.
+#define ND_FLAG_NOA16 0x0000000000010000 // The instruction #UDs if 16-bit addressing is used.
+#define ND_FLAG_MFR 0x0000000000020000 // The Mod inside Mod R/M is forced to reg. No SIB/disp present.
+#define ND_FLAG_VECTOR 0x0000000000040000 // The instruction is a SIMD instruction that operates on vector regs.
+#define ND_FLAG_S66 0x0000000000080000 // Special flag for mandatory 0x66 prefix that actually changes
+ // the default op length.
+#define ND_FLAG_BITBASE 0x0000000000100000 // The instruction uses bitbase addressing mode.
+#define ND_FLAG_AG 0x0000000000200000 // The instruction is an address generator; no actual memory access.
+#define ND_FLAG_SHS 0x0000000000400000 // The instruction does a shadow stack access.
+#define ND_FLAG_CETT 0x0000000000800000 // The instruction is CET tracked.
+#define ND_FLAG_SERIAL 0x0000000001000000 // The instruction is serializing.
+#define ND_FLAG_NORIPREL 0x0000000002000000 // The instruction #UDs if RIP-relative addressing is used.
+#define ND_FLAG_NO_RIP_REL ND_FLAG_NORIPREL
+#define ND_FLAG_NO66 0x0000000004000000 // The instruction #UDs if 0x66 prefix is present.
+#define ND_FLAG_SIBMEM 0x0000000008000000 // The instruction uses sibmem addressing (Intel AMX instructions).
+#define ND_FLAG_I67 0x0000000010000000 // Ignore the 0x67 prefix in 64 bit mode (Intel MPX instructions).
+#define ND_FLAG_IER 0x0000000020000000 // Ignore EVEX embedded rounding.
+#define ND_FLAG_IWO64 0x0000000040000000 // Ignore VEX/EVEX.W outside 64 bit mode. It behaves as if it's 0.
+#define ND_FLAG_NOREX2 0x0000000080000000 // The instruction #UDs if REX2 is present.
+#define ND_FLAG_NOREP 0x0000000100000000 // The instruction #UDs if REP prefixes are present.
+#define ND_FLAG_NO67 0x0000000200000000 // The instruction #UDs if 0x67 prefix is present.
+#define ND_FLAG_NOV 0x0000000400000000 // The instruction #UDs if XOP/VEX/EVEX.vvvv is not logical 0.
+#define ND_FLAG_NOVP 0x0000000800000000 // The instruction #UDs if EVEX.v' is not logical 0.
+#define ND_FLAG_SCALABLE 0x0000001000000000 // EVEX.pp can be 0 or 1, simulating the presence of 0x66 prefix.
+
+
+
+//
+// Accepted prefixes map
+//
+#define ND_PREF_REP 0x0001 // The instruction supports REP prefix.
+#define ND_PREF_REPC 0x0002 // The instruction supports REPZ/REPNZ prefixes.
+#define ND_PREF_LOCK 0x0004 // The instruction supports LOCK prefix.
+#define ND_PREF_HLE 0x0008 // The instruction supports XACQUIRE/XRELEASE prefixes.
+#define ND_PREF_XACQUIRE 0x0010 // The instruction supports only XACQUIRE.
+#define ND_PREF_XRELEASE 0x0020 // The instruction supports only XRELEASE.
+#define ND_PREF_BND 0x0040 // The instruction supports BND prefix.
+#define ND_PREF_BH 0x0080 // The instruction supports branch hints.
+#define ND_PREF_BHINT ND_PREF_BH
+#define ND_PREF_HLEWOL 0x0100 // HLE prefix is accepted without LOCK.
+#define ND_PREF_HLE_WO_LOCK ND_PREF_HLEWOL
+#define ND_PREF_DNT 0x0200 // The instruction supports the DNT (Do Not Track) CET prefix.
+
+
+//
+// Accepted decorators map. These are stored per-instruction. There are also per-operand indicators for
+// each decorator, where applicable.
+//
+#define ND_DECO_ER 0x01 // Embedded rounding is accepted.
+#define ND_DECO_SAE 0x02 // Suppress all Exceptions is accepted.
+#define ND_DECO_ZERO 0x04 // Zeroing is accepted.
+#define ND_DECO_MASK 0x08 // Masking is accepted.
+#define ND_DECO_BROADCAST 0x10 // Memory broadcast is accepted.
+#define ND_DECO_ND 0x20 // New-data destination specifier accepted.
+#define ND_DECO_NF 0x40 // No-Flags specifier accepted.
+#define ND_DECO_ZU 0x80 // Zero-Upper semantic accepted.
+
+
+//
+// Operand access flags.
+//
+#define ND_ACCESS_NONE 0x00 // The operand is not accessed.
+#define ND_ACCESS_READ 0x01 // The operand is read.
+#define ND_ACCESS_WRITE 0x02 // The operand is written.
+#define ND_ACCESS_COND_READ 0x04 // The operand is read only if some conditions are met.
+#define ND_ACCESS_COND_WRITE 0x08 // The operand is written only if some conditions are met (ie: CMOVcc).
+#define ND_ACCESS_ANY_READ (ND_ACCESS_READ | ND_ACCESS_COND_READ) // Any read mask.
+#define ND_ACCESS_ANY_WRITE (ND_ACCESS_WRITE | ND_ACCESS_COND_WRITE) // Any write mask.
+#define ND_ACCESS_PREFETCH 0x10 // The operand is prefetched.
+
+
+//
+// Condition definitions.
+//
+#define ND_COND_OVERFLOW 0x0 // OF
+#define ND_COND_CARRY 0x2 // CF
+#define ND_COND_BELOW 0x2 // CF
+#define ND_COND_NOT_ABOVE_OR_EQUAL 0x2 // CF
+#define ND_COND_ZERO 0x4 // ZF
+#define ND_COND_EQUAL 0x4 // ZF
+#define ND_COND_BELOW_OR_EQUAL 0x6 // CF | ZF
+#define ND_COND_NOT_ABOVE 0x6 // CF | ZF
+#define ND_COND_SIGN 0x8 // SF
+#define ND_COND_PARITY 0xA // PF
+#define ND_COND_LESS 0xC // SF ^ OF
+#define ND_COND_LESS_OR_EQUAL 0xE // (SF ^ OF) | ZF
+#define ND_COND_NOT(p) ((p) | 0x1) // Negates the predicate.
+
+
+//
+// Valid CPU modes.
+//
+// Group 1: ring
+#define ND_MOD_R0 0x00000001 // Instruction valid in ring 0.
+#define ND_MOD_R1 0x00000002 // Instruction valid in ring 1.
+#define ND_MOD_R2 0x00000004 // Instruction valid in ring 2.
+#define ND_MOD_R3 0x00000008 // Instruction valid in ring 3.
+
+// Group 2: operating mode.
+#define ND_MOD_REAL 0x00000010 // Instruction valid in real mode.
+#define ND_MOD_V8086 0x00000020 // Instruction valid in virtual 8086 mode.
+#define ND_MOD_PROT 0x00000040 // Instruction valid in protected mode.
+#define ND_MOD_COMPAT 0x00000080 // Instruction valid in compatibility mode.
+#define ND_MOD_LONG 0x00000100 // Instruction valid in long mode.
+
+// Group 3: misc modes.
+#define ND_MOD_SMM 0x00001000 // Instruction valid in System-Management Mode.
+#define ND_MOD_SMM_OFF 0x00002000 // Instruction valid outside SMM.
+#define ND_MOD_SGX 0x00004000 // Instruction valid in SGX enclaves.
+#define ND_MOD_SGX_OFF 0x00008000 // Instruction valid outside SGX enclaves.
+#define ND_MOD_TSX 0x00010000 // Instruction valid in TSX transactional regions.
+#define ND_MOD_TSX_OFF 0x00020000 // Instruction valid outside TSX.
+
+
+// Group 4: VMX
+#define ND_MOD_VMXR 0x00040000 // Instruction valid in VMX Root mode.
+#define ND_MOD_VMXN 0x00080000 // Instruction valid in VMX non-root mode.
+#define ND_MOD_VMXR_SEAM 0x00100000 // Instruction valid in VMX root Secure Arbitration Mode.
+#define ND_MOD_VMXN_SEAM 0x00200000 // Instruction valid in VMX non-root Secure Arbitration Mode.
+#define ND_MOD_VMX_OFF 0x00400000 // Instruction valid outside VMX operation.
+
+#define ND_MOD_RING_MASK 0x0000000F // Valid ring mask.
+#define ND_MOD_MODE_MASK 0x000001F0 // Valid mode mask.
+#define ND_MOD_OTHER_MASK 0x0003F000 // Misc mask.
+#define ND_MOD_VMX_MASK 0x007C0000 // VMX mask.
+
+// For instructions valid in any operating mode.
+#define ND_MOD_ANY 0xFFFFFFFF // Instruction valid in any mode.
+
+
+//
+// Misc constants
+//
+#define ND_MAX_INSTRUCTION_LENGTH 15 // 15 bytes is the maximum instruction length supported by the x86 arch.
+#define ND_MAX_MNEMONIC_LENGTH 32 // Should do for now.
+#define ND_MIN_BUF_SIZE 128 // Textual disassembly minimal buffer size.
+#define ND_MAX_OPERAND 10 // No more than 10 operands/instruction, but I'm generous.
+#define ND_MAX_REGISTER_SIZE 64 // Maximum register size - 64 bytes.
+#define ND_MAX_GPR_REGS 32 // Max number of GPRs.
+#define ND_MAX_SEG_REGS 8 // Max number of segment registers.
+#define ND_MAX_FPU_REGS 8 // Max number of FPU registers.
+#define ND_MAX_MMX_REGS 8 // Max number of MMX registers.
+#define ND_MAX_SSE_REGS 32 // Max number of SSE registers.
+#define ND_MAX_CR_REGS 32 // Max number of control registers.
+#define ND_MAX_DR_REGS 32 // Max number of debug registers.
+#define ND_MAX_TR_REGS 16 // Max number of test registers.
+#define ND_MAX_MSK_REGS 8 // Max number of mask registers.
+#define ND_MAX_BND_REGS 4 // Max number of bound registers.
+#define ND_MAX_SYS_REGS 8 // Max number of system registers.
+#define ND_MAX_X87_REGS 8 // Max number of x87 state/control registers registers.
+#define ND_MAX_TILE_REGS 8 // Max number of tile registers.
+
+
+
+//
+// Misc macros.
+//
+
+// NOTE: Macros that accept a size (in bytes) are undefined if the size is not in the interval [1, 8].
+
+// Sign extend 8 bit to 64 bit.
+#define ND_SIGN_EX_8(x) ND_SIGN_EX(1, x)
+// Sign extend 16 bit to 64 bit.
+#define ND_SIGN_EX_16(x) ND_SIGN_EX(2, x)
+// Sign extend 32 bit to 64 bit.
+#define ND_SIGN_EX_32(x) ND_SIGN_EX(4, x)
+// Sign extend sz bytes to 64 bits.
+#define ND_SIGN_EX(sz, x) ((((ND_UINT64)(x)) & ND_SIZE_TO_MASK(sz)) | (~ND_SIZE_TO_MASK(sz) * ND_GET_SIGN(sz, x)))
+
+// Trim 64 bits to sz bytes.
+#define ND_TRIM(sz, x) ((ND_UINT64)(x) & ND_SIZE_TO_MASK(sz))
+// Returns most significant bit, given size in bytes sz.
+#define ND_MSB(sz, x) ((((x)) >> (((sz) * 8) - 1)) & 1)
+// Returns least significant bit.
+#define ND_LSB(sz, x) ((x) & 1)
+// Convert a size in bytes to a bitmask.
+#define ND_SIZE_TO_MASK(sz) (0xFFFFFFFFFFFFFFFFull >> ((8 - (sz)) * 8))
+// Get bit at position bit from x.
+#define ND_GET_BIT(bit, x) (((x) >> (bit)) & 1)
+// Return the sign of sz bytes long value x.
+#define ND_GET_SIGN(sz, x) ND_MSB(sz, x)
+// Sets the sign of the sz bytes long value x.
+#define ND_SET_SIGN(sz, x) ND_SIGN_EX(sz, x)
+
+
+#define ND_FETCH_64(b) ((ND_UINT64)(((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b))) | \
+ (((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b) + 4) << 32))))
+#define ND_FETCH_32(b) ((ND_UINT32)(((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b))) | \
+ (((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b) + 2) << 16))))
+#define ND_FETCH_16(b) ((ND_UINT16)(((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b))) | \
+ (((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b) + 1) << 8))))
+#define ND_FETCH_8(b) (*((const ND_UINT8 *)(b)))
+
+
+
+//
+// Helper macros which simply test the presence of various ND_FLAG_* in the instruction attributes.
+//
+#define ND_IS_3DNOW(ix) (!!((ix)->Attributes & ND_FLAG_3DNOW))
+#define ND_HAS_CONDITION(ix) (!!((ix)->Attributes & ND_FLAG_COND))
+#define ND_HAS_MODRM(ix) (!!((ix)->Attributes & ND_FLAG_MODRM))
+#define ND_HAS_VSIB(ix) (!!((ix)->Attributes & ND_FLAG_VSIB))
+#define ND_HAS_MIB(ix) (!!((ix)->Attributes & ND_FLAG_MIB))
+#define ND_HAS_VECTOR(ix) (!!((ix)->Attributes & ND_FLAG_VECTOR))
+#define ND_HAS_BITBASE(ix) (!!((ix)->Attributes & ND_FLAG_BITBASE))
+#define ND_HAS_AG(ix) (!!((ix)->Attributes & ND_FLAG_AG))
+#define ND_HAS_SIBMEM(ix) (!!((ix)->Attributes & ND_FLAG_SIBMEM))
+#define ND_HAS_SHS(ix) (!!((ix)->Attributes & ND_FLAG_SHS))
+#define ND_HAS_CETT(ix) (!!((ix)->Attributes & ND_FLAG_CETT))
+
+//
+// Supported prefixes macros.
+//
+#define ND_REP_SUPPORT(ix) (!!((ix)->ValidPrefixes.Rep))
+#define ND_REPC_SUPPORT(ix) (!!((ix)->ValidPrefixes.RepCond))
+#define ND_LOCK_SUPPORT(ix) (!!((ix)->ValidPrefixes.Lock))
+#define ND_HLE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Hle))
+#define ND_XACQUIRE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xacquire))
+#define ND_XRELEASE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xrelease))
+#define ND_BND_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bnd))
+#define ND_BHINT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bhint))
+#define ND_DNT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Dnt))
+
+//
+// Decorators map macros.
+//
+#define ND_DECORATOR_SUPPORT(ix) ((ix)->ValidDecorators.Raw != 0)
+#define ND_MASK_SUPPORT(ix) (!!((ix)->ValidDecorators.Mask))
+#define ND_ZERO_SUPPORT(ix) (!!((ix)->ValidDecorators.Zero))
+#define ND_ER_SUPPORT(ix) (!!((ix)->ValidDecorators.Er))
+#define ND_SAE_SUPPORT(ix) (!!((ix)->ValidDecorators.Sae))
+#define ND_BROADCAST_SUPPORT(ix) (!!((ix)->ValidDecorators.Broadcast))
+
+// Generates a unique ID per register type, size and reg. The layout is the following:
+// - bits [63, 60] (4 bits) - the operand type (ND_OP_REG)
+// - bits [59, 52] (8 bits) - the register type
+// - bits [51, 36] (16 bits) - the register size, in bytes
+// - bits [35, 30] (6 bits) - the number of registers accessed starting with this reg (for block addressing)
+// - bits [29, 9] (21 bits) - reserved
+// - bit 8 - High8 indicator: indicates whether the reg is AH/CH/DH/BH
+// - bits [7, 0] (8 bits) - the register ID
+#define ND_OP_REG_ID(op) (((ND_UINT64)((op)->Type & 0xF) << 60) | \
+ ((ND_UINT64)((op)->Info.Register.Type & 0xFF) << 52) | \
+ ((ND_UINT64)((op)->Info.Register.Size & 0xFFFF) << 36) | \
+ ((ND_UINT64)((op)->Info.Register.Count & 0x3F) << 30) | \
+ ((ND_UINT64)((op)->Info.Register.IsHigh8 & 0x1) << 8) | \
+ ((ND_UINT64)((op)->Info.Register.Reg)))
+
+// Example: ND_IS_OP_REG(op, ND_REG_GPR, 4, REG_ESP)
+// Example: ND_IS_OP_REG(op, ND_REG_CR, 8, REG_CR3)
+// Example: ND_IS_OP_REG(op, ND_REG_RIP, 8, 0)
+
+// Checks if the indicated operand op is a register of type t, with size s and index r.
+#define ND_IS_OP_REG(op, t, s, r) (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) | \
+ ((ND_UINT64)((t) & 0xFF) << 52) | \
+ ((ND_UINT64)((s) & 0xFFFF) << 36) | \
+ ((ND_UINT64)(1) << 30) | \
+ ((ND_UINT64)(r))))
+
+// Checks if the indicated operand op is a register of type t, with size s and index r.
+#define ND_IS_OP_REG_EX(op, t, s, r, b, h) (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) | \
+ ((ND_UINT64)((t) & 0xFF) << 52) | \
+ ((ND_UINT64)((s) & 0xFFFF) << 36) | \
+ ((ND_UINT64)((b) & 0x3F) << 30) | \
+ ((ND_UINT64)((h) & 0x1) << 8) | \
+ ((ND_UINT64)(r))))
+
+// Checjs if the indicated operand is the stack.
+#define ND_IS_OP_STACK(op) ((op)->Type == ND_OP_MEM && (op)->Info.Memory.IsStack)
+
+
+//
+// Operand types.
+//
+typedef enum _ND_OPERAND_TYPE
+{
+ ND_OP_NOT_PRESENT, // Indicates the absence of any operand.
+ ND_OP_REG, // The operand is a register.
+ ND_OP_MEM, // The operand is located in memory.
+ ND_OP_IMM, // The operand is an immediate.
+ ND_OP_OFFS, // The operand is a relative offset.
+ ND_OP_ADDR, // The operand is an absolute far address, in the form seg:offset.
+ ND_OP_ADDR_FAR = ND_OP_ADDR,
+ ND_OP_ADDR_NEAR, // The operand is an absolute near address, in the form target64.
+ ND_OP_CONST, // The operand is an implicit constant.
+ ND_OP_BANK, // An entire bank/set of registers are being accessed. Used in PUSHA/POPA/XSAVE/LOADALL.
+ ND_OP_DFV, // The operand is dfv (default flags value).
+} ND_OPERAND_TYPE;
+
+
+//
+// Register types.
+//
+typedef enum _ND_REG_TYPE
+{
+ ND_REG_NOT_PRESENT,
+ ND_REG_GPR, // The register is a 8/16/32/64 bit general purpose register.
+ ND_REG_SEG, // The register is a segment register.
+ ND_REG_FPU, // The register is a 80-bit FPU register.
+ ND_REG_MMX, // The register is a 64-bit MMX register.
+ ND_REG_SSE, // The register is a 128/256/512 bit SSE vector register.
+ ND_REG_CR, // The register is a control register.
+ ND_REG_DR, // The register is a debug register.
+ ND_REG_TR, // The register is a test register.
+ ND_REG_BND, // The register is a bound register.
+ ND_REG_MSK, // The register is a mask register.
+ ND_REG_TILE, // The register is a tile register.
+ ND_REG_MSR, // The register is a model specific register.
+ ND_REG_XCR, // The register is a extended control register.
+ ND_REG_SYS, // The register is a system register.
+ ND_REG_X87, // The register is a x87 status/control register.
+ ND_REG_MXCSR, // The register is the MXCSR register.
+ ND_REG_PKRU, // The register is the PKRU register.
+ ND_REG_SSP, // The register is the SSP (Shadow Stack Pointer) register.
+ ND_REG_FLG, // The register is the FLAGS register.
+ ND_REG_RIP, // The register is the instruction pointer register.
+ ND_REG_UIF, // The register is the User Interrupt Flag.
+} ND_REG_TYPE;
+
+
+//
+// Operand encoding types.
+//
+typedef enum _ND_OPERAND_ENCODING
+{
+ ND_OPE_NP, // No encoding present.
+ ND_OPE_R, // Operand encoded in modrm.reg.
+ ND_OPE_M, // Operand encoded in modrm.rm.
+ ND_OPE_V, // Operand encoded in Xop/Vex/Evex/Mvex.(v')vvvv
+ ND_OPE_D, // Operand is encoded inside subsequent instruction bytes.
+ ND_OPE_O, // Operand is encoded in low 3 bit of the opcode.
+ ND_OPE_I, // Operand is an immediate.
+ ND_OPE_C, // Operand is CL.
+ ND_OPE_1, // Operand is 1.
+ ND_OPE_L, // Operand is reg encoded in immediate.
+ ND_OPE_A, // Operand is encoded in Evex.aaa.
+ ND_OPE_E, // Operand is a MSR or XCR encoded in ECX register.
+ ND_OPE_S, // Operand is implicit/suppressed. Not encoded anywhere.
+} ND_OPERAND_ENCODING;
+
+
+//
+// Instruction tuple type; used to determine compressed displacement size for disp8 EVEX instructions. Note that
+// most of the EVEX encoded instructions use the compressed displacement addressing scheme.
+//
+typedef enum _ND_TUPLE
+{
+ ND_TUPLE_None,
+ ND_TUPLE_FV, // Full Vector
+ ND_TUPLE_HV, // Half Vector
+ ND_TUPLE_QV, // Quarter Vector
+ ND_TUPLE_T1S8, // Tuple1 scalar, size 8 bit
+ ND_TUPLE_T1S16, // Tuple1 scalar, size 16 bit
+ ND_TUPLE_T1S, // Tuple1 scalar, size 32/64 bit
+ ND_TUPLE_T1F, // Tuple1 float, size 32/64 bit
+ ND_TUPLE_T2, // Tuple2, 64/128 bit
+ ND_TUPLE_T4, // Tuple4, 128/256 bit
+ ND_TUPLE_T8, // Tuple8, 256 bit
+ ND_TUPLE_FVM, // Full Vector Memory
+ ND_TUPLE_HVM, // Half Vector Memory
+ ND_TUPLE_QVM, // Quarter Vector Memory
+ ND_TUPLE_OVM, // Oct Vector Memory
+ ND_TUPLE_M128, // M128, 128 bit
+ ND_TUPLE_DUP, // DUP (VMOVDDUP)
+ ND_TUPLE_T1_4X, // 4 x 32 bit Memory Elements are referenced
+} ND_TUPLE;
+
+
+//
+// EVEX rounding control.
+//
+typedef enum _ND_ROUNDING
+{
+ ND_RND_RNE, // Round to nearest equal.
+ ND_RND_RD, // Round down.
+ ND_RND_RU, // Round up.
+ ND_RND_RZ, // round to zero.
+} ND_ROUNDING;
+
+//
+// Exception types.
+//
+typedef enum _ND_EX_TYPE
+{
+ ND_EXT_None,
+
+ // SSE/AVX exceptions.
+ ND_EXT_1,
+ ND_EXT_2,
+ ND_EXT_3,
+ ND_EXT_4,
+ ND_EXT_5,
+ ND_EXT_6,
+ ND_EXT_7,
+ ND_EXT_8,
+ ND_EXT_9,
+ ND_EXT_10,
+ ND_EXT_11,
+ ND_EXT_12,
+ ND_EXT_13,
+ ND_EXT_14,
+
+ // Opmask exceptios.
+ ND_EXT_K20,
+ ND_EXT_K21,
+
+ // EVEX exceptions.
+ ND_EXT_E1,
+ ND_EXT_E1NF,
+ ND_EXT_E2,
+ ND_EXT_E3,
+ ND_EXT_E3NF,
+ ND_EXT_E4,
+ ND_EXT_E4S, // E4, with an additional case: if (dst == src1) or (dst == src2)
+ ND_EXT_E4nb,
+ ND_EXT_E4NF,
+ ND_EXT_E4NFnb,
+ ND_EXT_E5,
+ ND_EXT_E5NF,
+ ND_EXT_E6,
+ ND_EXT_E6NF,
+ ND_EXT_E7NM,
+ ND_EXT_E9,
+ ND_EXT_E9NF,
+ ND_EXT_E10,
+ ND_EXT_E10S, // E10, with an additional case: if (dst == src1) or (dst == src2)
+ ND_EXT_E10NF,
+ ND_EXT_E11,
+ ND_EXT_E12,
+ ND_EXT_E12NP,
+
+ // AMX exceptions.
+ ND_EXT_AMX_E1,
+ ND_EXT_AMX_E2,
+ ND_EXT_AMX_E3,
+ ND_EXT_AMX_E4,
+ ND_EXT_AMX_E5,
+ ND_EXT_AMX_E6,
+ ND_EXT_AMX_E7,
+ ND_EXT_AMX_E8,
+ ND_EXT_AMX_E9,
+ ND_EXT_AMX_E10,
+ ND_EXT_AMX_E11,
+
+ // AMX-EVEX exceptions.
+ ND_EXT_AMX_EVEX_E1,
+ ND_EXT_AMX_EVEX_E2,
+ ND_EXT_AMX_EVEX_E3,
+ ND_EXT_AMX_EVEX_E4,
+ ND_EXT_AMX_EVEX_E5,
+ ND_EXT_AMX_EVEX_E6,
+ ND_EXT_AMX_EVEX_E7,
+ ND_EXT_AMX_EVEX_E8,
+
+ // APX-EVEX exceptions.
+ ND_EXT_APX_EVEX_BMI,
+ ND_EXT_APX_EVEX_CCMP,
+ ND_EXT_APX_EVEX_WRSS,
+ ND_EXT_APX_EVEX_WRUSS,
+ ND_EXT_APX_EVEX_CFCMOV,
+ ND_EXT_APX_EVEX_CMPCCXADD,
+ ND_EXT_APX_EVEX_ENQCMD,
+ ND_EXT_APX_EVEX_INT,
+ ND_EXT_APX_EVEX_INVEPT,
+ ND_EXT_APX_EVEX_INVPCID,
+ ND_EXT_APX_EVEX_INVVPID,
+ ND_EXT_APX_EVEX_KEYLOCKER,
+ ND_EXT_APX_EVEX_KMOV,
+ ND_EXT_APX_EVEX_PP2,
+ ND_EXT_APX_EVEX_RAOINT,
+ ND_EXT_APX_EVEX_SHA,
+ ND_EXT_APX_EVEX_USER_MSR,
+} ND_EX_TYPE;
+
+
+//
+// Operand access mode.
+//
+typedef union _ND_OPERAND_ACCESS
+{
+ ND_UINT8 Access;
+ struct
+ {
+ ND_UINT8 Read : 1; // The operand is read.
+ ND_UINT8 Write : 1; // The operand is written.
+ ND_UINT8 CondRead : 1; // The operand is read only under some conditions.
+ ND_UINT8 CondWrite : 1; // The operand is written only under some conditions.
+ ND_UINT8 Prefetch : 1; // The operand is prefetched.
+ };
+} ND_OPERAND_ACCESS;
+
+
+//
+// Operand flags.
+//
+typedef union _ND_OPERAND_FLAGS
+{
+ ND_UINT8 Flags;
+ struct
+ {
+ ND_UINT8 IsDefault : 1; // 1 if the operand is default. This also applies to implicit ops.
+ ND_UINT8 SignExtendedOp1 : 1; // 1 if the operand is sign extended to the first operands' size.
+ ND_UINT8 SignExtendedDws : 1; // 1 if the operand is sign extended to the default word size.
+ };
+} ND_OPERAND_FLAGS;
+
+
+//
+// Constant operand.
+//
+typedef struct _ND_OPDESC_CONSTANT
+{
+ ND_UINT64 Const; // Instruction constant, ie ROL reg, 1.
+} ND_OPDESC_CONSTANT;
+
+
+//
+// Immediate operand.
+//
+typedef struct _ND_OPDESC_IMMEDIATE
+{
+ ND_UINT64 Imm; // Immediate. Only Size bytes are valid. The rest are undefined.
+ ND_UINT8 RawSize; // Raw size (how many bytes are encoded in the instruction).
+} ND_OPDESC_IMMEDIATE;
+
+
+//
+// Relative offset operand.
+//
+typedef struct _ND_OPDESC_REL_OFFSET
+{
+ ND_UINT64 Rel; // Relative offset (relative to the current RIP). Sign extended.
+ ND_UINT8 RawSize; // Raw size (how many bytes are encoded in the instruction).
+} ND_OPDESC_RELOFFSET;
+
+
+//
+// Describes a register operand. Count registers are used starting with Reg.
+//
+typedef struct _ND_OPDESC_REGISTER
+{
+ ND_REG_TYPE Type; // The register type. See enum ND_REG_TYPE.
+ ND_REG_SIZE Size; // Indicates the register size. This may not be equal to the Size
+ // field, as a smaller amount of data may be processed from a
+ // register (especially if we have a SSE register or a mask register).
+ // Also note that as of now, 64 bytes is the maximum register size.
+ ND_UINT32 Reg; // The register number/ID.
+ ND_UINT8 Count; // The number of registers accessed, starting with Reg.
+
+ ND_UINT8 IsHigh8:1; // TRUE if this is AH, CH, DH or BH register.
+ ND_UINT8 IsBlock:1; // TRUE if this is a block register addressing.
+ ND_UINT8 IsZeroUpper:1; // TRUE if the upper register is zeroed.
+} ND_OPDESC_REGISTER;
+
+
+//
+// Describes a seg:offset absolute effective address.
+//
+typedef struct _ND_OPDESC_ADDRESS
+{
+ // Size is the size of the address. Usually 4 (16 bit mode) or 6 (32 bit mode) or 10 (64 bit).
+ ND_UINT64 Offset; // Offset inside the segment.
+ ND_UINT16 BaseSeg; // Base segment selector of the address.
+} ND_OPDESC_ADDRESS, ND_OPDESC_ADDRESS_FAR;
+
+
+//
+// Describes a 64-bit absolute effective address.
+//
+typedef struct _ND_OPDESC_ADDRESS_NEAR
+{
+ ND_UINT64 Target; // Absolue 64-bit target address.
+} ND_OPDESC_ADDRESS_NEAR;
+
+
+//
+// Shadow stack access types.
+//
+typedef enum _ND_SHSTK_ACCESS
+{
+ ND_SHSTK_NONE = 0,
+ ND_SHSTK_EXPLICIT, // Explicit memory operand accessed as shadow stack.
+ ND_SHSTK_SSP_LD_ST, // Shadow Stack Pointer (SSP) used as base for addressing using conventional load/store.
+ ND_SHSTK_SSP_PUSH_POP, // Shadow Stack Pointer (SSP) used as base for addressing using push/pop.
+ ND_SHSTK_PL0_SSP, // Privilege 0 SSP (IA32_PL0_SSP) used (SETSSBSY).
+} ND_SHSTK_ACCESS;
+
+
+//
+// Describes a memory operand.
+//
+typedef struct _ND_OPDESC_MEMORY
+{
+ ND_BOOL HasSeg:1; // TRUE if segment is present & used.
+ ND_BOOL HasBase:1; // TRUE if base register is present.
+ ND_BOOL HasIndex:1; // TRUE if index & scale are present.
+ ND_BOOL HasDisp:1; // TRUE if displacement is present.
+ ND_BOOL HasCompDisp:1; // TRUE if compressed disp8 is used (EVEX instructions).
+ ND_BOOL HasBroadcast:1; // TRUE if the memory operand is a broadcast operand.
+
+ ND_BOOL IsRipRel:1; // TRUE if this is a rip-relative addressing. Base, Index, Scale are
+ // all ignored.
+ ND_BOOL IsStack:1; // TRUE if this is a stack op. Note that explicit stack accesses are not
+ // included (eg: mov eax, [rsp] will NOT set IsStack).
+ ND_BOOL IsString:1; // TRUE for [RSI] and [RDI] operands inside string operations.
+ ND_BOOL IsShadowStack:1; // TRUE if this is a shadow stack access. Check out ShStkType for more info.
+ ND_BOOL IsDirect:1; // TRUE if direct addressing (MOV [...], EAX, 0xA3).
+ ND_BOOL IsBitbase:1; // TRUE if this is a bit base. Used for BT* instructions. The bitbase
+ // stored in the second operand must be added to the linear address.
+ ND_BOOL IsAG:1; // TRUE if the memory operand is address generation and no mem access is
+ // made.
+ ND_BOOL IsMib:1; // TRUE if MIB addressing is used (MPX instructions).
+ ND_BOOL IsVsib:1; // TRUE if the index register selects a vector register.
+ ND_BOOL IsSibMem:1; // TRUE if the addressing uses sibmem (AMX instructions).
+
+ ND_UINT8 BaseSize; // Base size, in bytes. Max 8 bytes.
+ ND_UINT8 IndexSize; // Ditto for index size. Max 64 bytes for VSIB.
+ ND_UINT8 DispSize; // Displacement size. Max 4 bytes.
+ ND_UINT8 CompDispSize; // Compressed displacement size - 1, 2, 4, 8, 16, 32, 64.
+
+ ND_UINT8 ShStkType; // Shadow stack access type. Check out ND_SHSTK_ACCESS.
+
+ union
+ {
+ struct
+ {
+ ND_UINT8 IndexSize; // VSIB index size.
+ ND_UINT8 ElemSize; // VSIB element size.
+ ND_UINT8 ElemCount; // Number of elements scattered/gathered/prefetched.
+ } Vsib; // Valid if HasVsib is set.
+
+ struct
+ {
+ ND_UINT8 Count; // Number of times to broadcast the element.
+ ND_UINT8 Size; // Size of one element.
+ } Broadcast; // Valid if HasBroadcast is set.
+ };
+
+ ND_UINT8 Seg:3; // Base segment used to address the memory. 0 = es, 1 = cs, etc.
+ ND_UINT8 Base:5; // Base register. Can only be a GPR.
+ ND_UINT8 Index; // Index register. Can be a vector reg (ZMM0-ZMM31).
+ ND_UINT8 Scale:4; // Scale: 1, 2, 4 or 8. Always present if Index is present.
+
+ ND_UINT64 Disp; // Sign extended displacement.
+
+} ND_OPDESC_MEMORY;
+
+
+//
+// Describes a Default Flags Value operand.
+//
+typedef struct _ND_OPDESC_DEFAULT_FLAGS
+{
+ ND_UINT8 CF:1;
+ ND_UINT8 ZF:1;
+ ND_UINT8 SF:1;
+ ND_UINT8 OF:1;
+} ND_OPDESC_DEFAULT_FLAGS;
+
+
+//
+// Describes a decorator that applies to an operand.
+//
+typedef struct _ND_OPERAND_DECORATOR
+{
+ ND_BOOL HasMask:1; // TRUE if mask is present, 0 otherwise.
+ ND_BOOL HasZero:1; // TRUE if zeroing will be made, 0 if merging will be made.
+ ND_BOOL HasBroadcast:1; // TRUE if broadcasting is being made. Valid only for memory operands.
+
+ // Mask register specifier.
+ ND_UINT8 Msk:3; // Mask register used. Only k0-k7 can be encoded.
+
+} ND_OPERAND_DECORATOR;
+
+
+//
+// Extended operand information.
+//
+typedef struct _ND_OPERAND
+{
+ ND_UINT8 Type:4; // Operand type. One of ND_OPERAND_TYPE enumerations.
+ ND_UINT8 Encoding:4; // Where is the operand encoded. One of ND_OPERAND_ENCODING enumerations.
+ ND_OPERAND_ACCESS Access; // Access mode (read, write, read-write, etc.)
+ ND_OPERAND_FLAGS Flags; // Misc operand flags.
+ ND_OPERAND_DECORATOR Decorator; // Decorator information.
+ ND_OPERAND_SIZE Size; // Operand size in bytes. This should be used when operating with
+ // the operand. It includes sign-extension or zero-extensions.
+ // Note that the Size field indicates the actual amount of data
+ // used for processing. If the operand type is a register, it MAY NOT
+ // indicate the register size. Use the Info.Register.Size
+ // field to get the actual register size.
+
+ // Depending in the Type field, one of these subfields contains information about the operand.
+ // Althoug Immediate, RelativeOffset & Address are all immediate payloads, they are kept separate, due
+ // the slightly different semantic:
+ // 1. Immediate is a plain immediate quantity
+ // 2. RelativeOffset is an immediate added to the instruction pointer
+ // 3. Address is an mmediate formed formed of a segment:offset pair
+ union
+ {
+ ND_OPDESC_REGISTER Register; // Register, if operand type if ND_OP_REG.
+ ND_OPDESC_MEMORY Memory; // Memory, if operand type is ND_OP_MEM.
+ ND_OPDESC_IMMEDIATE Immediate; // Immediate, if operand type is ND_OP_IMM.
+ ND_OPDESC_RELOFFSET RelativeOffset; // Relative offset, if operand type is ND_OP_OFFS.
+ ND_OPDESC_ADDRESS_FAR Address; // Address, seg:offset form, if operand type is ND_OP_ADDR.
+ ND_OPDESC_ADDRESS_NEAR AddressNear; // Address, target64 form, if operand type is ND_OP_ADDR_NEAR.
+ ND_OPDESC_CONSTANT Constant; // Constant, if operand type is ND_OP_CONST.
+ ND_OPDESC_DEFAULT_FLAGS DefaultFlags; // Default flags value, if operand type is ND_OP_DFV.
+ } Info;
+
+} ND_OPERAND, *PND_OPERAND;
+
+
+//
+// REX prefix.
+//
+typedef union _ND_REX
+{
+ ND_UINT8 Rex;
+ struct
+ {
+ ND_UINT8 b : 1; // b (rm or low opcode) extension field.
+ ND_UINT8 x : 1; // x (index) extension field.
+ ND_UINT8 r : 1; // r (reg) extension field.
+ ND_UINT8 w : 1; // w (size) extension field. Promotes to 64 bit.
+ };
+} ND_REX;
+
+//
+// REX2 prefix.
+//
+typedef union _ND_REX2
+{
+ ND_UINT8 Rex2[2];
+ struct
+ {
+ ND_UINT8 op; // 0xD5
+
+ ND_UINT8 b3 : 1; // B3 (rm or low opcode) extension field.
+ ND_UINT8 x3 : 1; // X3 (index) extension field.
+ ND_UINT8 r3 : 1; // R3 (reg) extension field.
+ ND_UINT8 w : 1; // W (size) extension field. Promotes to 64 bit.
+ ND_UINT8 b4 : 1; // B4 (rm or low opcode) extension field.
+ ND_UINT8 x4 : 1; // X4 (index) extension field.
+ ND_UINT8 r4 : 1; // R4 (reg) extension field.
+ ND_UINT8 m0 : 1; // M0 map ID.
+ };
+} ND_REX2;
+
+//
+// Mod R/M byte.
+//
+typedef union _ND_MODRM
+{
+ ND_UINT8 ModRm;
+ struct
+ {
+ ND_UINT8 rm : 3; // rm field.
+ ND_UINT8 reg : 3; // reg field.
+ ND_UINT8 mod : 2; // mod field. Indicates memory access (0, 1 or 2), or register access (3).
+ };
+} ND_MODRM;
+
+//
+// SIB byte.
+//
+typedef union _ND_SIB
+{
+ ND_UINT8 Sib;
+ struct
+ {
+ ND_UINT8 base : 3; // Base register.
+ ND_UINT8 index : 3; // Index register.
+ ND_UINT8 scale : 2; // Scale.
+ };
+} ND_SIB;
+
+//
+// 2-bytes VEX prefix.
+//
+typedef union _ND_VEX2
+{
+ ND_UINT8 Vex[2];
+ struct
+ {
+ ND_UINT8 op; // 0xC5
+
+ ND_UINT8 p : 2; // p0, p1
+ ND_UINT8 l : 1; // L
+ ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3
+ ND_UINT8 r : 1; // ~R
+ };
+} ND_VEX2;
+
+//
+// 3-bytes VEX prefix.
+//
+typedef union _ND_VEX3
+{
+ ND_UINT8 Vex[3];
+ struct
+ {
+ ND_UINT8 op; // 0xC4
+
+ ND_UINT8 m : 5; // m0, m1, m2, m3, m4
+ ND_UINT8 b : 1; // ~B
+ ND_UINT8 x : 1; // ~X
+ ND_UINT8 r : 1; // ~R
+
+ ND_UINT8 p : 2; // p0, p1
+ ND_UINT8 l : 1; // L
+ ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3
+ ND_UINT8 w : 1; // W
+ };
+} ND_VEX3;
+
+//
+// XOP prefix.
+//
+typedef union _ND_XOP
+{
+ ND_UINT8 Xop[3];
+ struct
+ {
+ ND_UINT8 op; // 0x8F
+
+ ND_UINT8 m : 5; // m0, m1, m2, m3, m4
+ ND_UINT8 b : 1; // ~B
+ ND_UINT8 x : 1; // ~X
+ ND_UINT8 r : 1; // ~R
+
+ ND_UINT8 p : 2; // p0, p1
+ ND_UINT8 l : 1; // L
+ ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3
+ ND_UINT8 w : 1; // W
+ };
+} ND_XOP;
+
+//
+// EVEX prefix.
+//
+typedef union _ND_EVEX
+{
+ ND_UINT8 Evex[4];
+ struct
+ {
+ ND_UINT8 op; // 0x62
+
+ ND_UINT8 m : 3; // m0, m1, m2. Indicates opcode map.
+ ND_UINT8 b4 : 1; // B4 (repurposed from a hard-coded 0 bit).
+ ND_UINT8 rp : 1; // ~R' or ~R4
+ ND_UINT8 b : 1; // ~B or ~B3
+ ND_UINT8 x : 1; // ~X or ~X3
+ ND_UINT8 r : 1; // ~R or ~R3
+
+ ND_UINT8 p : 2; // p0, p1
+ ND_UINT8 u : 1; // ~U (repurposed from a hard-coded 1 bit).
+ ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3
+ ND_UINT8 w : 1; // W
+
+ ND_UINT8 a : 3; // a0, a1, a2
+ ND_UINT8 vp : 1; // ~V'
+ ND_UINT8 bm : 1; // b
+ ND_UINT8 l : 2; // L'L
+ ND_UINT8 z : 1; // z
+ };
+} ND_EVEX;
+
+
+//
+// Describes the CPUID leaf, sub-leaf, register & bit that indicate whether an instruction is supported or not.
+// If Leaf == ND_CFF_NO_LEAF, the instruction is supported on any CPU, and no CPUID flag exists.
+// If SubLeaf == ND_CFF_NO_SUBLEAF, there is no subleaf to check.
+//
+typedef union _ND_CPUID_FLAG
+{
+ ND_UINT64 Flag;
+ struct
+ {
+ ND_UINT32 Leaf; // CPUID leaf. ND_CFF_NO_LEAF if not applicable.
+ ND_UINT32 SubLeaf : 24; // CPUID sub-leaf. ND_CFF_NO_SUBLEAF if not applicable.
+ ND_UINT32 Reg : 3; // The register that contains info regarding the instruction.
+ ND_UINT32 Bit : 5; // Bit inside the register that indicates whether the instruction is present.
+ };
+} ND_CPUID_FLAG;
+
+
+//
+// Each instruction may accept one or more prefixes. This structure indicates which prefixes are valid for the
+// given instruction.
+//
+typedef union _ND_VALID_PREFIXES
+{
+ ND_UINT16 Raw;
+ struct
+ {
+ ND_UINT16 Rep : 1; // The instruction supports REP prefix.
+ ND_UINT16 RepCond : 1; // The instruction supports REPZ/REPNZ prefixes.
+ ND_UINT16 Lock : 1; // The instruction supports LOCK prefix.
+ ND_UINT16 Hle : 1; // The instruction supports XACQUIRE/XRELEASE prefixes.
+ ND_UINT16 Xacquire : 1; // The instruction supports only XACQUIRE.
+ ND_UINT16 Xrelease : 1; // The instruction supports only XRELEASE.
+ ND_UINT16 Bnd : 1; // The instruction supports BND prefix.
+ ND_UINT16 Bhint : 1; // The instruction supports branch hints.
+ ND_UINT16 HleNoLock : 1; // HLE prefix is accepted without LOCK.
+ ND_UINT16 Dnt : 1; // The instruction supports the DNT (Do Not Track) CET prefix.
+ };
+} ND_VALID_PREFIXES, *PND_VALID_PREFIXES;
+
+
+//
+// Each instruction may accept several decorators. This instruction indicates which decorators are valid for the
+// given instruction.
+//
+typedef union _ND_VALID_DECORATORS
+{
+ ND_UINT8 Raw;
+ struct
+ {
+ ND_UINT8 Er : 1; // The instruction supports embedded rounding mode.
+ ND_UINT8 Sae : 1; // The instruction supports suppress all exceptions mode.
+ ND_UINT8 Zero : 1; // The instruction supports zeroing.
+ ND_UINT8 Mask : 1; // The instruction supports mask registers.
+ ND_UINT8 Broadcast : 1; // The instruction supports broadcast.
+ ND_UINT8 Nd : 1; // The instruction supports new data destination.
+ ND_UINT8 Nf : 1; // The instruction supports no-flags update.
+ ND_UINT8 Zu : 1; // The instruction supports zero-upper semantic.
+ };
+} ND_VALID_DECORATORS, *PND_VALID_DECORATORS;
+
+
+//
+// Each instruction is valid or invalid in any certain mode. This indicates which modes the instruction is valid in.
+// If the bit is set, the isntruction is valid in that given mode.
+//
+typedef union _ND_VALID_MODES
+{
+ ND_UINT32 Raw;
+ struct
+ {
+ // Group 1: privilege level.
+ ND_UINT32 Ring0 : 1; // The instruction is valid in ring 0.
+ ND_UINT32 Ring1 : 1; // The instruction is valid in ring 1.
+ ND_UINT32 Ring2 : 1; // The instruction is valid in ring 2.
+ ND_UINT32 Ring3 : 1; // The instruction is valid in ring 3.
+
+ // Group 2: operating mode - the CPU can be on only one of these modes at any moment.
+ ND_UINT32 Real : 1; // The instruction is valid in real mode.
+ ND_UINT32 V8086 : 1; // The instruction is valid in Virtual 8086 mode.
+ ND_UINT32 Protected : 1; // The instruction is valid in protected mode (32 bit).
+ ND_UINT32 Compat : 1; // The instruction is valid in compatibility mode (32 bit in 64 bit).
+ ND_UINT32 Long : 1; // The instruction is valid in long mode.
+
+ ND_UINT32 Reserved : 3; // Reserved for padding/future use.
+
+ // Group 3: special modes - these may be active inside other modes (example: TSX in Long mode).
+ ND_UINT32 Smm : 1; // The instruction is valid in System Management Mode.
+ ND_UINT32 SmmOff : 1; // The instruction is valid outside SMM.
+ ND_UINT32 Sgx : 1; // The instruction is valid in SGX mode.
+ ND_UINT32 SgxOff : 1; // The instruction is valid outside SGX.
+ ND_UINT32 Tsx : 1; // The instruction is valid in transactional regions.
+ ND_UINT32 TsxOff : 1; // The instruction is valid outside TSX.
+
+ // Group 4: VMX mode - they engulf all the other modes.
+ ND_UINT32 VmxRoot : 1; // The instruction is valid in VMX root mode.
+ ND_UINT32 VmxNonRoot : 1;// The instruction is valid in VMX non root mode.
+ ND_UINT32 VmxRootSeam : 1; // The instruction is valid in VMX root SEAM.
+ ND_UINT32 VmxNonRootSeam : 1;// The instruction is valid in VMX non-root SEAM.
+ ND_UINT32 VmxOff : 1; // The instruction is valid outside VMX operation.
+
+ };
+} ND_VALID_MODES, *PND_VALID_MODES;
+
+
+//
+// RFLAGS register. This structure reflects the actual position of each flag insdide the RFLAGS register, so it can
+// be used for direct processing.
+//
+typedef union _ND_RFLAGS
+{
+ ND_UINT32 Raw;
+ struct
+ {
+ ND_UINT32 CF : 1; // Carry flag.
+ ND_UINT32 Reserved1 : 1; // Reserved, must be 1.
+ ND_UINT32 PF : 1; // Parity flag.
+ ND_UINT32 Reserved2 : 1; // Reserved.
+ ND_UINT32 AF : 1; // Auxiliary flag.
+ ND_UINT32 Reserved3 : 1; // Reserved.
+ ND_UINT32 ZF : 1; // Zero flag.
+ ND_UINT32 SF : 1; // Sign flag.
+ ND_UINT32 TF : 1; // Trap flag.
+ ND_UINT32 IF : 1; // Interrupt flag.
+ ND_UINT32 DF : 1; // Direction flag.
+ ND_UINT32 OF : 1; // Overflow flag.
+ ND_UINT32 IOPL : 2; // I/O privilege level flag.
+ ND_UINT32 NT : 1; // Nested task flag.
+ ND_UINT32 Reserved4 : 1; // Reserved.
+ ND_UINT32 RF : 1; // Resume flag.
+ ND_UINT32 VM : 1; // Virtual mode flag.
+ ND_UINT32 AC : 1; // Alignment check flag.
+ ND_UINT32 VIF : 1; // Virtual interrupts flag.
+ ND_UINT32 VIP : 1; // Virtual interrupt pending flag.
+ ND_UINT32 ID : 1; // CPUID identification flag.
+ };
+} ND_RFLAGS, *PND_RFLAGS;
+
+
+#define ND_FPU_FLAG_SET_0 0 // The FPU status flag is cleared to 0.
+#define ND_FPU_FLAG_SET_1 1 // The FPU status flag is set to 1.
+#define ND_FPU_FLAG_MODIFIED 2 // The FPU status flag is modified according to a result.
+#define ND_FPU_FLAG_UNDEFINED 3 // The FPU status flag is undefined or unaffected.
+
+//
+// FPU status flags. Each status flag can be one of ND_FPU_FLAG*.
+//
+typedef union _ND_FPU_FLAGS
+{
+ ND_UINT8 Raw;
+ struct
+ {
+ ND_UINT8 C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*.
+ ND_UINT8 C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*.
+ ND_UINT8 C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*.
+ ND_UINT8 C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*.
+ };
+} ND_FPU_FLAGS, *PND_FPU_FLAGS;
+
+
+#define ND_SIMD_EXC_IE 0x01 // Invalid Operation Exception.
+#define ND_SIMD_EXC_DE 0x02 // Denormal Exception.
+#define ND_SIMD_EXC_ZE 0x04 // Divide-by-Zero Exception.
+#define ND_SIMD_EXC_OE 0x08 // Overflow Exception.
+#define ND_SIMD_EXC_UE 0x10 // Underflow Exception.
+#define ND_SIMD_EXC_PE 0x20 // Precision Exception.
+
+//
+// SIMD Floating-Point Exceptions. These values are the same as lower 6 bits in MXCSR. The Raw field
+// is a combination of ND_SIMD_EXC_* values, and is the same as the invidiual bitfields.
+//
+typedef union _ND_SIMD_EXCEPTIONS
+{
+ ND_UINT8 Raw;
+ struct
+ {
+ ND_UINT8 IE : 1; // Invalid Operation Exception.
+ ND_UINT8 DE : 1; // Denormal Exception.
+ ND_UINT8 ZE : 1; // Divide-by-Zero Exception.
+ ND_UINT8 OE : 1; // Overflow Exception.
+ ND_UINT8 UE : 1; // Underflow Exception.
+ ND_UINT8 PE : 1; // Precision Exception.
+ };
+} ND_SIMD_EXCEPTIONS;
+
+
+//
+// Branch information.
+//
+typedef struct _ND_BRANCH_INFO
+{
+ ND_UINT8 IsBranch : 1;
+ ND_UINT8 IsConditional : 1;
+ ND_UINT8 IsIndirect : 1;
+ ND_UINT8 IsFar : 1;
+} ND_BRANCH_INFO;
+
+
+
+//
+// Describes a decoded instruction. All the possible information about the instruction is contained in this structure.
+// You don't have to call any other APIs to gather any more info about it.
+//
+typedef struct _INSTRUX
+{
+ ND_UINT8 DefCode:2; // ND_CODE_*. Indicates disassembly mode.
+ ND_UINT8 DefData:2; // ND_DATA_*. Indicates default data size.
+ ND_UINT8 DefStack:2; // ND_STACK_*. Indicates default stack pointer width.
+ ND_UINT8 AddrMode:2; // ND_ADDR_*. Indicates addressing mode.
+ ND_UINT8 OpMode:2; // ND_OPSZ_*. Indicates operand mode/size.
+ ND_UINT8 EfOpMode:2; // ND_OPSZ_*. Indicates effective operand mode/size.
+ ND_UINT8 VecMode:2; // ND_VECM_*. Indicates vector length. Valid only for vector instructions.
+ ND_UINT8 EfVecMode:2; // ND_VECM_*. Indicates effective vector length. Valid only for vector instructions.
+ ND_UINT8 EncMode:4; // ND_ENCM_*. Indicates encoding mode.
+ ND_UINT8 VexMode:2; // ND_VEX_*. Indicates the VEX mode, if any. Valid only if HasVex set.
+ ND_UINT8 EvexMode:4; // ND_EVEX_*. Indicates EVEX extension, if any. Valid only if HasEvex set.
+ ND_UINT8 VendMode:4; // ND_VEND_*. Indicates vendor mode.
+ ND_UINT8 FeatMode; // ND_FEAT_*. Indicates which features are enabled.
+
+ // Present prefixes. Note that even if a prefix is marked as being present in the encoding, it does not necessary mean
+ // that the prefix is actually used. Check Is*Enabled fields to check if the prefix is enabled & used. In some cases,
+ // prefixes are ignored, even if present.
+ ND_BOOL HasRex:1; // TRUE - REX is present.
+ ND_BOOL HasRex2:1; // TRUE - REX2 is present.
+ ND_BOOL HasVex:1; // TRUE - VEX is present.
+ ND_BOOL HasXop:1; // TRUE - XOP is present.
+ ND_BOOL HasEvex:1; // TRUE - EVEX is present.
+ ND_BOOL HasOpSize:1; // TRUE - 0x66 present.
+ ND_BOOL HasAddrSize:1; // TRUE - 0x67 present.
+ ND_BOOL HasLock:1; // TRUE - 0xF0 present.
+ ND_BOOL HasRepnzXacquireBnd:1; // TRUE - 0xF2 present.
+ ND_BOOL HasRepRepzXrelease:1; // TRUE - 0xF3 present.
+ ND_BOOL HasSeg:1; // TRUE - segment override present.
+
+ // Present encoding components.
+ ND_BOOL HasModRm:1; // TRUE - we have valid MODRM.
+ ND_BOOL HasSib:1; // TRUE - we have valid SIB.
+ ND_BOOL HasDisp:1; // TRUE - the instruction has displacement.
+ ND_BOOL HasAddr:1; // TRUE - the instruction contains a direct far address (ie, CALL far 0x9A)
+ ND_BOOL HasAddrNear:1; // TRUE - the instruction contains a direct near address (ie, CALL far 0x9A)
+ ND_BOOL HasMoffset:1; // TRUE - the instruction contains a moffset (ie, MOV al, [mem], 0xA0)
+ ND_BOOL HasRelOffs:1; // TRUE - the instruction contains a relative offset (ie, Jcc 0x7x).
+ ND_BOOL HasImm1:1; // TRUE - immediate present.
+ ND_BOOL HasImm2:1; // TRUE - second immediate present.
+ ND_BOOL HasSseImm:1; // TRUE - SSE immediate that encodes additional registers is present.
+
+ // Present decorators & EVEX info.
+ ND_BOOL HasCompDisp:1; // TRUE - the instruction uses compressed displacement.
+ ND_BOOL HasBroadcast:1; // TRUE - the instruction uses broadcast addressing.
+ ND_BOOL HasMask:1; // TRUE - the instruction has mask.
+ ND_BOOL HasZero:1; // TRUE - the instruction uses zeroing.
+ ND_BOOL HasEr:1; // TRUE - the instruction has embedded rounding.
+ ND_BOOL HasSae:1; // TRUE - the instruction has SAE.
+ ND_BOOL HasNd:1; // TRUE - the instruction uses New-Data Destination.
+ ND_BOOL HasNf:1; // TRUE - the instruction uses NoFlags update.
+ ND_BOOL HasZu:1; // TRUE - the instruction has ZeroUpper.
+ ND_BOOL HasIgnEr:1; // TRUE - the instruction ignores embedded rounding.
+
+ // Mandatory prefixes.
+ ND_BOOL HasMandatory66:1; // 0x66 is mandatory prefix. Does not behave as size-changing prefix.
+ ND_BOOL HasMandatoryF2:1; // 0x66 is mandatory prefix. Does not behave as REP prefix.
+ ND_BOOL HasMandatoryF3:1; // 0x66 is mandatory prefix. Does not behave as REP prefix.
+
+ // Prefix activation. Use these fields to check whether a prefix is present & active for the instruction.
+ ND_BOOL IsLockEnabled:1; // TRUE - LOCK is present & used.
+ ND_BOOL IsRepEnabled:1; // TRUE - REP is present & used.
+ ND_BOOL IsRepcEnabled:1; // TRUE - REPZ/REPNZ is present & used.
+ ND_BOOL IsXacquireEnabled:1; // TRUE - the instruction is XACQUIRE enabled.
+ ND_BOOL IsXreleaseEnabled:1; // TRUE - the instruction is XRELEASE enabled.
+ ND_BOOL IsBhintEnabled:1; // TRUE - branch hints valid & used.
+ ND_BOOL IsBndEnabled:1; // TRUE - BND prefix valid & used.
+ ND_BOOL IsDntEnabled:1; // TRUE - DNT prefix valid & used.
+ ND_BOOL IsRepeated:1; // TRUE - the instruction is REPed up to RCX times.
+ ND_BOOL IsCetTracked:1; // TRUE - this is an indirect CALL/JMP that is CET tracked.
+
+ // Misc.
+ ND_UINT8 IsRipRelative:1; // TRUE - the instruction uses RIP relative addressing.
+ ND_UINT8 RoundingMode:2; // EVEX rounding mode, if present. One of ND_ROUNDING.
+
+ // Instruction components lengths. Will be 0 if the given field is not present.
+ ND_UINT8 Length; // 1-15 valid. Instructions longer than 15 bytes will cause #GP.
+ ND_UINT8 WordLength:4; // The length of the instruction word. 2, 4 or 8.
+ ND_UINT8 StackWords:4; // Number of words accessed on/from the stack. 0-15.
+
+ ND_UINT8 PrefLength:4; // The total number of bytes consumed by prefixes. This will also be
+ // the offset to the first opcode. The primary opcode will always be
+ // the last one, so at offset PrefixesLength + OpcodeLength - 1
+ ND_UINT8 OpLength:4; // Number of opcode bytes. Max 3.
+ ND_UINT8 DispLength:4; // Displacement length, in bytes. Maximum 4.
+ ND_UINT8 AddrLength:4; // Absolute address length, in bytes. Maximum 8 bytes.
+ ND_UINT8 MoffsetLength:4; // Memory offset length, in bytes. Maximum 8 bytes.
+ ND_UINT8 Imm1Length:4; // First immediate length, in bytes. Maximum 8 bytes.
+ ND_UINT8 Imm2Length:4; // Second immediate length, in bytes. Maximum 1 byte.
+ ND_UINT8 RelOffsLength:4; // Relative offset length, in bytes. Maximum 4 bytes.
+
+ // Instruction components offsets. Will be 0 if the given field is not present. Prefixes ALWAYS start at offset 0.
+ ND_UINT8 OpOffset:4; // The offset of the first opcode, inside the instruction.
+ ND_UINT8 MainOpOffset:4; // The offset of the nominal opcode, inside the instruction.
+ ND_UINT8 DispOffset:4; // The offset of the displacement, inside the instruction
+ ND_UINT8 AddrOffset:4; // The offset of the hard-coded address.
+ ND_UINT8 MoffsetOffset:4; // The offset of the absolute address, inside the instruction
+ ND_UINT8 Imm1Offset:4; // The offset of the immediate, inside the instruction
+ ND_UINT8 Imm2Offset:4; // The offset of the second immediate, if any, inside the instruction
+ ND_UINT8 RelOffsOffset:4; // The offset of the relative offset used in instruction.
+ ND_UINT8 SseImmOffset:4; // The offset of the SSE immediate, if any, inside the instruction.
+ ND_UINT8 ModRmOffset:4; // The offset of the mod rm byte inside the instruction, if any.
+ // If SIB is also present, it will always be at ModRmOffset + 1.
+
+ // This structures contains the fields extracted from either REX, REX2, XOP, VEX, or EVEX fields.
+ // They're globally placed here, in order to avoid testing for each kind of prefix each time.
+ // Instead, one can use the different fields directly from here, regardless the actual encoding mode.
+ struct
+ {
+ ND_UINT32 w:1; // REX/REX2/XOP/VEX/EVEX.W
+ ND_UINT32 r:1; // REX/REX2/XOP/VEX/EVEX.R3 (reg extension)
+ ND_UINT32 x:1; // REX/REX2/XOP/VEX/EVEX.X3 (index extension)
+ ND_UINT32 b:1; // REX/REX2/XOP/VEX/EVEX.B3 (base extension)
+ ND_UINT32 rp:1; // REX2/EVEX.R4 (reg extension, previously known as R')
+ ND_UINT32 x4:1; // REX2/EVEX.X4 (index extension)
+ ND_UINT32 b4:1; // REX2/EVEX.B4 (base extension)
+ ND_UINT32 p:2; // XOP/VEX/EVEX.pp (embedded prefix)
+ ND_UINT32 m:5; // XOP/VEX/EVEX.mmmmm (decoding table)
+ ND_UINT32 l:2; // XOP/VEX.L or EVEX.L'L (vector length)
+ ND_UINT32 v:4; // XOP/VEX/EVEX.VVVV (additional operand)
+ ND_UINT32 vp:1; // EVEX.V4 (vvvv extension, previously known as V')
+ ND_UINT32 bm:1; // EVEX.b (embedded broadcast)
+ ND_UINT32 z:1; // EVEX.z (zero)
+ ND_UINT32 k:3; // EVEX.aaa (mask registers)
+ ND_UINT32 nd:1; // EVEX.ND (new data destination)
+ ND_UINT32 nf:1; // EVEX.NF (no-flags)
+ ND_UINT32 sc:4; // EVEX.SC0,SC1,SC2,SC3 (standard condition).
+ } Exs;
+
+ // Raw instruction components.
+ ND_UINT8 Rep; // The last rep/repz/repnz prefix. 0 if none.
+ ND_UINT8 Seg; // The last segment override prefix. 0 if none. FS/GS if 64 bit.
+ ND_MODRM ModRm; // ModRM byte.
+ ND_SIB Sib; // SIB byte.
+
+ union
+ {
+ ND_REX Rex; // REX prefix.
+ ND_REX2 Rex2; // REX2 prefix.
+ ND_VEX2 Vex2; // VEX 2 prefix.
+ ND_VEX3 Vex3; // VEX 3 prefix.
+ ND_XOP Xop; // XOP prefix.
+ ND_EVEX Evex; // EVEX prefix.
+ };
+
+ // An Address, Moffset, Displacement or RelativeOffset cannot be present at the same time.
+ union
+ {
+ ND_UINT32 Displacement; // Displacement. Max 4 bytes. Used in ModRM instructions.
+ ND_UINT32 RelativeOffset; // Relative offset, used for branches. Max 4 bytes.
+ ND_UINT64 Moffset; // Offset. Used by 'O' operands. It's an absolute address.
+ ND_UINT64 AddressNear; // target64 near address.
+ struct
+ {
+ ND_UINT32 Ip;
+ ND_UINT16 Cs;
+ } Address; // seg:offset far address.
+ };
+ ND_UINT64 Immediate1; // Can be 8 bytes on x64.
+ union
+ {
+ ND_UINT8 Immediate2; // For enter, mainly. Can only be 1 byte.
+ ND_UINT8 SseImmediate; // This immediate actually selects a register.
+ };
+
+ ND_UINT8 OperandsCount:4; // Number of operands (total).
+ ND_UINT8 ExpOperandsCount:4; // Number of explicit operands. Use this if you want to ignore
+ // implicit operands such as stack, flags, etc.
+ ND_OPERAND Operands[ND_MAX_OPERAND]; // Instruction operands.
+
+ // SIMD/EVEX information.
+ ND_SIMD_EXCEPTIONS SimdExceptions; // SIMD Floating-Point Exceptions. Valid only for SIMD instructions!
+ ND_UINT8 ExceptionType; // Exception type. One of ND_EX_TYPE.
+ ND_UINT8 TupleType; // EVEX tuple type, if EVEX. One of ND_TUPLE.
+
+ // As extracted from the operands themselves.
+ ND_UINT8 CsAccess; // CS access mode (read/write). Includes only implicit CS accesses.
+ ND_UINT8 RipAccess; // RIP access mode (read/write).
+ ND_UINT8 RflAccess; // RFLAGS access mode (read/write), as per the entire register.
+ ND_UINT8 StackAccess; // Stack access mode (push/pop).
+ ND_UINT8 MemoryAccess; // Memory access mode (read/write, including stack or shadow stack).
+ ND_FPU_FLAGS FpuFlagsAccess; // FPU status word C0-C3 bits access. Valid only for FPU instructions!
+ ND_BRANCH_INFO BranchInfo; // Branch information.
+
+ struct
+ {
+ ND_RFLAGS Tested; // Tested flags.
+ ND_RFLAGS Modified; // Modified (according to the result) flags.
+ ND_RFLAGS Set; // Flags that are always set to 1.
+ ND_RFLAGS Cleared; // Flags that are always cleared to 0.
+ ND_RFLAGS Undefined; // Undefined flags.
+ } FlagsAccess;
+
+ // Stored inside the instruction entry as well. These are specific for an instruction and do not depend on
+ // encoding. Use the flags definitions (ND_FLAG_*, ND_PREF_*, ND_DECO_*, ND_EXOP_*) to access specific bits.
+ ND_UINT64 Attributes; // Instruction attributes/flags. A collection of ND_FLAG_*.
+
+ // Instruction metadata.
+ ND_INS_CLASS Instruction; // One of the ND_INS_*
+ ND_INS_CATEGORY Category; // One of the ND_CAT_*
+ ND_INS_SET IsaSet; // One of the ND_SET_*
+
+ ND_CPUID_FLAG CpuidFlag; // CPUID support flag.
+ ND_VALID_MODES ValidModes; // Valid CPU modes for the instruction.
+ ND_VALID_PREFIXES ValidPrefixes; // Indicates which prefixes are valid for this instruction.
+ ND_VALID_DECORATORS ValidDecorators; // What decorators are accepted by the instruction.
+
+ // Instruction bytes & mnemonic.
+ union
+ {
+ ND_UINT8 PrimaryOpCode; // Main opcode.
+ ND_UINT8 Condition:4; // Condition code. Valid only if ND_FLAG_COND is set in Attributes.
+ // Aliased over low 4 bits inside the main opcode.
+ };
+
+#ifndef BDDISASM_NO_MNEMONIC
+ const char *Mnemonic; // Instruction mnemonic.
+#endif // !BDDISASM_NO_MNEMONIC
+ ND_UINT8 InstructionBytes[16]; // The entire instruction.
+ ND_UINT8 OpCodeBytes[3]; // Opcode bytes - escape codes and main opcode.
+
+} INSTRUX, *PINSTRUX;
+
+
+
+//
+// Decoder context. Such a structure must be passed to the NdDecodeWithContext API. This structure must be initialized
+// only once, and then it can be re-used across NdDecodeWithContext calls.
+//
+typedef struct _ND_CONTEXT
+{
+ ND_UINT64 DefCode : 4; // Decode mode - one of the ND_CODE_* values.
+ ND_UINT64 DefData : 4; // Data mode - one of the ND_DATA_* values.
+ ND_UINT64 DefStack : 4; // Stack mode - one of the ND_STACK_* values.
+ ND_UINT64 VendMode : 4; // Prefered vendor - one of the ND_VEND_* values.
+ ND_UINT64 FeatMode : 8; // Supported features mask. A combination of ND_FEAT_* values.
+ ND_UINT64 Reserved : 40; // Reserved for future use.
+ ND_UINT32 Options; // Decoding options. A combination of ND_OPTION_* values.
+} ND_CONTEXT;
+
+/// Decode only explicit instruction operands. If this options is set, implicit operands, such as RIP or RFLAGS
+/// will not be decoded. As a consequence, the following fields inside INSTRUX will be undefined:
+/// CsAccess, RipAccess, RflAccess, StackAcces, MemoryAccess, BranchInfo.
+#define ND_OPTION_ONLY_EXPLICIT_OPERANDS 0x00000001
+
+// Do NOT zero the output INSTRUX structure before decoding this instruction. Use this option only if the
+// output INSTRUX structure is already zeroed (for example, as is the case when allocating it with calloc).
+// Make sure to NOT use this option when making succesive decode calls on the same buffer - this option
+// should only be used when decoding an instruction in an output buffer that has just been allocated and
+// has been 0-initialized, or if the caller explictly zeroed it before each decode call.
+#define ND_OPTION_SKIP_ZERO_INSTRUX 0x00000002
+
+
+//
+// Operands access map. Contains every register except for MSR & XCR, includes memory, flags, RIP, stack.
+// Use NdGetFullAccessMap to populate this structure.
+//
+typedef struct _ND_ACCESS_MAP
+{
+ ND_UINT8 RipAccess;
+ ND_UINT8 FlagsAccess;
+ ND_UINT8 StackAccess;
+ ND_UINT8 MemAccess;
+ ND_UINT8 MxcsrAccess;
+ ND_UINT8 PkruAccess;
+ ND_UINT8 SspAccess;
+ ND_UINT8 GprAccess[ND_MAX_GPR_REGS];
+ ND_UINT8 SegAccess[ND_MAX_SEG_REGS];
+ ND_UINT8 FpuAccess[ND_MAX_FPU_REGS];
+ ND_UINT8 MmxAccess[ND_MAX_MMX_REGS];
+ ND_UINT8 SseAccess[ND_MAX_SSE_REGS];
+ ND_UINT8 CrAccess [ND_MAX_CR_REGS ];
+ ND_UINT8 DrAccess [ND_MAX_DR_REGS ];
+ ND_UINT8 TrAccess [ND_MAX_TR_REGS ];
+ ND_UINT8 BndAccess[ND_MAX_BND_REGS];
+ ND_UINT8 MskAccess[ND_MAX_MSK_REGS];
+ ND_UINT8 TmmAccess[ND_MAX_TILE_REGS];
+ ND_UINT8 SysAccess[ND_MAX_SYS_REGS];
+ ND_UINT8 X87Access[ND_MAX_X87_REGS];
+} ND_ACCESS_MAP, *PND_ACCESS_MAP;
+
+
+//
+// Operand reverse-lookup table. Each entry inside this structure contains the pointer to the relevant operand.
+// Some rules govern this special structure:
+// - It is not generated by default. The user must call NdGetOperandRlut manually to fill in this structure.
+// - This structure holds pointers inside the INSTRUX provided to the NdGetOperandRlut function; please make sure
+// you call NdGetOperandRlut again if the INSTRUX is relocated, as all the pointers will dangle.
+// - Not all the operand types have a corresponding entry in ND_OPERAND_RLUT, only the usual ones.
+// - Some operands may have multiple entries in ND_OPERAND_RLUT - for example, RMW (read-modify-write) instructions
+// will have Dst1 and Src1 pointing to the same operand.
+// - The implicit registers entries in ND_OPERAND_RLUT will point to the operand which is of that type, and implicit;
+// for example, ND_OPERAND_RLUT.Rax will be NULL for `add rax, rcx`, since in this case, `rax` is not an implicit
+// operand. For `cpuid`, however, ND_OPERAND_RLUT.Rax will point to the implicit `eax` register.
+// Use NdGetOperandRlut to populate this structure.
+//
+typedef struct _ND_OPERAND_RLUT
+{
+ PND_OPERAND Dst1; // First destination operand.
+ PND_OPERAND Dst2; // Second destination operand.
+ PND_OPERAND Src1; // First source operand.
+ PND_OPERAND Src2; // Second source operand.
+ PND_OPERAND Src3; // Third source operand.
+ PND_OPERAND Src4; // Fourth source operand.
+ PND_OPERAND Mem1; // First memory operand.
+ PND_OPERAND Mem2; // Second memory operand.
+ PND_OPERAND Stack; // Stack operand.
+ PND_OPERAND Flags; // Flags register operand.
+ PND_OPERAND Rip; // Instruction Pointer register operand.
+ PND_OPERAND Cs; // Implicit CS operand.
+ PND_OPERAND Ss; // Implicit SS operand.
+ PND_OPERAND Rax; // Implicit accumulator register operand.
+ PND_OPERAND Rcx; // Implicit counter register operand.
+ PND_OPERAND Rdx; // Implicit data register operand
+ PND_OPERAND Rbx; // Implicit base address register operand.
+ PND_OPERAND Rsp; // Implicit stack pointer operand.
+ PND_OPERAND Rbp; // Implicit base pointer operand.
+ PND_OPERAND Rsi; // Implicit source index operand.
+ PND_OPERAND Rdi; // Implicit destination index operand.
+} ND_OPERAND_RLUT;
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Returns the bddisasm version.
+//
+void
+NdGetVersion(
+ ND_UINT32 *Major,
+ ND_UINT32 *Minor,
+ ND_UINT32 *Revision,
+ const char **BuildDate,
+ const char **BuildTime
+ );
+
+//
+// Decode one instruction. Note that this is equivalent to:
+// NdDecodeEx(Instrux, Code, ND_MAX_INSTRUCTION_LEN, DefCode, DefData).
+// This version should be used if the caller doesn't care about the length of the buffer. Otherwise, use the other
+// decode API.
+//
+NDSTATUS
+NdDecode(
+ INSTRUX *Instrux, // Output decoded instruction.
+ const ND_UINT8 *Code, // Buffer containing the instruction bytes.
+ ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values.
+ ND_UINT8 DefData // Data mode - one of the ND_DATA_* value.
+ );
+
+//
+// Decode one instruction. Note that this is equivalent to:
+// NdDecodeEx2(Instrux, Code, Size, DefCode, DefData, DefCode, ND_VEND_ANY).
+// By default, the used vendor will be ND_VEND_ANY, so all instructions will be decoded.
+// By default, the feature mode will be ND_FEAT_ALL, so all instructions will be decoded (but may yield error where
+// otherwise a NOP would be encoded - use ND_FEAT_NONE in that case).
+//
+NDSTATUS
+NdDecodeEx(
+ INSTRUX *Instrux, // Output decoded instruction.
+ const ND_UINT8 *Code, // Buffer containing the instruction bytes.
+ ND_SIZET Size, // Maximum size of the Code buffer.
+ ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values.
+ ND_UINT8 DefData // Data mode - one of the ND_DATA_* value.
+ );
+
+//
+// Fills a ND_CONTEXT structure, and calls NdDecodeWithContext. The feature mode will be ND_FEAT_ALL by default.
+//
+NDSTATUS
+NdDecodeEx2(
+ INSTRUX *Instrux, // Output decoded instruction.
+ const ND_UINT8 *Code, // Buffer containing the instruction bytes.
+ ND_SIZET Size, // Maximum size of the Code buffer.
+ ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values.
+ ND_UINT8 DefData, // Data mode - one of the ND_DATA_* value.
+ ND_UINT8 DefStack, // Stack mode - one of the ND_STACK_* values.
+ ND_UINT8 PreferedVendor // Preferred vendor - one of the ND_VEND_* values.
+ );
+
+//
+// This API received a decode context, where it expects DefCode, DefData, DefStack, VendMode and FeatMode to be
+// already initialized. The Context will not be modified by the decoder, so it can be reused across decode calls.
+// The Context should initially be initialized using NdInitContext. This will ensure backwards compatibility
+// by setting new fields to default values.
+// Note that this is the base decoding API, and this ends up being called by all the other decoding APIs, after
+// providing default arguments and filling them in the Context structure. For maximum speed, use this instead of
+// the others.
+//
+NDSTATUS
+NdDecodeWithContext(
+ INSTRUX *Instrux, // Output decoded instruction.
+ const ND_UINT8 *Code, // Buffer containing the instruction bytes.
+ ND_SIZET Size, // Maximum size of the Code buffer.
+ ND_CONTEXT *Context // Context describing decode mode, vendor mode and supported features.
+ );
+
+//
+// Convert the given instruction into textual representation (Intel syntax).
+//
+NDSTATUS
+NdToText(
+ const INSTRUX *Instrux,
+ ND_UINT64 Rip,
+ ND_UINT32 BufferSize,
+ char *Buffer
+ );
+
+//
+// Returns true if the instruction is RIP relative. Note that this function is kept for backwards compatibility, since
+// there already is a IsRipRelative field inside INSTRUX.
+//
+ND_BOOL
+NdIsInstruxRipRelative(
+ const INSTRUX *Instrux
+ );
+
+//
+// Returns an access map that contains the access for each register.
+//
+NDSTATUS
+NdGetFullAccessMap(
+ const INSTRUX *Instrux,
+ ND_ACCESS_MAP *AccessMap
+ );
+
+//
+// Returns an operand reverse-lookup. One can use the Rlut to quickly reference different kinds of operands in INSTRUX.
+//
+NDSTATUS
+NdGetOperandRlut(
+ const INSTRUX *Instrux,
+ ND_OPERAND_RLUT *Rlut
+ );
+
+//
+// Initialize the decoder context.
+//
+void
+NdInitContext(
+ ND_CONTEXT *Context
+ );
+
+#ifdef __cplusplus
+}
+#endif
+
+// #pragma warning(default: 4214) // Bitfield in type other than int.
+// #pragma warning(default: 4201) // Nonstandard extension used: nameless struct/union.
+#ifdef _MSC_VER
+#pragma warning(pop)
+#endif
+
+#endif // BDX86_CORE_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bdx86_cpuidflags.h b/compiler-rt/lib/interception/bddisasm/inc/bdx86_cpuidflags.h
new file mode 100644
index 00000000000000..77d6e862a65b29
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bdx86_cpuidflags.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2024 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//
+// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
+//
+
+#ifndef BDX86_CPUID_FLAGS_H
+#define BDX86_CPUID_FLAGS_H
+
+#define ND_CFF_NO_LEAF 0xFFFFFFFF
+#define ND_CFF_NO_SUBLEAF 0x00FFFFFF
+
+
+#define ND_CFF(leaf, subleaf, reg, bit) ((ND_UINT64)(leaf) | ((ND_UINT64)((subleaf) & 0xFFFFFF) << 32) | ((ND_UINT64)(reg) << 56) | ((ND_UINT64)(bit) << 59))
+#define ND_CFF_FPU ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 0)
+#define ND_CFF_MSR ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 5)
+#define ND_CFF_CX8 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 8)
+#define ND_CFF_SEP ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 11)
+#define ND_CFF_CMOV ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 15)
+#define ND_CFF_CLFSH ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 19)
+#define ND_CFF_MMX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 23)
+#define ND_CFF_FXSAVE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 24)
+#define ND_CFF_SSE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 25)
+#define ND_CFF_SSE2 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 26)
+#define ND_CFF_SSE3 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 0)
+#define ND_CFF_PCLMULQDQ ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 1)
+#define ND_CFF_MONITOR ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 3)
+#define ND_CFF_VTX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 5)
+#define ND_CFF_SMX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 6)
+#define ND_CFF_SSSE3 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 9)
+#define ND_CFF_FMA ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 12)
+#define ND_CFF_SSE4 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 19)
+#define ND_CFF_SSE42 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 20)
+#define ND_CFF_MOVBE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 22)
+#define ND_CFF_POPCNT ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 23)
+#define ND_CFF_AES ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 25)
+#define ND_CFF_XSAVE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 26)
+#define ND_CFF_AVX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 28)
+#define ND_CFF_F16C ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 29)
+#define ND_CFF_RDRAND ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 30)
+#define ND_CFF_RDWRFSGS ND_CFF(0x00000007, 0x00000000, NDR_EBX, 0)
+#define ND_CFF_SGX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 2)
+#define ND_CFF_BMI1 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 3)
+#define ND_CFF_HLE ND_CFF(0x00000007, 0x00000000, NDR_EBX, 4)
+#define ND_CFF_AVX2 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 5)
+#define ND_CFF_BMI2 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 8)
+#define ND_CFF_INVPCID ND_CFF(0x00000007, 0x00000000, NDR_EBX, 10)
+#define ND_CFF_RTM ND_CFF(0x00000007, 0x00000000, NDR_EBX, 11)
+#define ND_CFF_MPX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 14)
+#define ND_CFF_AVX512F ND_CFF(0x00000007, 0x00000000, NDR_EBX, 16)
+#define ND_CFF_AVX512DQ ND_CFF(0x00000007, 0x00000000, NDR_EBX, 17)
+#define ND_CFF_RDSEED ND_CFF(0x00000007, 0x00000000, NDR_EBX, 18)
+#define ND_CFF_ADX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 19)
+#define ND_CFF_SMAP ND_CFF(0x00000007, 0x00000000, NDR_EBX, 20)
+#define ND_CFF_AVX512IFMA ND_CFF(0x00000007, 0x00000000, NDR_EBX, 21)
+#define ND_CFF_CLFSHOPT ND_CFF(0x00000007, 0x00000000, NDR_EBX, 23)
+#define ND_CFF_CLWB ND_CFF(0x00000007, 0x00000000, NDR_EBX, 24)
+#define ND_CFF_AVX512PF ND_CFF(0x00000007, 0x00000000, NDR_EBX, 26)
+#define ND_CFF_AVX512ER ND_CFF(0x00000007, 0x00000000, NDR_EBX, 27)
+#define ND_CFF_AVX512CD ND_CFF(0x00000007, 0x00000000, NDR_EBX, 28)
+#define ND_CFF_SHA ND_CFF(0x00000007, 0x00000000, NDR_EBX, 29)
+#define ND_CFF_AVX512BW ND_CFF(0x00000007, 0x00000000, NDR_EBX, 30)
+#define ND_CFF_PREFETCHWT1 ND_CFF(0x00000007, 0x00000000, NDR_ECX, 0)
+#define ND_CFF_AVX512VBMI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 1)
+#define ND_CFF_PKU ND_CFF(0x00000007, 0x00000000, NDR_ECX, 3)
+#define ND_CFF_WAITPKG ND_CFF(0x00000007, 0x00000000, NDR_ECX, 5)
+#define ND_CFF_AVX512VBMI2 ND_CFF(0x00000007, 0x00000000, NDR_ECX, 6)
+#define ND_CFF_CET_SS ND_CFF(0x00000007, 0x00000000, NDR_ECX, 7)
+#define ND_CFF_GFNI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 8)
+#define ND_CFF_VAES ND_CFF(0x00000007, 0x00000000, NDR_ECX, 9)
+#define ND_CFF_VPCLMULQDQ ND_CFF(0x00000007, 0x00000000, NDR_ECX, 10)
+#define ND_CFF_AVX512VNNI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 11)
+#define ND_CFF_AVX512BITALG ND_CFF(0x00000007, 0x00000000, NDR_ECX, 12)
+#define ND_CFF_AVX512VPOPCNTDQ ND_CFF(0x00000007, 0x00000000, NDR_ECX, 14)
+#define ND_CFF_RDPID ND_CFF(0x00000007, 0x00000000, NDR_ECX, 22)
+#define ND_CFF_KL ND_CFF(0x00000007, 0x00000000, NDR_ECX, 23)
+#define ND_CFF_CLDEMOTE ND_CFF(0x00000007, 0x00000000, NDR_ECX, 25)
+#define ND_CFF_MOVDIRI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 27)
+#define ND_CFF_MOVDIR64B ND_CFF(0x00000007, 0x00000000, NDR_ECX, 28)
+#define ND_CFF_ENQCMD ND_CFF(0x00000007, 0x00000000, NDR_ECX, 29)
+#define ND_CFF_AVX5124VNNIW ND_CFF(0x00000007, 0x00000000, NDR_EDX, 2)
+#define ND_CFF_AVX5124FMAPS ND_CFF(0x00000007, 0x00000000, NDR_EDX, 3)
+#define ND_CFF_UINTR ND_CFF(0x00000007, 0x00000000, NDR_EDX, 5)
+#define ND_CFF_AVX512VP2INTERSECT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 8)
+#define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 14)
+#define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, NDR_EDX, 16)
+#define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, NDR_EDX, 18)
+#define ND_CFF_CET_IBT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 20)
+#define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 22)
+#define ND_CFF_AVX512FP16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 23)
+#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24)
+#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25)
+#define ND_CFF_SHA512 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 0)
+#define ND_CFF_SM3 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 1)
+#define ND_CFF_SM4 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 2)
+#define ND_CFF_RAOINT ND_CFF(0x00000007, 0x00000001, NDR_EAX, 3)
+#define ND_CFF_AVXVNNI ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4)
+#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5)
+#define ND_CFF_CMPCCXADD ND_CFF(0x00000007, 0x00000001, NDR_EAX, 7)
+#define ND_CFF_FRED ND_CFF(0x00000007, 0x00000001, NDR_EAX, 17)
+#define ND_CFF_LKGS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 18)
+#define ND_CFF_WRMSRNS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 19)
+#define ND_CFF_AMXFP16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 21)
+#define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22)
+#define ND_CFF_AVXIFMA ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23)
+#define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27)
+#define ND_CFF_MOVRS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 31)
+#define ND_CFF_TSE ND_CFF(0x00000007, 0x00000001, NDR_EBX, 1)
+#define ND_CFF_MSR_IMM ND_CFF(0x00000007, 0x00000001, NDR_ECX, 5)
+#define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4)
+#define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5)
+#define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8)
+#define ND_CFF_AVXVNNIINT16 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 10)
+#define ND_CFF_PREFETCHITI ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14)
+#define ND_CFF_USER_MSR ND_CFF(0x00000007, 0x00000001, NDR_EDX, 15)
+#define ND_CFF_APX_F ND_CFF(0x00000007, 0x00000001, NDR_EDX, 21)
+#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0)
+#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
+#define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3)
+#define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, NDR_EBX, 4)
+#define ND_CFF_AMXFP8 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 4)
+#define ND_CFF_AMXTRANSPOSE ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 5)
+#define ND_CFF_AMXTF32 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 6)
+#define ND_CFF_AMXAVX512 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 7)
+#define ND_CFF_AMXMOVRS ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 8)
+#define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 2)
+#define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 5)
+#define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 6)
+#define ND_CFF_PREFETCHW ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 8)
+#define ND_CFF_FSC ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 11)
+#define ND_CFF_XOP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 11)
+#define ND_CFF_LWP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 15)
+#define ND_CFF_FMA4 ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 16)
+#define ND_CFF_TBM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 21)
+#define ND_CFF_INVLPGB ND_CFF(0x80000001, 0xFFFFFFFF, NDR_EDX, 24)
+#define ND_CFF_RDTSCP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 27)
+#define ND_CFF_3DNOW ND_CFF(0x80000001, 0xFFFFFFFF, NDR_EDX, 31)
+#define ND_CFF_WBNOINVD ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 9)
+#define ND_CFF_RDPRU ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 4)
+#define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 8)
+#define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 4)
+#define ND_CFF_RMPQUERY ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 6)
+#define ND_CFF_RMPREAD ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 21)
+
+#endif // CPUID_FLAGS_H
diff --git a/compiler-rt/lib/interception/bddisasm/inc/bdx86_registers.h b/compiler-rt/lib/interception/bddisasm/inc/bdx86_registers.h
new file mode 100644
index 00000000000000..3904e3d37aad0c
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/inc/bdx86_registers.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2020 Bitdefender
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef BDX86_REGISTERS_H
+#define BDX86_REGISTERS_H
+
+//
+// Registers enumerations
+//
+enum
+{
+ NDR_RAX, NDR_RCX, NDR_RDX, NDR_RBX, NDR_RSP, NDR_RBP, NDR_RSI, NDR_RDI,
+ NDR_R8, NDR_R9, NDR_R10, NDR_R11, NDR_R12, NDR_R13, NDR_R14, NDR_R15,
+ NDR_R16, NDR_R17, NDR_R18, NDR_R19, NDR_R20, NDR_R21, NDR_R22, NDR_R23,
+ NDR_R24, NDR_R25, NDR_R26, NDR_R27, NDR_R28, NDR_R29, NDR_R30, NDR_R31,
+};
+
+enum
+{
+ NDR_EAX, NDR_ECX, NDR_EDX, NDR_EBX, NDR_ESP, NDR_EBP, NDR_ESI, NDR_EDI,
+ NDR_R8D, NDR_R9D, NDR_R10D,NDR_R11D,NDR_R12D,NDR_R13D,NDR_R14D,NDR_R15D,
+ NDR_R16D, NDR_R17D, NDR_R18D, NDR_R19D, NDR_R20D, NDR_R21D, NDR_R22D, NDR_R23D,
+ NDR_R24D, NDR_R25D, NDR_R26D, NDR_R27D, NDR_R28D, NDR_R29D, NDR_R30D, NDR_R31D,
+};
+
+enum
+{
+ NDR_AX, NDR_CX, NDR_DX, NDR_BX, NDR_SP, NDR_BP, NDR_SI, NDR_DI,
+ NDR_R8W, NDR_R9W, NDR_R10W,NDR_R11W,NDR_R12W,NDR_R13W,NDR_R14W,NDR_R15W,
+ NDR_R16W, NDR_R17W, NDR_R18W, NDR_R19W, NDR_R20W, NDR_R21W, NDR_R22W, NDR_R23W,
+ NDR_R24W, NDR_R25W, NDR_R26W, NDR_R27W, NDR_R28W, NDR_R29W, NDR_R30W, NDR_R31W,
+};
+
+enum
+{
+ NDR_AL, NDR_CL, NDR_DL, NDR_BL, NDR_AH, NDR_CH, NDR_DH, NDR_BH,
+};
+
+enum
+{
+ NDR_AL64, NDR_CL64, NDR_DL64, NDR_BL64, NDR_SPL, NDR_BPL, NDR_SIL, NDR_DIL,
+ NDR_R8L, NDR_R9L, NDR_R10L, NDR_R11L, NDR_R12L, NDR_R13L, NDR_R14L, NDR_R15L,
+ NDR_R16L, NDR_R17L, NDR_R18L, NDR_R19L, NDR_R20L, NDR_R21L, NDR_R22L, NDR_R23L,
+ NDR_R24L, NDR_R25L, NDR_R26L, NDR_R27L, NDR_R28L, NDR_R29L, NDR_R30L, NDR_R31L,
+};
+
+enum
+{
+ NDR_ES, NDR_CS, NDR_SS, NDR_DS, NDR_FS, NDR_GS, NDR_INV6, NDR_INV7,
+};
+
+enum
+{
+ NDR_CR0, NDR_CR1, NDR_CR2, NDR_CR3, NDR_CR4, NDR_CR5, NDR_CR6, NDR_CR7,
+ NDR_CR8, NDR_CR9, NDR_CR10, NDR_CR11, NDR_CR12, NDR_CR13, NDR_CR14, NDR_CR15,
+ NDR_CR16, NDR_CR17, NDR_CR18, NDR_CR19, NDR_CR20, NDR_CR21, NDR_CR22, NDR_CR23,
+ NDR_CR24, NDR_CR25, NDR_CR26, NDR_CR27, NDR_CR28, NDR_CR29, NDR_CR30, NDR_CR31
+};
+
+enum
+{
+ NDR_DR0, NDR_DR1, NDR_DR2, NDR_DR3, NDR_DR4, NDR_DR5, NDR_DR6, NDR_DR7,
+ NDR_DR8, NDR_DR9, NDR_DR10, NDR_DR11, NDR_DR12, NDR_DR13, NDR_DR14, NDR_DR15,
+ NDR_DR16, NDR_DR17, NDR_DR18, NDR_DR19, NDR_DR20, NDR_DR21, NDR_DR22, NDR_DR23,
+ NDR_DR24, NDR_DR25, NDR_DR26, NDR_DR27, NDR_DR28, NDR_DR29, NDR_DR30, NDR_DR31
+};
+
+enum
+{
+ NDR_TR0, NDR_TR1, NDR_TR2, NDR_TR3, NDR_TR4, NDR_TR5, NDR_TR6, NDR_TR7,
+ NDR_TR8, NDR_TR9, NDR_TR10, NDR_TR11, NDR_TR12, NDR_TR13, NDR_TR14, NDR_TR15,
+};
+
+enum
+{
+ NDR_K0, NDR_K1, NDR_K2, NDR_K3, NDR_K4, NDR_K5, NDR_K6, NDR_K7,
+};
+
+enum
+{
+ NDR_BND0, NDR_BND1, NDR_BND2, NDR_BND3,
+};
+
+enum
+{
+ NDR_ST0, NDR_ST1, NDR_ST2, NDR_ST3, NDR_ST4, NDR_ST5, NDR_ST6, NDR_ST7,
+};
+
+enum
+{
+ NDR_XMM0, NDR_XMM1, NDR_XMM2, NDR_XMM3, NDR_XMM4, NDR_XMM5, NDR_XMM6, NDR_XMM7,
+ NDR_XMM8, NDR_XMM9, NDR_XMM10, NDR_XMM11, NDR_XMM12, NDR_XMM13, NDR_XMM14, NDR_XMM15,
+ NDR_XMM16, NDR_XMM17, NDR_XMM18, NDR_XMM19, NDR_XMM20, NDR_XMM21, NDR_XMM22, NDR_XMM23,
+ NDR_XMM24, NDR_XMM25, NDR_XMM26, NDR_XMM27, NDR_XMM28, NDR_XMM29, NDR_XMM30, NDR_XMM31,
+};
+
+enum
+{
+ NDR_YMM0, NDR_YMM1, NDR_YMM2, NDR_YMM3, NDR_YMM4, NDR_YMM5, NDR_YMM6, NDR_YMM7,
+ NDR_YMM8, NDR_YMM9, NDR_YMM10, NDR_YMM11, NDR_YMM12, NDR_YMM13, NDR_YMM14, NDR_YMM15,
+ NDR_YMM16, NDR_YMM17, NDR_YMM18, NDR_YMM19, NDR_YMM20, NDR_YMM21, NDR_YMM22, NDR_YMM23,
+ NDR_YMM24, NDR_YMM25, NDR_YMM26, NDR_YMM27, NDR_YMM28, NDR_YMM29, NDR_YMM30, NDR_YMM31,
+};
+
+enum
+{
+ NDR_ZMM0, NDR_ZMM1, NDR_ZMM2, NDR_ZMM3, NDR_ZMM4, NDR_ZMM5, NDR_ZMM6, NDR_ZMM7,
+ NDR_ZMM8, NDR_ZMM9, NDR_ZMM10, NDR_ZMM11, NDR_ZMM12, NDR_ZMM13, NDR_ZMM14, NDR_ZMM15,
+ NDR_ZMM16, NDR_ZMM17, NDR_ZMM18, NDR_ZMM19, NDR_ZMM20, NDR_ZMM21, NDR_ZMM22, NDR_ZMM23,
+ NDR_ZMM24, NDR_ZMM25, NDR_ZMM26, NDR_ZMM27, NDR_ZMM28, NDR_ZMM29, NDR_ZMM30, NDR_ZMM31,
+};
+
+enum
+{
+ NDR_GDTR, NDR_IDTR, NDR_LDTR, NDR_TR,
+};
+
+enum
+{
+ NDR_X87_CONTROL, NDR_X87_TAG, NDR_X87_STATUS,
+};
+
+enum
+{
+ NDR_XCR0, NDR_XCR1, NDR_XCR_ANY = 0xFF,
+};
+
+#define NDR_IA32_TSC 0x00000010
+#define NDR_IA32_SYSENTER_CS 0x00000174
+#define NDR_IA32_SYSENTER_ESP 0x00000175
+#define NDR_IA32_SYSENTER_EIP 0x00000176
+#define NDR_IA32_STAR 0xC0000081
+#define NDR_IA32_LSTAR 0xC0000082
+#define NDR_IA32_FMASK 0xC0000084
+#define NDR_IA32_FS_BASE 0xC0000100
+#define NDR_IA32_GS_BASE 0xC0000101
+#define NDR_IA32_KERNEL_GS_BASE 0xC0000102
+#define NDR_IA32_TSC_AUX 0xC0000103
+#define NDR_MSR_ANY 0xFFFFFFFF
+
+#define NDR_RFLAG_CF (1ULL << 0)
+#define NDR_RFLAG_PF (1ULL << 2)
+#define NDR_RFLAG_AF (1ULL << 4)
+#define NDR_RFLAG_ZF (1ULL << 6)
+#define NDR_RFLAG_SF (1ULL << 7)
+#define NDR_RFLAG_TF (1ULL << 8)
+#define NDR_RFLAG_IF (1ULL << 9)
+#define NDR_RFLAG_DF (1ULL << 10)
+#define NDR_RFLAG_OF (1ULL << 11)
+#define NDR_RFLAG_IOPL (3ULL << 12)
+#define NDR_RFLAG_NT (1ULL << 14)
+#define NDR_RFLAG_RF (1ULL << 16)
+#define NDR_RFLAG_VM (1ULL << 17)
+#define NDR_RFLAG_AC (1ULL << 18)
+#define NDR_RFLAG_VIF (1ULL << 19)
+#define NDR_RFLAG_VIP (1ULL << 20)
+#define NDR_RFLAG_ID (1ULL << 21)
+
+#endif
diff --git a/compiler-rt/lib/interception/bddisasm/llvm-project-import.txt b/compiler-rt/lib/interception/bddisasm/llvm-project-import.txt
new file mode 100644
index 00000000000000..7339d73e87a525
--- /dev/null
+++ b/compiler-rt/lib/interception/bddisasm/llvm-project-import.txt
@@ -0,0 +1,2 @@
+This is a minimal import of for evaluation purpose:
+https://github.com/bitdefender/bddisasm
>From dc9394c715940c9b77a3c614252f7cce5a5661b0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Wed, 27 Nov 2024 01:13:19 +0100
Subject: [PATCH 05/20] TEMP: Use bddisasm to verify test results.
---
.../tests/interception_win_test.cpp | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 600eb3779775f4..d0510468cf454a 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -847,6 +847,19 @@ std::string dumpInstruction(unsigned arrayIndex,
return ret.str();
}
+
+
+extern "C" {
+#include "bddisasm/inc/bdx86_core.h"
+#include "bddisasm/bddisasm/bdx86_decoder.c"
+ void *nd_memset(void *s, int c, ND_SIZET n) {
+ memset(s, c, n);
+ return NULL;
+ }
+}
+
+
+
TEST(Interception, GetInstructionSize) {
SetErrorReportCallback(DebugOutputPrinter::Report);
for (unsigned i = 0; i < sizeof(data) / sizeof(*data); i++) {
@@ -855,6 +868,48 @@ TEST(Interception, GetInstructionSize) {
(uptr)data[i].instr, &rel_offset);
EXPECT_EQ(data[i].size, size) << dumpInstruction(i, data[i]);
EXPECT_EQ(data[i].rel_offset, rel_offset) << dumpInstruction(i, data[i]);
+
+ INSTRUX instrux;
+ ND_CONTEXT ctx = { 0 };
+ NDSTATUS status;
+ NdInitContext(&ctx);
+#if SANITIZER_WINDOWS_x64
+ ctx.DefCode = ND_CODE_64;
+#else
+ ctx.DefCode = ND_CODE_32;
+#endif
+ ctx.DefData = ctx.DefCode;
+ ctx.DefStack = ctx.DefCode;
+ ctx.VendMode = ND_VEND_ANY;
+ ctx.FeatMode = ND_FEAT_ALL;
+
+ status = NdDecodeWithContext(&instrux, (const ND_UINT8 *)data[i].instr, 15, &ctx);
+ if (ND_SUCCESS(status)) {
+ if (data[i].size > 0) {
+ EXPECT_EQ(data[i].size, (size_t)instrux.Length) << dumpInstruction(i, data[i]);
+ if (instrux.OperandsCount == 2 && instrux.HasDisp && instrux.DispLength == 4) {
+ EXPECT_EQ(data[i].rel_offset, (size_t)instrux.DispOffset) << dumpInstruction(i, data[i]);
+ } else {
+ EXPECT_EQ(data[i].rel_offset, (size_t)0) << dumpInstruction(i, data[i]);
+ }
+ }
+ }
+
+ //// check if instruction is possibly the same in 64-bit and 32-bit
+ //if (i > 60) { // last index, which is already visible in i386 and x86_64
+ // if (sizeof(void*) == 8 && data[i].size > 0) {
+ // NdInitContext(&ctx);
+ // ctx.DefCode = ND_CODE_32;
+ // ctx.DefData = ctx.DefCode;
+ // ctx.DefStack = ctx.DefCode;
+ // ctx.VendMode = ND_VEND_ANY;
+ // ctx.FeatMode = ND_FEAT_ALL;
+ // status = NdDecodeWithContext(&instrux, (const ND_UINT8 *)data[i].instr, 15, &ctx);
+ // if (ND_SUCCESS(status)) {
+ // EXPECT_NE(data[i].size, (size_t)instrux.Length) << dumpInstruction(i, data[i]);
+ // }
+ // }
+ //}
}
}
>From 879c8cca9b27bc025f852d9639d528fed8066896 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sun, 1 Dec 2024 15:01:20 +0100
Subject: [PATCH 06/20] TEMP: Use rel_offset just below 4 for now.
Enabling this and using the rel_offset of 4 leads
to a crash in wines 64bit notepad.exe when opening the file open dialog.
---
compiler-rt/lib/interception/tests/interception_win_test.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index d0510468cf454a..38015cb8ab5972 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -887,7 +887,7 @@ TEST(Interception, GetInstructionSize) {
if (ND_SUCCESS(status)) {
if (data[i].size > 0) {
EXPECT_EQ(data[i].size, (size_t)instrux.Length) << dumpInstruction(i, data[i]);
- if (instrux.OperandsCount == 2 && instrux.HasDisp && instrux.DispLength == 4) {
+ if (instrux.OperandsCount == 2 && instrux.HasDisp && instrux.DispLength == 4 && instrux.DispOffset < 4) {
EXPECT_EQ(data[i].rel_offset, (size_t)instrux.DispOffset) << dumpInstruction(i, data[i]);
} else {
EXPECT_EQ(data[i].rel_offset, (size_t)0) << dumpInstruction(i, data[i]);
>From 6e94287ef70fddec07a4a092b395cbaf7e10b290 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sun, 24 Nov 2024 14:50:51 +0100
Subject: [PATCH 07/20] [win/asan] Avoid warnings in interception_win.cpp.
warning: format specifies type 'void *' but the argument has type 'uptr' (aka 'unsigned long long') [-Wformat]
(observed at x86_64, in AllocateTrampolineRegion)
warning: format specifies type 'char *' but the argument has type 'RVAPtr<char>' [-Wformat]
(observed at x86_64, in InternalGetProcAddress)
---
compiler-rt/lib/interception/interception_win.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index dc3018a675dee2..93886e79fd88c8 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -418,7 +418,7 @@ static void *AllocateTrampolineRegion(uptr min_addr, uptr max_addr,
ReportError(
"interception_win: AllocateTrampolineRegion failed to find free memory; "
"min_addr: %p, max_addr: %p, func_addr: %p, granularity: %zu\n",
- (void *)min_addr, (void *)max_addr, granularity);
+ (void *)min_addr, (void *)max_addr, (void *)func_addr, granularity);
return nullptr;
#else
return ::VirtualAlloc(nullptr,
@@ -1247,7 +1247,7 @@ uptr InternalGetProcAddress(void *module, const char *func_name) {
char function_name[256];
size_t funtion_name_length = _strlen(func);
if (funtion_name_length >= sizeof(function_name) - 1) {
- ReportError("interception_win: func too long: '%s'\n", func);
+ ReportError("interception_win: func too long: '%s'\n", (char *)func);
InterceptionFailed();
}
>From 164ebeca7a860da7b9e5f1878bbe8471c987af39 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Tue, 26 Nov 2024 23:58:39 +0100
Subject: [PATCH 08/20] [win/asan] Populate test for function
GetInstructionSize.
---
.../tests/interception_win_test.cpp | 212 +++++++++++++++++-
1 file changed, 209 insertions(+), 3 deletions(-)
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 38015cb8ab5972..55df15774da378 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -826,11 +826,217 @@ const struct InstructionSizeData {
size_t size; // hold instruction size or 0 for failure,
// e.g. on control instructions
u8 instr[16];
- size_t rel_offset;
+ size_t rel_offset; // filled just for instructions with two operands
+ // and displacement length of four bytes.
const char *comment;
} data[] = {
- /* sorted list */
- {1, {0x50}, 0, "50 : push eax / rax"},
+ // clang-format off
+ // sorted list
+ { 0, {0x70, 0x71}, 0, "70 XX : jo XX (short conditional jump)"},
+ { 0, {0x71, 0x71}, 0, "71 XX : jno XX (short conditional jump)"},
+ { 0, {0x72, 0x71}, 0, "72 XX : jb XX (short conditional jump)"},
+ { 0, {0x73, 0x71}, 0, "73 XX : jae XX (short conditional jump)"},
+ { 0, {0x74, 0x71}, 0, "74 XX : je XX (short conditional jump)"},
+ { 0, {0x75, 0x71}, 0, "75 XX : jne XX (short conditional jump)"},
+ { 0, {0x76, 0x71}, 0, "76 XX : jbe XX (short conditional jump)"},
+ { 0, {0x77, 0x71}, 0, "77 XX : ja XX (short conditional jump)"},
+ { 0, {0x78, 0x71}, 0, "78 XX : js XX (short conditional jump)"},
+ { 0, {0x79, 0x71}, 0, "79 XX : jns XX (short conditional jump)"},
+ { 0, {0x7A, 0x71}, 0, "7A XX : jp XX (short conditional jump)"},
+ { 0, {0x7B, 0x71}, 0, "7B XX : jnp XX (short conditional jump)"},
+ { 0, {0x7C, 0x71}, 0, "7C XX : jl XX (short conditional jump)"},
+ { 0, {0x7D, 0x71}, 0, "7D XX : jge XX (short conditional jump)"},
+ { 0, {0x7E, 0x71}, 0, "7E XX : jle XX (short conditional jump)"},
+ { 0, {0x7F, 0x71}, 0, "7F XX : jg XX (short conditional jump)"},
+ { 0, {0xE8, 0x71, 0x72, 0x73, 0x74}, 0, "E8 XX XX XX XX : call <func>"},
+ { 0, {0xE9, 0x71, 0x72, 0x73, 0x74}, 0, "E9 XX XX XX XX : jmp <label>"},
+ { 0, {0xEB, 0x71}, 0, "EB XX : jmp XX (short jump)"},
+ { 0, {0xFF, 0x25, 0x72, 0x73, 0x74, 0x75}, 0, "FF 25 XX YY ZZ WW : jmp dword ptr ds:[WWZZYYXX]"},
+ { 1, {0x50}, 0, "50 : push eax / rax"},
+ { 1, {0x51}, 0, "51 : push ecx / rcx"},
+ { 1, {0x52}, 0, "52 : push edx / rdx"},
+ { 1, {0x53}, 0, "53 : push ebx / rbx"},
+ { 1, {0x54}, 0, "54 : push esp / rsp"},
+ { 1, {0x55}, 0, "55 : push ebp / rbp"},
+ { 1, {0x56}, 0, "56 : push esi / rsi"},
+ { 1, {0x57}, 0, "57 : push edi / rdi"},
+ { 1, {0x5D}, 0, "5D : pop ebp / rbp"},
+ { 1, {0x90}, 0, "90 : nop"},
+ { 1, {0xC3}, 0, "C3 : ret (for small/empty function interception"},
+ { 1, {0xCC}, 0, "CC : int 3 i.e. registering weak functions)"},
+ { 2, {0x33, 0xC0}, 0, "33 C0 : xor eax, eax"},
+ { 2, {0x33, 0xC9}, 0, "33 C9 : xor ecx, ecx"},
+ { 2, {0x33, 0xD2}, 0, "33 D2 : xor edx, edx"},
+ { 2, {0x6A, 0x71}, 0, "6A XX : push XX"},
+ { 2, {0x84, 0xC9}, 0, "84 C9 : test cl,cl"},
+ { 2, {0x84, 0xD2}, 0, "84 D2 : test dl,dl"},
+ { 2, {0x84, 0xDB}, 0, "84 DB : test bl,bl"},
+ { 2, {0x89, 0xE5}, 0, "89 E5 : mov ebp, esp"},
+ { 2, {0x89, 0xc8}, 0, "89 C8 : mov eax, ecx"},
+ { 2, {0x8A, 0x01}, 0, "8A 01 : mov al, byte ptr [ecx]"},
+ { 2, {0x8B, 0xC1}, 0, "8B C1 : mov eax, ecx"},
+ { 2, {0x8B, 0xEC}, 0, "8B EC : mov ebp, esp"},
+ { 2, {0x8B, 0xFF}, 0, "8B FF : mov edi, edi"},
+ { 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"},
+ { 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
+ { 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
+ { 5, {0xb8, 0x71, 0x72, 0x73, 0x74}, 0, "b8 XX XX XX XX : mov eax, XX XX XX XX"},
+#if SANITIZER_WINDOWS_x64
+ // sorted list
+ { 2, {0x40, 0x50}, 0, "40 50 : push rax"},
+ { 2, {0x40, 0x51}, 0, "40 51 : push rcx"},
+ { 2, {0x40, 0x52}, 0, "40 52 : push rdx"},
+ { 2, {0x40, 0x53}, 0, "40 53 : push rbx"},
+ { 2, {0x40, 0x54}, 0, "40 54 : push rsp"},
+ { 2, {0x40, 0x55}, 0, "40 55 : push rbp"},
+ { 2, {0x40, 0x56}, 0, "40 56 : push rsi"},
+ { 2, {0x40, 0x57}, 0, "40 57 : push rdi"},
+ { 2, {0x41, 0x54}, 0, "41 54 : push r12"},
+ { 2, {0x41, 0x55}, 0, "41 55 : push r13"},
+ { 2, {0x41, 0x56}, 0, "41 56 : push r14"},
+ { 2, {0x41, 0x57}, 0, "41 57 : push r15"},
+ { 2, {0x66, 0x90}, 0, "66 90 : Two-byte NOP"},
+ { 2, {0x84, 0xc0}, 0, "84 c0 : test al, al"},
+ { 2, {0x8a, 0x01}, 0, "8a 01 : mov al, byte ptr [rcx]"},
+ { 3, {0x0f, 0xb6, 0xc2}, 0, "0f b6 c2 : movzx eax, dl"},
+ { 3, {0x0f, 0xb6, 0xd2}, 0, "0f b6 d2 : movzx edx, dl"},
+ { 3, {0x0f, 0xb7, 0x10}, 0, "0f b7 10 : movzx edx, WORD PTR [rax]"},
+ { 3, {0x41, 0x8b, 0xc0}, 0, "41 8b c0 : mov eax, r8d"},
+ { 3, {0x41, 0x8b, 0xc1}, 0, "41 8b c1 : mov eax, r9d"},
+ { 3, {0x41, 0x8b, 0xc2}, 0, "41 8b c2 : mov eax, r10d"},
+ { 3, {0x41, 0x8b, 0xc3}, 0, "41 8b c3 : mov eax, r11d"},
+ { 3, {0x41, 0x8b, 0xc4}, 0, "41 8b c4 : mov eax, r12d"},
+ { 3, {0x45, 0x33, 0xc0}, 0, "45 33 c0 : xor r8d, r8d"},
+ { 3, {0x45, 0x33, 0xc9}, 0, "45 33 c9 : xor r9d, r9d"},
+ { 3, {0x45, 0x33, 0xdb}, 0, "45 33 db : xor r11d, r11d"},
+ { 3, {0x48, 0x2b, 0xca}, 0, "48 2b ca : sub rcx, rdx"},
+ { 3, {0x48, 0x2b, 0xd1}, 0, "48 2b d1 : sub rdx, rcx"},
+ { 3, {0x48, 0x3b, 0xca}, 0, "48 3b ca : cmp rcx, rdx"},
+ { 3, {0x48, 0x85, 0xc0}, 0, "48 85 c0 : test rax, rax"},
+ { 3, {0x48, 0x85, 0xc9}, 0, "48 85 c9 : test rcx, rcx"},
+ { 3, {0x48, 0x85, 0xd2}, 0, "48 85 d2 : test rdx, rdx"},
+ { 3, {0x48, 0x85, 0xdb}, 0, "48 85 db : test rbx, rbx"},
+ { 3, {0x48, 0x85, 0xe4}, 0, "48 85 e4 : test rsp, rsp"},
+ { 3, {0x48, 0x85, 0xed}, 0, "48 85 ed : test rbp, rbp"},
+ { 3, {0x48, 0x89, 0xe5}, 0, "48 89 e5 : mov rbp, rsp"},
+ { 3, {0x48, 0x8b, 0xc1}, 0, "48 8b c1 : mov rax, rcx"},
+ { 3, {0x48, 0x8b, 0xc4}, 0, "48 8b c4 : mov rax, rsp"},
+ { 3, {0x48, 0x8b, 0xd1}, 0, "48 8b d1 : mov rdx, rcx"},
+ { 3, {0x48, 0xf7, 0xd9}, 0, "48 f7 d9 : neg rcx"},
+ { 3, {0x48, 0xff, 0xc0}, 0, "48 ff c0 : inc rax"},
+ { 3, {0x48, 0xff, 0xc1}, 0, "48 ff c1 : inc rcx"},
+ { 3, {0x48, 0xff, 0xc2}, 0, "48 ff c2 : inc rdx"},
+ { 3, {0x48, 0xff, 0xc3}, 0, "48 ff c3 : inc rbx"},
+ { 3, {0x48, 0xff, 0xc6}, 0, "48 ff c6 : inc rsi"},
+ { 3, {0x48, 0xff, 0xc7}, 0, "48 ff c7 : inc rdi"},
+ { 3, {0x49, 0xff, 0xc0}, 0, "49 ff c0 : inc r8"},
+ { 3, {0x49, 0xff, 0xc1}, 0, "49 ff c1 : inc r9"},
+ { 3, {0x49, 0xff, 0xc2}, 0, "49 ff c2 : inc r10"},
+ { 3, {0x49, 0xff, 0xc3}, 0, "49 ff c3 : inc r11"},
+ { 3, {0x49, 0xff, 0xc4}, 0, "49 ff c4 : inc r12"},
+ { 3, {0x49, 0xff, 0xc5}, 0, "49 ff c5 : inc r13"},
+ { 3, {0x49, 0xff, 0xc6}, 0, "49 ff c6 : inc r14"},
+ { 3, {0x49, 0xff, 0xc7}, 0, "49 ff c7 : inc r15"},
+ { 3, {0x4c, 0x8b, 0xc1}, 0, "4c 8b c1 : mov r8, rcx"},
+ { 3, {0x4c, 0x8b, 0xc9}, 0, "4c 8b c9 : mov r9, rcx"},
+ { 3, {0x4c, 0x8b, 0xd1}, 0, "4c 8b d1 : mov r10, rcx"},
+ { 3, {0x4c, 0x8b, 0xd2}, 0, "4c 8b d2 : mov r10, rdx"},
+ { 3, {0x4c, 0x8b, 0xd9}, 0, "4c 8b d9 : mov r11, rcx"},
+ { 3, {0x4c, 0x8b, 0xdc}, 0, "4c 8b dc : mov r11, rsp"},
+ { 3, {0x4d, 0x0b, 0xc0}, 0, "4d 0b c0 : or r8, r8"},
+ { 3, {0x4d, 0x85, 0xc0}, 0, "4d 85 c0 : test r8, r8"},
+ { 3, {0x4d, 0x85, 0xc9}, 0, "4d 85 c9 : test r9, r9"},
+ { 3, {0x4d, 0x85, 0xd2}, 0, "4d 85 d2 : test r10, r10"},
+ { 3, {0x4d, 0x85, 0xdb}, 0, "4d 85 db : test r11, r11"},
+ { 3, {0x4d, 0x85, 0xe4}, 0, "4d 85 e4 : test r12, r12"},
+ { 3, {0x4d, 0x85, 0xed}, 0, "4d 85 ed : test r13, r13"},
+ { 3, {0x4d, 0x85, 0xf6}, 0, "4d 85 f6 : test r14, r14"},
+ { 3, {0x4d, 0x85, 0xff}, 0, "4d 85 ff : test r15, r15"},
+ { 4, {0x44, 0x0f, 0xb6, 0x1a}, 0, "44 0f b6 1a : movzx r11d, BYTE PTR [rdx]"},
+ { 4, {0x44, 0x8d, 0x42, 0x73}, 0, "44 8d 42 XX : lea r8d , [rdx + XX]"},
+ { 4, {0x48, 0x83, 0xec, 0x73}, 0, "48 83 ec XX : sub rsp, XX"},
+ { 4, {0x48, 0x89, 0x58, 0x73}, 0, "48 89 58 XX : mov QWORD PTR[rax + XX], rbx"},
+ { 4, {0x49, 0x83, 0xf8, 0x73}, 0, "49 83 f8 XX : cmp r8, XX"},
+ { 4, {0x80, 0x78, 0x72, 0x73}, 0, "80 78 YY XX : cmp BYTE PTR [rax+YY], XX"},
+ { 4, {0x80, 0x79, 0x72, 0x73}, 0, "80 79 YY XX : cmp BYTE ptr [rcx+YY], XX"},
+ { 4, {0x80, 0x7A, 0x72, 0x73}, 0, "80 7A YY XX : cmp BYTE PTR [rdx+YY], XX"},
+ { 4, {0x80, 0x7B, 0x72, 0x73}, 0, "80 7B YY XX : cmp BYTE PTR [rbx+YY], XX"},
+ { 4, {0x80, 0x7D, 0x72, 0x73}, 0, "80 7D YY XX : cmp BYTE PTR [rbp+YY], XX"},
+ { 4, {0x80, 0x7E, 0x72, 0x73}, 0, "80 7E YY XX : cmp BYTE PTR [rsi+YY], XX"},
+ { 4, {0x89, 0x54, 0x24, 0x73}, 0, "89 54 24 XX : mov DWORD PTR[rsp + XX], edx"},
+ { 5, {0x44, 0x89, 0x44, 0x24, 0x74}, 0, "44 89 44 24 XX : mov DWORD PTR [rsp + XX], r8d"},
+ { 5, {0x44, 0x89, 0x4c, 0x24, 0x74}, 0, "44 89 4c 24 XX : mov DWORD PTR [rsp + XX], r9d"},
+ { 5, {0x48, 0x89, 0x4C, 0x24, 0x74}, 0, "48 89 4C 24 XX : mov QWORD PTR [rsp + XX], rcx"},
+ { 5, {0x48, 0x89, 0x54, 0x24, 0x74}, 0, "48 89 54 24 XX : mov QWORD PTR [rsp + XX], rdx"},
+ { 5, {0x48, 0x89, 0x5c, 0x24, 0x74}, 0, "48 89 5c 24 XX : mov QWORD PTR [rsp + XX], rbx"},
+ { 5, {0x48, 0x89, 0x6c, 0x24, 0x74}, 0, "48 89 6C 24 XX : mov QWORD ptr [rsp + XX], rbp"},
+ { 5, {0x48, 0x89, 0x74, 0x24, 0x74}, 0, "48 89 74 24 XX : mov QWORD PTR [rsp + XX], rsi"},
+ { 5, {0x48, 0x89, 0x7c, 0x24, 0x74}, 0, "48 89 7c 24 XX : mov QWORD PTR [rsp + XX], rdi"},
+ { 5, {0x48, 0x8b, 0x44, 0x24, 0x74}, 0, "48 8b 44 24 XX : mov rax, QWORD ptr [rsp + XX]"},
+ { 5, {0x48, 0x8d, 0x6c, 0x24, 0x74}, 0, "48 8d 6c 24 XX : lea rbp, [rsp + XX]"},
+ { 5, {0x4c, 0x89, 0x44, 0x24, 0x74}, 0, "4c 89 44 24 XX : mov QWORD PTR [rsp + XX], r8"},
+ { 5, {0x4c, 0x89, 0x4c, 0x24, 0x74}, 0, "4c 89 4c 24 XX : mov QWORD PTR [rsp + XX], r9"},
+ { 5, {0x83, 0x44, 0x72, 0x73, 0x74}, 0, "83 44 72 XX YY : add DWORD PTR [rdx+rsi*2+XX],YY"},
+ { 5, {0x83, 0x64, 0x24, 0x73, 0x74}, 0, "83 64 24 XX YY : and DWORD PTR [rsp+XX], YY"},
+ { 6, {0x48, 0x83, 0x64, 0x24, 0x74, 0x75}, 0, "48 83 64 24 XX YY : and QWORD PTR [rsp + XX], YY"},
+ { 6, {0x66, 0x81, 0x78, 0x73, 0x74, 0x75}, 0, "66 81 78 XX YY YY : cmp WORD PTR [rax+XX], YY YY"},
+ { 6, {0x66, 0x81, 0x79, 0x73, 0x74, 0x75}, 0, "66 81 79 XX YY YY : cmp WORD PTR [rcx+XX], YY YY"},
+ { 6, {0x66, 0x81, 0x7a, 0x73, 0x74, 0x75}, 0, "66 81 7a XX YY YY : cmp WORD PTR [rdx+XX], YY YY"},
+ { 6, {0x66, 0x81, 0x7b, 0x73, 0x74, 0x75}, 0, "66 81 7b XX YY YY : cmp WORD PTR [rbx+XX], YY YY"},
+ { 6, {0x66, 0x81, 0x7e, 0x73, 0x74, 0x75}, 0, "66 81 7e XX YY YY : cmp WORD PTR [rsi+XX], YY YY"},
+ { 6, {0x66, 0x81, 0x7f, 0x73, 0x74, 0x75}, 0, "66 81 7f XX YY YY : cmp WORD PTR [rdi+XX], YY YY"},
+ { 6, {0x8A, 0x05, 0x72, 0x73, 0x74, 0x75}, 2, "8A 05 XX XX XX XX : mov al, byte ptr [XX XX XX XX]"},
+ { 6, {0x8B, 0x05, 0x72, 0x73, 0x74, 0x75}, 2, "8B 05 XX XX XX XX : mov eax, dword ptr [XX XX XX XX]"},
+ { 6, {0xF2, 0x0f, 0x11, 0x44, 0x24, 0x75}, 0, "f2 0f 11 44 24 XX : movsd QWORD PTR [rsp + XX], xmm0"},
+ { 6, {0xF2, 0x0f, 0x11, 0x4c, 0x24, 0x75}, 0, "f2 0f 11 4c 24 XX : movsd QWORD PTR [rsp + XX], xmm1"},
+ { 6, {0xF2, 0x0f, 0x11, 0x54, 0x24, 0x75}, 0, "f2 0f 11 54 24 XX : movsd QWORD PTR [rsp + XX], xmm2"},
+ { 6, {0xF2, 0x0f, 0x11, 0x5c, 0x24, 0x75}, 0, "f2 0f 11 5c 24 XX : movsd QWORD PTR [rsp + XX], xmm3"},
+ { 6, {0xF2, 0x0f, 0x11, 0x64, 0x24, 0x75}, 0, "f2 0f 11 64 24 XX : movsd QWORD PTR [rsp + XX], xmm4"},
+ { 7, {0x48, 0x81, 0xec, 0x73, 0x74, 0x75, 0x76}, 0, "48 81 EC XX XX XX XX : sub rsp, XXXXXXXX"},
+ { 7, {0x48, 0x89, 0x0d, 0x73, 0x74, 0x75, 0x76}, 3, "48 89 0d XX XX XX XX : mov QWORD PTR [rip + XXXXXXXX], rcx"},
+ { 7, {0x48, 0x89, 0x15, 0x73, 0x74, 0x75, 0x76}, 3, "48 89 15 XX XX XX XX : mov QWORD PTR [rip + XXXXXXXX], rdx"},
+ { 7, {0x48, 0x8b, 0x05, 0x73, 0x74, 0x75, 0x76}, 3, "48 8b 05 XX XX XX XX : mov rax, QWORD PTR [rip + XXXXXXXX]"},
+ { 7, {0x48, 0x8d, 0x05, 0x73, 0x74, 0x75, 0x76}, 3, "48 8d 05 XX XX XX XX : lea rax, QWORD PTR [rip + XXXXXXXX]"},
+ { 7, {0x48, 0xff, 0x25, 0x73, 0x74, 0x75, 0x76}, 3, "48 ff 25 XX XX XX XX : rex.W jmp QWORD PTR [rip + XXXXXXXX]"},
+ { 7, {0x4C, 0x8D, 0x15, 0x73, 0x74, 0x75, 0x76}, 3, "4c 8d 15 XX XX XX XX : lea r10, [rip + XX]"},
+ { 7, {0x81, 0x78, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "81 78 YY XX XX XX XX : cmp DWORD PTR [rax+YY], XX XX XX XX"},
+ { 7, {0x81, 0x79, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "81 79 YY XX XX XX XX : cmp dword ptr [rcx+YY], XX XX XX XX"},
+ { 7, {0x81, 0x7A, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "81 7A YY XX XX XX XX : cmp DWORD PTR [rdx+YY], XX XX XX XX"},
+ { 7, {0x81, 0x7B, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "81 7B YY XX XX XX XX : cmp DWORD PTR [rbx+YY], XX XX XX XX"},
+ { 7, {0x81, 0x7D, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "81 7D YY XX XX XX XX : cmp DWORD PTR [rbp+YY], XX XX XX XX"},
+ { 7, {0x81, 0x7E, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "81 7E YY XX XX XX XX : cmp DWORD PTR [rsi+YY], XX XX XX XX"},
+ { 8, {0x41, 0x81, 0x78, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 78 XX YY YY YY YY : cmp DWORD PTR [r8+YY], XX XX XX XX"},
+ { 8, {0x41, 0x81, 0x79, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 79 XX YY YY YY YY : cmp DWORD PTR [r9+YY], XX XX XX XX"},
+ { 8, {0x41, 0x81, 0x7a, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7a XX YY YY YY YY : cmp DWORD PTR [r10+YY], XX XX XX XX"},
+ { 8, {0x41, 0x81, 0x7b, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7b XX YY YY YY YY : cmp DWORD PTR [r11+YY], XX XX XX XX"},
+ { 8, {0x41, 0x81, 0x7d, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7d XX YY YY YY YY : cmp DWORD PTR [r13+YY], XX XX XX XX"},
+ { 8, {0x41, 0x81, 0x7e, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7e XX YY YY YY YY : cmp DWORD PTR [r14+YY], XX XX XX XX"},
+ { 8, {0x41, 0x81, 0x7f, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7f YY XX XX XX XX : cmp DWORD PTR [r15+YY], XX XX XX XX"},
+ { 8, {0x81, 0x7c, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "81 7c 24 YY XX XX XX XX : cmp DWORD PTR [rsp+YY], XX XX XX XX"},
+ { 8, {0xc7, 0x44, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "C7 44 24 XX YY YY YY YY : mov dword ptr [rsp + XX], YYYYYYYY"},
+ { 9, {0xA1, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "A1 XX XX XX XX XX XX XX XX : movabs eax, dword ptr ds:[XXXXXXXX]"},
+#else
+ // sorted list
+ { 3, {0x8B, 0x45, 0x72}, 0, "8B 45 XX : mov eax, dword ptr [ebp + XX]"},
+ { 3, {0x8B, 0x5D, 0x72}, 0, "8B 5D XX : mov ebx, dword ptr [ebp + XX]"},
+ { 3, {0x8B, 0x75, 0x72}, 0, "8B 75 XX : mov esi, dword ptr [ebp + XX]"},
+ { 3, {0x8B, 0x7D, 0x72}, 0, "8B 7D XX : mov edi, dword ptr [ebp + XX]"},
+ { 3, {0xFF, 0x75, 0x72}, 0, "FF 75 XX : push dword ptr [ebp + XX]"},
+ { 4, {0x83, 0x7D, 0x72, 0x73}, 0, "83 7D XX YY : cmp dword ptr [ebp + XX], YY"},
+ { 4, {0x8A, 0x44, 0x24, 0x73}, 0, "8A 44 24 XX : mov eal, dword ptr [esp + XX]"},
+ { 4, {0x8B, 0x44, 0x24, 0x73}, 0, "8B 44 24 XX : mov eax, dword ptr [esp + XX]"},
+ { 4, {0x8B, 0x4C, 0x24, 0x73}, 0, "8B 4C 24 XX : mov ecx, dword ptr [esp + XX]"},
+ { 4, {0x8B, 0x54, 0x24, 0x73}, 0, "8B 54 24 XX : mov edx, dword ptr [esp + XX]"},
+ { 4, {0x8B, 0x5C, 0x24, 0x73}, 0, "8B 5C 24 XX : mov ebx, dword ptr [esp + XX]"},
+ { 4, {0x8B, 0x6C, 0x24, 0x73}, 0, "8B 6C 24 XX : mov ebp, dword ptr [esp + XX]"},
+ { 4, {0x8B, 0x74, 0x24, 0x73}, 0, "8B 74 24 XX : mov esi, dword ptr [esp + XX]"},
+ { 4, {0x8B, 0x7C, 0x24, 0x73}, 0, "8B 7C 24 XX : mov edi, dword ptr [esp + XX]"},
+ { 5, {0x0F, 0xB6, 0x44, 0x24, 0x74}, 0, "0F B6 44 24 XX : movzx eax, byte ptr [esp + XX]"},
+ { 5, {0xA1, 0x71, 0x72, 0x73, 0x74}, 0, "A1 XX XX XX XX : mov eax, dword ptr ds:[XXXXXXXX]"},
+ { 6, {0xF7, 0xC1, 0x72, 0x73, 0x74, 0x75}, 0, "F7 C1 XX YY ZZ WW : test ecx, WWZZYYXX"},
+ { 7, {0x83, 0x3D, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "83 3D XX YY ZZ WW TT : cmp TT, WWZZYYXX"},
+#endif
+ // clang-format on
};
std::string dumpInstruction(unsigned arrayIndex,
>From 60b0d0792d7135e35b2abb44ff953b243102ba20 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 22:00:06 +0100
Subject: [PATCH 09/20] [win/asan] GetInstructionSize: Fix `41 81 7c ...` to
return 9.
---
compiler-rt/lib/interception/interception_win.cpp | 5 ++++-
compiler-rt/lib/interception/tests/interception_win_test.cpp | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 93886e79fd88c8..cfa38fe702ebcd 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -808,7 +808,6 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x798141: // 41 81 79 XX YY YY YY YY : cmp DWORD PTR [r9+YY], XX XX XX XX
case 0x7a8141: // 41 81 7a XX YY YY YY YY : cmp DWORD PTR [r10+YY], XX XX XX XX
case 0x7b8141: // 41 81 7b XX YY YY YY YY : cmp DWORD PTR [r11+YY], XX XX XX XX
- case 0x7c8141: // 41 81 7c XX YY YY YY YY : cmp DWORD PTR [r12+YY], XX XX XX XX
case 0x7d8141: // 41 81 7d XX YY YY YY YY : cmp DWORD PTR [r13+YY], XX XX XX XX
case 0x7e8141: // 41 81 7e XX YY YY YY YY : cmp DWORD PTR [r14+YY], XX XX XX XX
case 0x7f8141: // 41 81 7f YY XX XX XX XX : cmp DWORD PTR [r15+YY], XX XX XX XX
@@ -835,6 +834,10 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x2444c7: // C7 44 24 XX YY YY YY YY
// mov dword ptr [rsp + XX], YYYYYYYY
return 8;
+
+ case 0x7c8141: // 41 81 7c ZZ YY XX XX XX XX
+ // cmp DWORD PTR [reg+reg*n+YY], XX XX XX XX
+ return 9;
}
switch (*(u32*)(address)) {
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 55df15774da378..0f6cd64bc37eff 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -1014,6 +1014,7 @@ const struct InstructionSizeData {
{ 8, {0x41, 0x81, 0x7f, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7f YY XX XX XX XX : cmp DWORD PTR [r15+YY], XX XX XX XX"},
{ 8, {0x81, 0x7c, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "81 7c 24 YY XX XX XX XX : cmp DWORD PTR [rsp+YY], XX XX XX XX"},
{ 8, {0xc7, 0x44, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "C7 44 24 XX YY YY YY YY : mov dword ptr [rsp + XX], YYYYYYYY"},
+ { 9, {0x41, 0x81, 0x7c, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "41 81 7c ZZ YY XX XX XX XX : cmp DWORD PTR [reg+reg*n+YY], XX XX XX XX"},
{ 9, {0xA1, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "A1 XX XX XX XX XX XX XX XX : movabs eax, dword ptr ds:[XXXXXXXX]"},
#else
// sorted list
>From 02c48987d811f363895a83a12da5936df0fbd1eb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 22:00:35 +0100
Subject: [PATCH 10/20] [win/asan] GetInstructionSize: Make `F6 C1 XX` a
generic entry.
---
compiler-rt/lib/interception/interception_win.cpp | 6 ++++--
.../lib/interception/tests/interception_win_test.cpp | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index cfa38fe702ebcd..b0fb263b62f156 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -634,6 +634,9 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xD284: // 84 D2 : test dl,dl
return 2;
+ case 0xC1F6: // F6 C1 XX : test cl, XX
+ return 3;
+
// Cannot overwrite control-instruction. Return 0 to indicate failure.
case 0x25FF: // FF 25 XX YY ZZ WW : jmp dword ptr ds:[WWZZYYXX]
return 0;
@@ -723,8 +726,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
return 7;
}
- switch (0x00FFFFFF & *(u32*)address) {
- case 0x07c1f6: // f6 c1 07 : test cl, 0x7
+ switch (0x00FFFFFF & *(u32 *)address) {
case 0x10b70f: // 0f b7 10 : movzx edx, WORD PTR [rax]
case 0xc00b4d: // 4d 0b c0 : or r8, r8
case 0xc03345: // 45 33 c0 : xor r8d, r8d
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 0f6cd64bc37eff..ba9c88d4baada1 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -952,6 +952,7 @@ const struct InstructionSizeData {
{ 3, {0x4d, 0x85, 0xed}, 0, "4d 85 ed : test r13, r13"},
{ 3, {0x4d, 0x85, 0xf6}, 0, "4d 85 f6 : test r14, r14"},
{ 3, {0x4d, 0x85, 0xff}, 0, "4d 85 ff : test r15, r15"},
+ { 3, {0xf6, 0xc1, 0x72}, 0, "f6 c1 XX : test cl, XX"},
{ 4, {0x44, 0x0f, 0xb6, 0x1a}, 0, "44 0f b6 1a : movzx r11d, BYTE PTR [rdx]"},
{ 4, {0x44, 0x8d, 0x42, 0x73}, 0, "44 8d 42 XX : lea r8d , [rdx + XX]"},
{ 4, {0x48, 0x83, 0xec, 0x73}, 0, "48 83 ec XX : sub rsp, XX"},
>From e9487203bf132b9a6bf85cd3e9bda8227a4af7e4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 22:01:06 +0100
Subject: [PATCH 11/20] [win/asan] GetInstructionSize: Make `83 EC XX` a
generic entry.
---
compiler-rt/lib/interception/interception_win.cpp | 4 +---
compiler-rt/lib/interception/tests/interception_win_test.cpp | 1 +
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index b0fb263b62f156..4afc74933a33bc 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -634,6 +634,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xD284: // 84 D2 : test dl,dl
return 2;
+ case 0xEC83: // 83 EC XX : sub esp, XX
case 0xC1F6: // F6 C1 XX : test cl, XX
return 3;
@@ -644,8 +645,6 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
switch (0x00FFFFFF & *(u32*)address) {
case 0xF8E483: // 83 E4 F8 : and esp, 0xFFFFFFF8
- case 0x64EC83: // 83 EC 64 : sub esp, 64h
- return 3;
case 0x24A48D: // 8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]
return 7;
}
@@ -873,7 +872,6 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x5D8B: // 8B 5D XX : mov ebx, dword ptr [ebp + XX]
case 0x7D8B: // 8B 7D XX : mov edi, dword ptr [ebp + XX]
case 0x758B: // 8B 75 XX : mov esi, dword ptr [ebp + XX]
- case 0xEC83: // 83 EC XX : sub esp, XX
case 0x75FF: // FF 75 XX : push dword ptr [ebp + XX]
return 3;
case 0xC1F7: // F7 C1 XX YY ZZ WW : test ecx, WWZZYYXX
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index ba9c88d4baada1..f8fa55ec90100c 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -877,6 +877,7 @@ const struct InstructionSizeData {
{ 2, {0x8B, 0xC1}, 0, "8B C1 : mov eax, ecx"},
{ 2, {0x8B, 0xEC}, 0, "8B EC : mov ebp, esp"},
{ 2, {0x8B, 0xFF}, 0, "8B FF : mov edi, edi"},
+ { 3, {0x83, 0xEC, 0x72}, 0, "83 EC XX : sub esp, XX"},
{ 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"},
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
{ 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
>From 9607def77d2547cb5b047b36569dae6311335741 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 22:08:46 +0100
Subject: [PATCH 12/20] [win/asan] GetInstructionSize: Make `83 E4 XX` a
generic entry.
---
compiler-rt/lib/interception/interception_win.cpp | 5 ++---
compiler-rt/lib/interception/tests/interception_win_test.cpp | 1 +
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 4afc74933a33bc..a5897274521e92 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -634,6 +634,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xD284: // 84 D2 : test dl,dl
return 2;
+ case 0xE483: // 83 E4 XX : and esp, XX
case 0xEC83: // 83 EC XX : sub esp, XX
case 0xC1F6: // F6 C1 XX : test cl, XX
return 3;
@@ -643,8 +644,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
return 0;
}
- switch (0x00FFFFFF & *(u32*)address) {
- case 0xF8E483: // 83 E4 F8 : and esp, 0xFFFFFFF8
+ switch (0x00FFFFFF & *(u32 *)address) {
case 0x24A48D: // 8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]
return 7;
}
@@ -773,7 +773,6 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xdb8548: // 48 85 db : test rbx, rbx
case 0xdb854d: // 4d 85 db : test r11, r11
case 0xdc8b4c: // 4c 8b dc : mov r11, rsp
- case 0xe0e483: // 83 e4 e0 : and esp, 0xFFFFFFE0
case 0xe48548: // 48 85 e4 : test rsp, rsp
case 0xe4854d: // 4d 85 e4 : test r12, r12
case 0xe58948: // 48 89 e5 : mov rbp, rsp
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index f8fa55ec90100c..51c3d762553c5d 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -877,6 +877,7 @@ const struct InstructionSizeData {
{ 2, {0x8B, 0xC1}, 0, "8B C1 : mov eax, ecx"},
{ 2, {0x8B, 0xEC}, 0, "8B EC : mov ebp, esp"},
{ 2, {0x8B, 0xFF}, 0, "8B FF : mov edi, edi"},
+ { 3, {0x83, 0xE4, 0x72}, 0, "83 E4 XX : and esp, XX"},
{ 3, {0x83, 0xEC, 0x72}, 0, "83 EC XX : sub esp, XX"},
{ 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"},
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
>From 51ef546ff73c47505bc59f6cd6f5a5f8c4133527 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sun, 1 Dec 2024 10:56:29 +0100
Subject: [PATCH 13/20] [win/asan] GetInstructionSize: Fix `8D A4 24 ...` to
return rel_offset=3.
---
compiler-rt/lib/interception/interception_win.cpp | 2 ++
compiler-rt/lib/interception/tests/interception_win_test.cpp | 1 +
2 files changed, 3 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index a5897274521e92..89f75e8fd2a7b9 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -646,6 +646,8 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
switch (0x00FFFFFF & *(u32 *)address) {
case 0x24A48D: // 8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]
+ if (rel_offset)
+ *rel_offset = 3;
return 7;
}
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 51c3d762553c5d..74fe931e60be60 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -883,6 +883,7 @@ const struct InstructionSizeData {
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
{ 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
{ 5, {0xb8, 0x71, 0x72, 0x73, 0x74}, 0, "b8 XX XX XX XX : mov eax, XX XX XX XX"},
+ { 7, {0x8D, 0xA4, 0x24, 0x73, 0x74, 0x75, 0x76}, 3, "8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]"},
#if SANITIZER_WINDOWS_x64
// sorted list
{ 2, {0x40, 0x50}, 0, "40 50 : push rax"},
>From 4e4869a66c0f8c79679eae0a89c210b1dd2548d2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Wed, 6 Nov 2024 22:58:53 +0100
Subject: [PATCH 14/20] [win/asan] GetInstructionSize: Support some more 2 byte
instructions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
Related: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
---
compiler-rt/lib/interception/interception_win.cpp | 5 +++++
compiler-rt/lib/interception/tests/interception_win_test.cpp | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 89f75e8fd2a7b9..1907dbd806e052 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -624,12 +624,17 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xFF8B: // 8B FF : mov edi, edi
case 0xEC8B: // 8B EC : mov ebp, esp
case 0xc889: // 89 C8 : mov eax, ecx
+ case 0xD189: // 89 D1 : mov ecx, edx
case 0xE589: // 89 E5 : mov ebp, esp
case 0xC18B: // 8B C1 : mov eax, ecx
+ case 0xC031: // 31 C0 : xor eax, eax
+ case 0xC931: // 31 C9 : xor ecx, ecx
+ case 0xD231: // 31 D2 : xor edx, edx
case 0xC033: // 33 C0 : xor eax, eax
case 0xC933: // 33 C9 : xor ecx, ecx
case 0xD233: // 33 D2 : xor edx, edx
case 0xDB84: // 84 DB : test bl,bl
+ case 0xC084: // 84 C0 : test al,al
case 0xC984: // 84 C9 : test cl,cl
case 0xD284: // 84 D2 : test dl,dl
return 2;
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 74fe931e60be60..3f80df996b5b67 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -864,13 +864,18 @@ const struct InstructionSizeData {
{ 1, {0x90}, 0, "90 : nop"},
{ 1, {0xC3}, 0, "C3 : ret (for small/empty function interception"},
{ 1, {0xCC}, 0, "CC : int 3 i.e. registering weak functions)"},
+ { 2, {0x31, 0xC0}, 0, "31 C0 : xor eax, eax"},
+ { 2, {0x31, 0xC9}, 0, "31 C9 : xor ecx, ecx"},
+ { 2, {0x31, 0xD2}, 0, "31 D2 : xor edx, edx"},
{ 2, {0x33, 0xC0}, 0, "33 C0 : xor eax, eax"},
{ 2, {0x33, 0xC9}, 0, "33 C9 : xor ecx, ecx"},
{ 2, {0x33, 0xD2}, 0, "33 D2 : xor edx, edx"},
{ 2, {0x6A, 0x71}, 0, "6A XX : push XX"},
+ { 2, {0x84, 0xC0}, 0, "84 C0 : test al,al"},
{ 2, {0x84, 0xC9}, 0, "84 C9 : test cl,cl"},
{ 2, {0x84, 0xD2}, 0, "84 D2 : test dl,dl"},
{ 2, {0x84, 0xDB}, 0, "84 DB : test bl,bl"},
+ { 2, {0x89, 0xD1}, 0, "89 D1 : mov ecx, edx"},
{ 2, {0x89, 0xE5}, 0, "89 E5 : mov ebp, esp"},
{ 2, {0x89, 0xc8}, 0, "89 C8 : mov eax, ecx"},
{ 2, {0x8A, 0x01}, 0, "8A 01 : mov al, byte ptr [ecx]"},
>From 0021083421ba039fb111780f2acd901813aea6d0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 00:00:39 +0100
Subject: [PATCH 15/20] [win/asan] GetInstructionSize: Support some more 3 byte
instructions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
Related: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
---
.../lib/interception/interception_win.cpp | 25 +++++++++++++++++++
.../tests/interception_win_test.cpp | 25 +++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 1907dbd806e052..10af3a0c8abf95 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -639,6 +639,10 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xD284: // 84 D2 : test dl,dl
return 2;
+ case 0x3980: // 80 39 XX : cmp BYTE PTR [rcx], XX
+ case 0x4D8B: // 8B 4D XX : mov XX(%ebp), ecx
+ case 0x558B: // 8B 55 XX : mov XX(%ebp), edx
+ case 0x758B: // 8B 75 XX : mov XX(%ebp), esp
case 0xE483: // 83 E4 XX : and esp, XX
case 0xEC83: // 83 EC XX : sub esp, XX
case 0xC1F6: // F6 C1 XX : test cl, XX
@@ -747,6 +751,9 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xc1ff48: // 48 ff c1 : inc rcx
case 0xc1ff49: // 49 ff c1 : inc r9
case 0xc28b41: // 41 8b c2 : mov eax, r10d
+ case 0x01b60f: // 0f b6 01 : movzx eax, BYTE PTR [rcx]
+ case 0x09b60f: // 0f b6 09 : movzx ecx, BYTE PTR [rcx]
+ case 0x11b60f: // 0f b6 11 : movzx edx, BYTE PTR [rcx]
case 0xc2b60f: // 0f b6 c2 : movzx eax, dl
case 0xc2ff48: // 48 ff c2 : inc rdx
case 0xc2ff49: // 49 ff c2 : inc r10
@@ -765,6 +772,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xc98548: // 48 85 c9 : test rcx, rcx
case 0xc9854d: // 4d 85 c9 : test r9, r9
case 0xc98b4c: // 4c 8b c9 : mov r9, rcx
+ case 0xd12948: // 48 29 d1 : sub rcx, rdx
case 0xca2b48: // 48 2b ca : sub rcx, rdx
case 0xca3b48: // 48 3b ca : cmp rcx, rdx
case 0xd12b48: // 48 2b d1 : sub rdx, rcx
@@ -774,16 +782,33 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xd2854d: // 4d 85 d2 : test r10, r10
case 0xd28b4c: // 4c 8b d2 : mov r10, rdx
case 0xd2b60f: // 0f b6 d2 : movzx edx, dl
+ case 0xd2be0f: // 0f be d2 : movsx edx, dl
case 0xd98b4c: // 4c 8b d9 : mov r11, rcx
case 0xd9f748: // 48 f7 d9 : neg rcx
+ case 0xc03145: // 45 31 c0 : xor r8d,r8d
+ case 0xc93145: // 45 31 c9 : xor r9d,r9d
case 0xdb3345: // 45 33 db : xor r11d, r11d
+ case 0xc08445: // 45 84 c0 : test r8b,r8b
+ case 0xd28445: // 45 84 d2 : test r10b,r10b
case 0xdb8548: // 48 85 db : test rbx, rbx
case 0xdb854d: // 4d 85 db : test r11, r11
case 0xdc8b4c: // 4c 8b dc : mov r11, rsp
case 0xe48548: // 48 85 e4 : test rsp, rsp
case 0xe4854d: // 4d 85 e4 : test r12, r12
+ case 0xc88948: // 48 89 c8 : mov rax,rcx
+ case 0xcb8948: // 48 89 cb : mov rbx,rcx
+ case 0xd08948: // 48 89 d0 : mov rax,rdx
+ case 0xd18948: // 48 89 d1 : mov rcx,rdx
+ case 0xd38948: // 48 89 d3 : mov rbx,rdx
case 0xe58948: // 48 89 e5 : mov rbp, rsp
case 0xed8548: // 48 85 ed : test rbp, rbp
+ case 0xc88949: // 49 89 c8 : mov r8, rcx
+ case 0xc98949: // 49 89 c9 : mov r9, rcx
+ case 0xca8949: // 49 89 ca : mov r10,rcx
+ case 0xd08949: // 49 89 d0 : mov r8, rdx
+ case 0xd18949: // 49 89 d1 : mov r9, rdx
+ case 0xd28949: // 49 89 d2 : mov r10, rdx
+ case 0xd38949: // 49 89 d3 : mov r11, rdx
case 0xed854d: // 4d 85 ed : test r13, r13
case 0xf6854d: // 4d 85 f6 : test r14, r14
case 0xff854d: // 4d 85 ff : test r15, r15
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 3f80df996b5b67..a8ba8c8f721e2e 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -882,8 +882,12 @@ const struct InstructionSizeData {
{ 2, {0x8B, 0xC1}, 0, "8B C1 : mov eax, ecx"},
{ 2, {0x8B, 0xEC}, 0, "8B EC : mov ebp, esp"},
{ 2, {0x8B, 0xFF}, 0, "8B FF : mov edi, edi"},
+ { 3, {0x80, 0x39, 0x72}, 0, "80 39 XX : cmp BYTE PTR [rcx], XX"},
{ 3, {0x83, 0xE4, 0x72}, 0, "83 E4 XX : and esp, XX"},
{ 3, {0x83, 0xEC, 0x72}, 0, "83 EC XX : sub esp, XX"},
+ { 3, {0x8B, 0x4D, 0x72}, 0, "8B 4D XX : mov XX(%ebp), ecx"},
+ { 3, {0x8B, 0x55, 0x72}, 0, "8B 55 XX : mov XX(%ebp), edx"},
+ { 3, {0x8B, 0x75, 0x72}, 0, "8B 75 XX : mov XX(%ebp), esp"},
{ 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"},
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
{ 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
@@ -906,17 +910,26 @@ const struct InstructionSizeData {
{ 2, {0x66, 0x90}, 0, "66 90 : Two-byte NOP"},
{ 2, {0x84, 0xc0}, 0, "84 c0 : test al, al"},
{ 2, {0x8a, 0x01}, 0, "8a 01 : mov al, byte ptr [rcx]"},
+ { 3, {0x0f, 0xb6, 0x01}, 0, "0f b6 01 : movzx eax, BYTE PTR [rcx]"},
+ { 3, {0x0f, 0xb6, 0x09}, 0, "0f b6 09 : movzx ecx, BYTE PTR [rcx]"},
+ { 3, {0x0f, 0xb6, 0x11}, 0, "0f b6 11 : movzx edx, BYTE PTR [rcx]"},
{ 3, {0x0f, 0xb6, 0xc2}, 0, "0f b6 c2 : movzx eax, dl"},
{ 3, {0x0f, 0xb6, 0xd2}, 0, "0f b6 d2 : movzx edx, dl"},
{ 3, {0x0f, 0xb7, 0x10}, 0, "0f b7 10 : movzx edx, WORD PTR [rax]"},
+ { 3, {0x0f, 0xbe, 0xd2}, 0, "0f be d2 : movsx edx, dl"},
{ 3, {0x41, 0x8b, 0xc0}, 0, "41 8b c0 : mov eax, r8d"},
{ 3, {0x41, 0x8b, 0xc1}, 0, "41 8b c1 : mov eax, r9d"},
{ 3, {0x41, 0x8b, 0xc2}, 0, "41 8b c2 : mov eax, r10d"},
{ 3, {0x41, 0x8b, 0xc3}, 0, "41 8b c3 : mov eax, r11d"},
{ 3, {0x41, 0x8b, 0xc4}, 0, "41 8b c4 : mov eax, r12d"},
+ { 3, {0x45, 0x31, 0xc0}, 0, "45 31 c0 : xor r8d,r8d"},
+ { 3, {0x45, 0x31, 0xc9}, 0, "45 31 c9 : xor r9d,r9d"},
{ 3, {0x45, 0x33, 0xc0}, 0, "45 33 c0 : xor r8d, r8d"},
{ 3, {0x45, 0x33, 0xc9}, 0, "45 33 c9 : xor r9d, r9d"},
{ 3, {0x45, 0x33, 0xdb}, 0, "45 33 db : xor r11d, r11d"},
+ { 3, {0x45, 0x84, 0xc0}, 0, "45 84 c0 : test r8b,r8b"},
+ { 3, {0x45, 0x84, 0xd2}, 0, "45 84 d2 : test r10b,r10b"},
+ { 3, {0x48, 0x29, 0xd1}, 0, "48 29 d1 : sub rcx, rdx"},
{ 3, {0x48, 0x2b, 0xca}, 0, "48 2b ca : sub rcx, rdx"},
{ 3, {0x48, 0x2b, 0xd1}, 0, "48 2b d1 : sub rdx, rcx"},
{ 3, {0x48, 0x3b, 0xca}, 0, "48 3b ca : cmp rcx, rdx"},
@@ -926,6 +939,11 @@ const struct InstructionSizeData {
{ 3, {0x48, 0x85, 0xdb}, 0, "48 85 db : test rbx, rbx"},
{ 3, {0x48, 0x85, 0xe4}, 0, "48 85 e4 : test rsp, rsp"},
{ 3, {0x48, 0x85, 0xed}, 0, "48 85 ed : test rbp, rbp"},
+ { 3, {0x48, 0x89, 0xc8}, 0, "48 89 c8 : mov rax,rcx"},
+ { 3, {0x48, 0x89, 0xcb}, 0, "48 89 cb : mov rbx,rcx"},
+ { 3, {0x48, 0x89, 0xd0}, 0, "48 89 d0 : mov rax,rdx"},
+ { 3, {0x48, 0x89, 0xd1}, 0, "48 89 d1 : mov rcx,rdx"},
+ { 3, {0x48, 0x89, 0xd3}, 0, "48 89 d3 : mov rbx,rdx"},
{ 3, {0x48, 0x89, 0xe5}, 0, "48 89 e5 : mov rbp, rsp"},
{ 3, {0x48, 0x8b, 0xc1}, 0, "48 8b c1 : mov rax, rcx"},
{ 3, {0x48, 0x8b, 0xc4}, 0, "48 8b c4 : mov rax, rsp"},
@@ -937,6 +955,13 @@ const struct InstructionSizeData {
{ 3, {0x48, 0xff, 0xc3}, 0, "48 ff c3 : inc rbx"},
{ 3, {0x48, 0xff, 0xc6}, 0, "48 ff c6 : inc rsi"},
{ 3, {0x48, 0xff, 0xc7}, 0, "48 ff c7 : inc rdi"},
+ { 3, {0x49, 0x89, 0xc8}, 0, "49 89 c8 : mov r8, rcx"},
+ { 3, {0x49, 0x89, 0xc9}, 0, "49 89 c9 : mov r9, rcx"},
+ { 3, {0x49, 0x89, 0xca}, 0, "49 89 ca : mov r10,rcx"},
+ { 3, {0x49, 0x89, 0xd0}, 0, "49 89 d0 : mov r8, rdx"},
+ { 3, {0x49, 0x89, 0xd1}, 0, "49 89 d1 : mov r9, rdx"},
+ { 3, {0x49, 0x89, 0xd2}, 0, "49 89 d2 : mov r10, rdx"},
+ { 3, {0x49, 0x89, 0xd3}, 0, "49 89 d3 : mov r11, rdx"},
{ 3, {0x49, 0xff, 0xc0}, 0, "49 ff c0 : inc r8"},
{ 3, {0x49, 0xff, 0xc1}, 0, "49 ff c1 : inc r9"},
{ 3, {0x49, 0xff, 0xc2}, 0, "49 ff c2 : inc r10"},
>From 7609c96af9c5d874bc4a91fb7722052baeb34496 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 23:47:45 +0100
Subject: [PATCH 16/20] [win/asan] GetInstructionSize: Support some more 4 byte
instructions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
Related: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
---
compiler-rt/lib/interception/interception_win.cpp | 10 ++++++++++
.../lib/interception/tests/interception_win_test.cpp | 9 +++++++++
2 files changed, 19 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 10af3a0c8abf95..a661f578083c79 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -654,6 +654,8 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
}
switch (0x00FFFFFF & *(u32 *)address) {
+ case 0x244C8D: // 8D 4C 24 XX : lea ecx, [esp + XX]
+ return 4;
case 0x24A48D: // 8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]
if (rel_offset)
*rel_offset = 3;
@@ -819,6 +821,8 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x588948: // 48 89 58 XX : mov QWORD PTR[rax + XX], rbx
case 0xec8348: // 48 83 ec XX : sub rsp, XX
case 0xf88349: // 49 83 f8 XX : cmp r8, XX
+ case 0x148d4e: // 4e 8d 14 XX : lea r10, [rcx+r8*XX]
+ case 0x398366: // 66 83 39 XX : cmp WORD PTR [rcx], XX
return 4;
case 0x246483: // 83 64 24 XX YY : and DWORD PTR [rsp+XX], YY
@@ -873,7 +877,13 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
}
switch (*(u32*)(address)) {
+ case 0x01b60f44: // 44 0f b6 01 : movzx r8d, BYTE PTR [rcx]
+ case 0x09b60f44: // 44 0f b6 09 : movzx r9d, BYTE PTR [rcx]
+ case 0x0ab60f44: // 44 0f b6 0a : movzx r8d, BYTE PTR [rdx]
+ case 0x11b60f44: // 44 0f b6 11 : movzx r10d, BYTE PTR [rcx]
case 0x1ab60f44: // 44 0f b6 1a : movzx r11d, BYTE PTR [rdx]
+ case 0x11048d4c: // 4c 8d 04 11 : lea r8,[rcx+rdx*1]
+ case 0xff488d49: // 49 8d 48 ff : lea rcx,[r8-0x1]
return 4;
case 0x24448b48: // 48 8b 44 24 XX : mov rax, QWORD ptr [rsp + XX]
case 0x246c8948: // 48 89 6C 24 XX : mov QWORD ptr [rsp + XX], rbp
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index a8ba8c8f721e2e..fe84dd1b664bd6 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -889,6 +889,7 @@ const struct InstructionSizeData {
{ 3, {0x8B, 0x55, 0x72}, 0, "8B 55 XX : mov XX(%ebp), edx"},
{ 3, {0x8B, 0x75, 0x72}, 0, "8B 75 XX : mov XX(%ebp), esp"},
{ 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"},
+ { 4, {0x8D, 0x4C, 0x24}, 0, "8D 4C 24 XX : lea ecx, [esp + XX]"},
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
{ 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
{ 5, {0xb8, 0x71, 0x72, 0x73, 0x74}, 0, "b8 XX XX XX XX : mov eax, XX XX XX XX"},
@@ -986,11 +987,19 @@ const struct InstructionSizeData {
{ 3, {0x4d, 0x85, 0xf6}, 0, "4d 85 f6 : test r14, r14"},
{ 3, {0x4d, 0x85, 0xff}, 0, "4d 85 ff : test r15, r15"},
{ 3, {0xf6, 0xc1, 0x72}, 0, "f6 c1 XX : test cl, XX"},
+ { 4, {0x44, 0x0f, 0xb6, 0x01}, 0, "44 0f b6 01 : movzx r8d, BYTE PTR [rcx]"},
+ { 4, {0x44, 0x0f, 0xb6, 0x09}, 0, "44 0f b6 09 : movzx r9d, BYTE PTR [rcx]"},
+ { 4, {0x44, 0x0f, 0xb6, 0x0a}, 0, "44 0f b6 0a : movzx r8d, BYTE PTR [rdx]"},
+ { 4, {0x44, 0x0f, 0xb6, 0x11}, 0, "44 0f b6 11 : movzx r10d, BYTE PTR [rcx]"},
{ 4, {0x44, 0x0f, 0xb6, 0x1a}, 0, "44 0f b6 1a : movzx r11d, BYTE PTR [rdx]"},
{ 4, {0x44, 0x8d, 0x42, 0x73}, 0, "44 8d 42 XX : lea r8d , [rdx + XX]"},
{ 4, {0x48, 0x83, 0xec, 0x73}, 0, "48 83 ec XX : sub rsp, XX"},
{ 4, {0x48, 0x89, 0x58, 0x73}, 0, "48 89 58 XX : mov QWORD PTR[rax + XX], rbx"},
{ 4, {0x49, 0x83, 0xf8, 0x73}, 0, "49 83 f8 XX : cmp r8, XX"},
+ { 4, {0x49, 0x8d, 0x48, 0xff}, 0, "49 8d 48 ff : lea rcx,[r8-0x1]"},
+ { 4, {0x4c, 0x8d, 0x04, 0x11}, 0, "4c 8d 04 11 : lea r8,[rcx+rdx*1]"},
+ { 4, {0x4e, 0x8d, 0x14, 0x73}, 0, "4e 8d 14 XX : lea r10, [rcx+r8*XX]"},
+ { 4, {0x66, 0x83, 0x39, 0x73}, 0, "66 83 39 XX : cmp WORD PTR [rcx], XX"},
{ 4, {0x80, 0x78, 0x72, 0x73}, 0, "80 78 YY XX : cmp BYTE PTR [rax+YY], XX"},
{ 4, {0x80, 0x79, 0x72, 0x73}, 0, "80 79 YY XX : cmp BYTE ptr [rcx+YY], XX"},
{ 4, {0x80, 0x7A, 0x72, 0x73}, 0, "80 7A YY XX : cmp BYTE PTR [rdx+YY], XX"},
>From 6d6daf94d0ad7ebf2dcbd98749d5aaf0cfc750a9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 00:03:02 +0100
Subject: [PATCH 17/20] [win/asan] GetInstructionSize: Support some more 5 byte
instructions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
Related: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
---
compiler-rt/lib/interception/interception_win.cpp | 7 +++++++
.../lib/interception/tests/interception_win_test.cpp | 3 +++
2 files changed, 10 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index a661f578083c79..0f91d6048a400b 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -594,6 +594,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xb8: // b8 XX XX XX XX : mov eax, XX XX XX XX
case 0xB9: // b9 XX XX XX XX : mov ecx, XX XX XX XX
+ case 0xBA: // ba XX XX XX XX : mov edx, XX XX XX XX
return 5;
// Cannot overwrite control-instruction. Return 0 to indicate failure.
@@ -902,6 +903,12 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
return 6;
}
+ switch (0xFFFFFFFFFFULL & *(u64*)(address)) {
+ case 0xC07E0F4866: // 66 48 0F 7E C0 : movq rax,xmm0 (for wine fexp)
+ case 0x0000441F0F: // 0F 1F 44 00 00 : nop DWORD PTR [rax+rax*1+0x0]
+ return 5;
+ }
+
#else
switch (*(u8*)address) {
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index fe84dd1b664bd6..b2bd5621c9d526 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -892,6 +892,7 @@ const struct InstructionSizeData {
{ 4, {0x8D, 0x4C, 0x24}, 0, "8D 4C 24 XX : lea ecx, [esp + XX]"},
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
{ 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
+ { 5, {0xBA, 0x71, 0x72, 0x73, 0x74}, 0, "ba XX XX XX XX : mov edx, XX XX XX XX"},
{ 5, {0xb8, 0x71, 0x72, 0x73, 0x74}, 0, "b8 XX XX XX XX : mov eax, XX XX XX XX"},
{ 7, {0x8D, 0xA4, 0x24, 0x73, 0x74, 0x75, 0x76}, 3, "8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]"},
#if SANITIZER_WINDOWS_x64
@@ -1007,6 +1008,7 @@ const struct InstructionSizeData {
{ 4, {0x80, 0x7D, 0x72, 0x73}, 0, "80 7D YY XX : cmp BYTE PTR [rbp+YY], XX"},
{ 4, {0x80, 0x7E, 0x72, 0x73}, 0, "80 7E YY XX : cmp BYTE PTR [rsi+YY], XX"},
{ 4, {0x89, 0x54, 0x24, 0x73}, 0, "89 54 24 XX : mov DWORD PTR[rsp + XX], edx"},
+ { 5, {0x0F, 0x1F, 0x44, 0x00, 0x00}, 0, "0F 1F 44 00 00 : nop DWORD PTR [rax+rax*1+0x0]"},
{ 5, {0x44, 0x89, 0x44, 0x24, 0x74}, 0, "44 89 44 24 XX : mov DWORD PTR [rsp + XX], r8d"},
{ 5, {0x44, 0x89, 0x4c, 0x24, 0x74}, 0, "44 89 4c 24 XX : mov DWORD PTR [rsp + XX], r9d"},
{ 5, {0x48, 0x89, 0x4C, 0x24, 0x74}, 0, "48 89 4C 24 XX : mov QWORD PTR [rsp + XX], rcx"},
@@ -1019,6 +1021,7 @@ const struct InstructionSizeData {
{ 5, {0x48, 0x8d, 0x6c, 0x24, 0x74}, 0, "48 8d 6c 24 XX : lea rbp, [rsp + XX]"},
{ 5, {0x4c, 0x89, 0x44, 0x24, 0x74}, 0, "4c 89 44 24 XX : mov QWORD PTR [rsp + XX], r8"},
{ 5, {0x4c, 0x89, 0x4c, 0x24, 0x74}, 0, "4c 89 4c 24 XX : mov QWORD PTR [rsp + XX], r9"},
+ { 5, {0x66, 0x48, 0x0F, 0x7E, 0xC0}, 0, "66 48 0F 7E C0 : movq rax,xmm0 (for wine fexp)"},
{ 5, {0x83, 0x44, 0x72, 0x73, 0x74}, 0, "83 44 72 XX YY : add DWORD PTR [rdx+rsi*2+XX],YY"},
{ 5, {0x83, 0x64, 0x24, 0x73, 0x74}, 0, "83 64 24 XX YY : and DWORD PTR [rsp+XX], YY"},
{ 6, {0x48, 0x83, 0x64, 0x24, 0x74, 0x75}, 0, "48 83 64 24 XX YY : and QWORD PTR [rsp + XX], YY"},
>From 0974b902bac555742c3c09e70c9a3a25c842b2bb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 00:03:36 +0100
Subject: [PATCH 18/20] [win/asan] GetInstructionSize: Support some more 6 byte
instructions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
Related: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
---
compiler-rt/lib/interception/interception_win.cpp | 4 ++++
compiler-rt/lib/interception/tests/interception_win_test.cpp | 2 ++
2 files changed, 6 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 0f91d6048a400b..1e2357e2118093 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -649,6 +649,9 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xC1F6: // F6 C1 XX : test cl, XX
return 3;
+ case 0xEC81: // 81 EC XX XX XX XX : sub esp, XX XX XX XX
+ return 6;
+
// Cannot overwrite control-instruction. Return 0 to indicate failure.
case 0x25FF: // FF 25 XX YY ZZ WW : jmp dword ptr ds:[WWZZYYXX]
return 0;
@@ -728,6 +731,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x058B: // 8B 05 XX XX XX XX : mov eax, dword ptr [XX XX XX XX]
if (rel_offset)
*rel_offset = 2;
+ case 0xB841: // 41 B8 XX XX XX XX : mov r8d, XX XX XX XX
return 6;
case 0x7E81: // 81 7E YY XX XX XX XX cmp DWORD PTR [rsi+YY], XX XX XX XX
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index b2bd5621c9d526..f9d93161b08669 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -894,6 +894,7 @@ const struct InstructionSizeData {
{ 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
{ 5, {0xBA, 0x71, 0x72, 0x73, 0x74}, 0, "ba XX XX XX XX : mov edx, XX XX XX XX"},
{ 5, {0xb8, 0x71, 0x72, 0x73, 0x74}, 0, "b8 XX XX XX XX : mov eax, XX XX XX XX"},
+ { 6, {0x81, 0xEC, 0x72, 0x73, 0x74, 0x75}, 0, "81 EC XX XX XX XX : sub esp, XX XX XX XX"},
{ 7, {0x8D, 0xA4, 0x24, 0x73, 0x74, 0x75, 0x76}, 3, "8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]"},
#if SANITIZER_WINDOWS_x64
// sorted list
@@ -1024,6 +1025,7 @@ const struct InstructionSizeData {
{ 5, {0x66, 0x48, 0x0F, 0x7E, 0xC0}, 0, "66 48 0F 7E C0 : movq rax,xmm0 (for wine fexp)"},
{ 5, {0x83, 0x44, 0x72, 0x73, 0x74}, 0, "83 44 72 XX YY : add DWORD PTR [rdx+rsi*2+XX],YY"},
{ 5, {0x83, 0x64, 0x24, 0x73, 0x74}, 0, "83 64 24 XX YY : and DWORD PTR [rsp+XX], YY"},
+ { 6, {0x41, 0xB8, 0x72, 0x73, 0x74, 0x75}, 0, "41 B8 XX XX XX XX : mov r8d, XX XX XX XX"},
{ 6, {0x48, 0x83, 0x64, 0x24, 0x74, 0x75}, 0, "48 83 64 24 XX YY : and QWORD PTR [rsp + XX], YY"},
{ 6, {0x66, 0x81, 0x78, 0x73, 0x74, 0x75}, 0, "66 81 78 XX YY YY : cmp WORD PTR [rax+XX], YY YY"},
{ 6, {0x66, 0x81, 0x79, 0x73, 0x74, 0x75}, 0, "66 81 79 XX YY YY : cmp WORD PTR [rcx+XX], YY YY"},
>From cb33c236dd5bf6f492ada25b2c4185271a4abe0d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 00:04:12 +0100
Subject: [PATCH 19/20] [win/asan] GetInstructionSize: Support some more 7 or 8
byte instructions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
Related: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
---
compiler-rt/lib/interception/interception_win.cpp | 3 +++
compiler-rt/lib/interception/tests/interception_win_test.cpp | 2 ++
2 files changed, 5 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 1e2357e2118093..27628b7712311e 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -842,6 +842,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
return 6;
case 0xec8148: // 48 81 EC XX XX XX XX : sub rsp, XXXXXXXX
+ case 0xc0c748: // 48 C7 C0 XX XX XX XX : mov rax, XX XX XX XX
return 7;
// clang-format off
@@ -905,6 +906,8 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
return 5;
case 0x24648348: // 48 83 64 24 XX YY : and QWORD PTR [rsp + XX], YY
return 6;
+ case 0x24A48D48: // 48 8D A4 24 XX YY ZZ WW : lea rsp, [rsp + WWZZYYXX]
+ return 8;
}
switch (0xFFFFFFFFFFULL & *(u64*)(address)) {
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index f9d93161b08669..29e4cf2b64fdb6 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -1045,6 +1045,7 @@ const struct InstructionSizeData {
{ 7, {0x48, 0x89, 0x15, 0x73, 0x74, 0x75, 0x76}, 3, "48 89 15 XX XX XX XX : mov QWORD PTR [rip + XXXXXXXX], rdx"},
{ 7, {0x48, 0x8b, 0x05, 0x73, 0x74, 0x75, 0x76}, 3, "48 8b 05 XX XX XX XX : mov rax, QWORD PTR [rip + XXXXXXXX]"},
{ 7, {0x48, 0x8d, 0x05, 0x73, 0x74, 0x75, 0x76}, 3, "48 8d 05 XX XX XX XX : lea rax, QWORD PTR [rip + XXXXXXXX]"},
+ { 7, {0x48, 0xc7, 0xc0, 0x73, 0x74, 0x75, 0x76}, 0, "48 C7 C0 XX XX XX XX : mov rax, XX XX XX XX"},
{ 7, {0x48, 0xff, 0x25, 0x73, 0x74, 0x75, 0x76}, 3, "48 ff 25 XX XX XX XX : rex.W jmp QWORD PTR [rip + XXXXXXXX]"},
{ 7, {0x4C, 0x8D, 0x15, 0x73, 0x74, 0x75, 0x76}, 3, "4c 8d 15 XX XX XX XX : lea r10, [rip + XX]"},
{ 7, {0x81, 0x78, 0x72, 0x73, 0x74, 0x75, 0x76}, 0, "81 78 YY XX XX XX XX : cmp DWORD PTR [rax+YY], XX XX XX XX"},
@@ -1060,6 +1061,7 @@ const struct InstructionSizeData {
{ 8, {0x41, 0x81, 0x7d, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7d XX YY YY YY YY : cmp DWORD PTR [r13+YY], XX XX XX XX"},
{ 8, {0x41, 0x81, 0x7e, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7e XX YY YY YY YY : cmp DWORD PTR [r14+YY], XX XX XX XX"},
{ 8, {0x41, 0x81, 0x7f, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7f YY XX XX XX XX : cmp DWORD PTR [r15+YY], XX XX XX XX"},
+ { 8, {0x48, 0x8D, 0xA4, 0x24, 0x74, 0x75, 0x76, 0x77}, 0, "48 8D A4 24 XX YY ZZ WW : lea rsp, [rsp + WWZZYYXX]"}, // should be rel_offset=4, but then intercepted exectuable crashes
{ 8, {0x81, 0x7c, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "81 7c 24 YY XX XX XX XX : cmp DWORD PTR [rsp+YY], XX XX XX XX"},
{ 8, {0xc7, 0x44, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "C7 44 24 XX YY YY YY YY : mov dword ptr [rsp + XX], YYYYYYYY"},
{ 9, {0x41, 0x81, 0x7c, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "41 81 7c ZZ YY XX XX XX XX : cmp DWORD PTR [reg+reg*n+YY], XX XX XX XX"},
>From 62ee9f2230282638de02d9021e145d081fb07d0e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bernhard=20=C3=9Cbelacker?= <bernhardu at mailbox.org>
Date: Sat, 30 Nov 2024 00:04:33 +0100
Subject: [PATCH 20/20] [win/asan] GetInstructionSize: Support some more 10 or
more byte instructions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
Fixes: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
---
compiler-rt/lib/interception/interception_win.cpp | 14 ++++++++++++++
.../interception/tests/interception_win_test.cpp | 3 +++
2 files changed, 17 insertions(+)
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 27628b7712311e..a672d0db1a9369 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -741,6 +741,8 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x7B81: // 81 7B YY XX XX XX XX cmp DWORD PTR [rbx+YY], XX XX XX XX
case 0x7981: // 81 79 YY XX XX XX XX cmp dword ptr [rcx+YY], XX XX XX XX
return 7;
+ case 0xb848: // 48 b8 XX XX XX XX XX XX XX XX : movabs rax, XX XX XX XX XX XX XX XX
+ return 10;
}
switch (0x00FFFFFF & *(u32 *)address) {
@@ -916,6 +918,18 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
return 5;
}
+ switch (0xFFFFFFFFFFFFULL & *(u64*)(address)) {
+ case 0x841f0f2e6666: // 66 66 2e 0f 1f 84 YY XX XX XX XX
+ // data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]
+ return 11;
+ }
+
+ switch (*(u64*)(address)) {
+ case 0x841f0f2e66666666: // 66 66 66 66 2e 0f 1f 84 YY XX XX XX XX
+ // data16 data16 data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]
+ return 13;
+ }
+
#else
switch (*(u8*)address) {
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index 29e4cf2b64fdb6..6a344530b5fa86 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -1066,6 +1066,9 @@ const struct InstructionSizeData {
{ 8, {0xc7, 0x44, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "C7 44 24 XX YY YY YY YY : mov dword ptr [rsp + XX], YYYYYYYY"},
{ 9, {0x41, 0x81, 0x7c, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "41 81 7c ZZ YY XX XX XX XX : cmp DWORD PTR [reg+reg*n+YY], XX XX XX XX"},
{ 9, {0xA1, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "A1 XX XX XX XX XX XX XX XX : movabs eax, dword ptr ds:[XXXXXXXX]"},
+ {10, {0x48, 0xb8, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79}, 0, "48 b8 XX XX XX XX XX XX XX XX : movabs rax,XX XX XX XX XX XX XX XX"},
+ {11, {0x66, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x76, 0x77, 0x78, 0x79, 0x70}, 0, "66 66 2e 0f 1f 84 YY XX XX XX XX : data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]"},
+ {13, {0x66, 0x66, 0x66, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x78, 0x79, 0x70, 0x71, 0x72}, 0, "66 66 66 66 2e 0f 1f 84 YY XX XX XX XX : data16 data16 data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]"},
#else
// sorted list
{ 3, {0x8B, 0x45, 0x72}, 0, "8B 45 XX : mov eax, dword ptr [ebp + XX]"},
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