[llvm] 2e30df7 - [TableGen] Fix validateOperandClass for non Phyical Reg (#118146)

[via llvm-commits]

Author: Jinsong Ji
Date: 2024-11-30T12:07:15-05:00
New Revision: 2e30df740ef0b9f8edb7075768540ce08678023d

URL: https://github.com/llvm/llvm-project/commit/2e30df740ef0b9f8edb7075768540ce08678023d
DIFF: https://github.com/llvm/llvm-project/commit/2e30df740ef0b9f8edb7075768540ce08678023d.diff

LOG: [TableGen] Fix validateOperandClass for non Phyical Reg (#118146)

https://github.com/llvm/llvm-project/commit/b71704436e61
Rewrote the register operands handling,
but the Table only contains physical regs, we will SEGV when there are
non physical regs.

---------

Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>

Added: 
    

Modified: 
    llvm/utils/TableGen/AsmMatcherEmitter.cpp

Removed: 
    


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diff  --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 28efd780c5c615..f2f6066538e1ad 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2522,8 +2522,9 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
   for (auto &MatchClassName : Table)
     OS << "      " << MatchClassName << ",\n";
   OS << "    };\n\n";
-  OS << "    MatchClassKind OpKind = "
-        "(MatchClassKind)Table[Operand.getReg().id()];\n";
+  OS << "    unsigned RegID = Operand.getReg().id();\n";
+  OS << "    MatchClassKind OpKind = MCRegister::isPhysicalRegister(RegID) ? "
+        "(MatchClassKind)Table[RegID] : InvalidMatchClass;\n";
   OS << "    return isSubclass(OpKind, Kind) ? "
      << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "
      << "                 getDiagKindFromRegisterClass(Kind);\n  }\n\n";