[llvm] [TableGen] Fix validateOperandClass for non Phyical Reg (PR #118146)

[Jinsong Ji via llvm-commits]

https://github.com/jsji updated https://github.com/llvm/llvm-project/pull/118146

>From 9cc10d463928d0e3adc454294402cacc56eff640 Mon Sep 17 00:00:00 2001
From: Jinsong Ji <jinsong.ji at intel.com>
Date: Sat, 30 Nov 2024 01:54:03 +0100
Subject: [PATCH 1/4] Fix validateOperandClass for non Phyical Reg

https://github.com/llvm/llvm-project/commit/b71704436e61
Rewrote the register operands handling,
but the Table only contains physical regs, we will SEGV when there are
non physical regs.
---
 llvm/utils/TableGen/AsmMatcherEmitter.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 28efd780c5c615..1823783e82be4a 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2522,8 +2522,9 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
   for (auto &MatchClassName : Table)
     OS << "      " << MatchClassName << ",\n";
   OS << "    };\n\n";
-  OS << "    MatchClassKind OpKind = "
-        "(MatchClassKind)Table[Operand.getReg().id()];\n";
+  OS << "    auto RegID=Operand.getReg().id();\n";
+  OS << "    MatchClassKind OpKind =  Register::isPhysicalRegister(RegID)?"
+        "(MatchClassKind)Table[RegID]: InvalidMatchClass;\n";
   OS << "    return isSubclass(OpKind, Kind) ? "
      << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "
      << "                 getDiagKindFromRegisterClass(Kind);\n  }\n\n";

>From 5b129ec407921fde8d33bc1fac35788fff270611 Mon Sep 17 00:00:00 2001
From: Jinsong Ji <jinsong.ji at intel.com>
Date: Sat, 30 Nov 2024 04:11:19 +0100
Subject: [PATCH 2/4] Use MCRegister

---
 llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 1823783e82be4a..b0804d35fadd56 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2523,7 +2523,7 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
     OS << "      " << MatchClassName << ",\n";
   OS << "    };\n\n";
   OS << "    auto RegID=Operand.getReg().id();\n";
-  OS << "    MatchClassKind OpKind =  Register::isPhysicalRegister(RegID)?"
+  OS << "    MatchClassKind OpKind =  MCRegister::isPhysicalRegister(RegID)?"
         "(MatchClassKind)Table[RegID]: InvalidMatchClass;\n";
   OS << "    return isSubclass(OpKind, Kind) ? "
      << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "

>From 5c362f5f791c4342d0ff996051e5cd2f207080c6 Mon Sep 17 00:00:00 2001
From: Jinsong Ji <jinsong.ji at intel.com>
Date: Sat, 30 Nov 2024 16:57:32 +0100
Subject: [PATCH 3/4] Address comments

---
 llvm/utils/TableGen/AsmMatcherEmitter.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index b0804d35fadd56..07493f68a80dac 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2522,9 +2522,9 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
   for (auto &MatchClassName : Table)
     OS << "      " << MatchClassName << ",\n";
   OS << "    };\n\n";
-  OS << "    auto RegID=Operand.getReg().id();\n";
-  OS << "    MatchClassKind OpKind =  MCRegister::isPhysicalRegister(RegID)?"
-        "(MatchClassKind)Table[RegID]: InvalidMatchClass;\n";
+  OS << "    unsigned RegID=Operand.getReg().id();\n";
+  OS << "    MatchClassKind OpKind =  MCRegister::isPhysicalRegister(RegID) ? "
+        "(MatchClassKind)Table[RegID] : InvalidMatchClass;\n";
   OS << "    return isSubclass(OpKind, Kind) ? "
      << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "
      << "                 getDiagKindFromRegisterClass(Kind);\n  }\n\n";

>From be8cb1d3f6b878a7bb7cc1333118957d1fe27ad2 Mon Sep 17 00:00:00 2001
From: Jinsong Ji <jinsong.ji at intel.com>
Date: Sat, 30 Nov 2024 11:47:40 -0500
Subject: [PATCH 4/4] Update llvm/utils/TableGen/AsmMatcherEmitter.cpp

Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
---
 llvm/utils/TableGen/AsmMatcherEmitter.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 07493f68a80dac..f2f6066538e1ad 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2522,8 +2522,8 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
   for (auto &MatchClassName : Table)
     OS << "      " << MatchClassName << ",\n";
   OS << "    };\n\n";
-  OS << "    unsigned RegID=Operand.getReg().id();\n";
-  OS << "    MatchClassKind OpKind =  MCRegister::isPhysicalRegister(RegID) ? "
+  OS << "    unsigned RegID = Operand.getReg().id();\n";
+  OS << "    MatchClassKind OpKind = MCRegister::isPhysicalRegister(RegID) ? "
         "(MatchClassKind)Table[RegID] : InvalidMatchClass;\n";
   OS << "    return isSubclass(OpKind, Kind) ? "
      << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "