[llvm] [TableGen] Fix validateOperandClass for non Phyical Reg (PR #118146)

[Sergei Barannikov via llvm-commits]

s-barannikov wrote:

> > How can a register not be physical here?
> 
> Target can allow using non-physical registers in assembly. We do have a downstream target that use virtual registers. The original code also supports such scenarios in the `default` clause.

I see, thanks.


https://github.com/llvm/llvm-project/pull/118146