[llvm] [TableGen] Fix validateOperandClass for non Phyical Reg (PR #118146)

[Jinsong Ji via llvm-commits]

jsji wrote:

> How can a register not be physical here?

Target can allow using non-physical registers in assembly. 
We do have a downstream target that use virtual registers.
The original code also supports such scenarios in the `default` clause.

https://github.com/llvm/llvm-project/pull/118146