[llvm] [SCEV] Do not allow refinement in the rewriting of BEValue (PR #117152)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 29 08:37:44 PST 2024
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/117152
>From 8aecde3e8d931073e1ab2c94cd04bf9084f24cfe Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Thu, 21 Nov 2024 20:16:58 +0800
Subject: [PATCH 1/5] [SCEV] Add pre-commit tests. NFC.
---
.../test/Analysis/ScalarEvolution/pr117133.ll | 53 +++++++++++++++++++
.../Transforms/IndVarSimplify/pr117133.ll | 45 ++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 llvm/test/Analysis/ScalarEvolution/pr117133.ll
create mode 100644 llvm/test/Transforms/IndVarSimplify/pr117133.ll
diff --git a/llvm/test/Analysis/ScalarEvolution/pr117133.ll b/llvm/test/Analysis/ScalarEvolution/pr117133.ll
new file mode 100644
index 00000000000000..ab8c952b0e5c84
--- /dev/null
+++ b/llvm/test/Analysis/ScalarEvolution/pr117133.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -disable-output "-passes=print<scalar-evolution>" < %s 2>&1 | FileCheck %s
+
+define i32 @widget() {
+; CHECK-LABEL: 'widget'
+; CHECK-NEXT: Classifying expressions for: @widget
+; CHECK-NEXT: %phi = phi i32 [ 0, %b ], [ %udiv6, %b5 ]
+; CHECK-NEXT: --> ({0,+,1}<nuw><nsw><%b1> /u 0) U: empty-set S: empty-set Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
+; CHECK-NEXT: %phi2 = phi i32 [ 1, %b ], [ %add, %b5 ]
+; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%b1> U: [1,2) S: [1,2) Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
+; CHECK-NEXT: %udiv = udiv i32 10, %phi2
+; CHECK-NEXT: --> (10 /u {1,+,1}<nuw><nsw><%b1>) U: [10,11) S: [10,11) Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
+; CHECK-NEXT: %urem = urem i32 %udiv, 10
+; CHECK-NEXT: --> ((-10 * ((10 /u {1,+,1}<nuw><nsw><%b1>) /u 10))<nuw><nsw> + (10 /u {1,+,1}<nuw><nsw><%b1>)) U: [0,1) S: [0,1) Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
+; CHECK-NEXT: %udiv6 = udiv i32 %phi2, 0
+; CHECK-NEXT: --> ({1,+,1}<nuw><nsw><%b1> /u 0) U: empty-set S: empty-set Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
+; CHECK-NEXT: %add = add i32 %phi2, 1
+; CHECK-NEXT: --> {2,+,1}<nuw><nsw><%b1> U: [2,3) S: [2,3) Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
+; CHECK-NEXT: Determining loop execution counts for: @widget
+; CHECK-NEXT: Loop %b1: <multiple exits> Unpredictable backedge-taken count.
+; CHECK-NEXT: exit count for b1: ***COULDNOTCOMPUTE***
+; CHECK-NEXT: exit count for b3: i32 0
+; CHECK-NEXT: Loop %b1: constant max backedge-taken count is i32 0
+; CHECK-NEXT: Loop %b1: symbolic max backedge-taken count is i32 0
+; CHECK-NEXT: symbolic max exit count for b1: ***COULDNOTCOMPUTE***
+; CHECK-NEXT: symbolic max exit count for b3: i32 0
+;
+b:
+ br label %b1
+
+b1: ; preds = %b5, %b
+ %phi = phi i32 [ 0, %b ], [ %udiv6, %b5 ]
+ %phi2 = phi i32 [ 1, %b ], [ %add, %b5 ]
+ %icmp = icmp eq i32 %phi, 0
+ br i1 %icmp, label %b3, label %b8
+
+b3: ; preds = %b1
+ %udiv = udiv i32 10, %phi2
+ %urem = urem i32 %udiv, 10
+ %icmp4 = icmp eq i32 %urem, 0
+ br i1 %icmp4, label %b7, label %b5
+
+b5: ; preds = %b3
+ %udiv6 = udiv i32 %phi2, 0
+ %add = add i32 %phi2, 1
+ br label %b1
+
+b7: ; preds = %b3
+ ret i32 5
+
+b8: ; preds = %b1
+ ret i32 7
+}
diff --git a/llvm/test/Transforms/IndVarSimplify/pr117133.ll b/llvm/test/Transforms/IndVarSimplify/pr117133.ll
new file mode 100644
index 00000000000000..bb9f1cf4d82cdf
--- /dev/null
+++ b/llvm/test/Transforms/IndVarSimplify/pr117133.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -passes=indvars < %s | FileCheck %s
+
+
+define i32 @widget() {
+; CHECK-LABEL: define i32 @widget() {
+; CHECK-NEXT: [[B:.*:]]
+; CHECK-NEXT: br label %[[B1:.*]]
+; CHECK: [[B1]]:
+; CHECK-NEXT: br i1 false, label %[[B3:.*]], label %[[B8:.*]]
+; CHECK: [[B3]]:
+; CHECK-NEXT: br i1 true, label %[[B7:.*]], label %[[B5:.*]]
+; CHECK: [[B5]]:
+; CHECK-NEXT: br label %[[B1]]
+; CHECK: [[B7]]:
+; CHECK-NEXT: ret i32 5
+; CHECK: [[B8]]:
+; CHECK-NEXT: ret i32 7
+;
+b:
+ br label %b1
+
+b1:
+ %phi = phi i32 [ 0, %b ], [ %udiv6, %b5 ]
+ %phi2 = phi i32 [ 1, %b ], [ %add, %b5 ]
+ %icmp = icmp eq i32 %phi, 0
+ br i1 %icmp, label %b3, label %b8
+
+b3:
+ %udiv = udiv i32 10, %phi2
+ %urem = urem i32 %udiv, 10
+ %icmp4 = icmp eq i32 %urem, 0
+ br i1 %icmp4, label %b7, label %b5
+
+b5:
+ %udiv6 = udiv i32 %phi2, 0
+ %add = add i32 %phi2, 1
+ br label %b1
+
+b7:
+ ret i32 5
+
+b8:
+ ret i32 7
+}
>From 5ba4943d99916f287ade5b4a2cd6c427970f2883 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Thu, 21 Nov 2024 23:06:52 +0800
Subject: [PATCH 2/5] [SCEV] Do not allow refinement in the rewriting of
BEValue
---
llvm/include/llvm/Analysis/ScalarEvolution.h | 3 ++
llvm/lib/Analysis/ScalarEvolution.cpp | 47 ++++++++++---------
llvm/test/Analysis/ScalarEvolution/fold.ll | 2 +-
.../test/Analysis/ScalarEvolution/pr117133.ll | 2 +-
.../udiv-of-x-xsmaxone-fold.ll | 4 +-
.../Transforms/IndVarSimplify/pr117133.ll | 2 +-
6 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/llvm/include/llvm/Analysis/ScalarEvolution.h b/llvm/include/llvm/Analysis/ScalarEvolution.h
index 885c5985f9d23a..b20c6a13cb6bd7 100644
--- a/llvm/include/llvm/Analysis/ScalarEvolution.h
+++ b/llvm/include/llvm/Analysis/ScalarEvolution.h
@@ -2187,6 +2187,9 @@ class ScalarEvolution {
bool isGuaranteedToTransferExecutionTo(const Instruction *A,
const Instruction *B);
+ /// Returns true if \p Op is guaranteed not to cause immediate UB.
+ bool isGuaranteedNotToCauseUB(const SCEV *Op);
+
/// Returns true if \p Op is guaranteed to not be poison.
static bool isGuaranteedNotToBePoison(const SCEV *Op);
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 376f260846bbaa..091a0762fad212 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -4307,15 +4307,7 @@ ScalarEvolution::getSequentialMinMaxExpr(SCEVTypes Kind,
}
for (unsigned i = 1, e = Ops.size(); i != e; ++i) {
- bool MayBeUB = SCEVExprContains(Ops[i], [this](const SCEV *S) {
- auto *UDiv = dyn_cast<SCEVUDivExpr>(S);
- // The UDiv may be UB if the divisor is poison or zero. Unless the divisor
- // is a non-zero constant, we have to assume the UDiv may be UB.
- return UDiv && (!isKnownNonZero(UDiv->getOperand(1)) ||
- !isGuaranteedNotToBePoison(UDiv->getOperand(1)));
- });
-
- if (MayBeUB)
+ if (!isGuaranteedNotToCauseUB(Ops[i]))
continue;
// We can replace %x umin_seq %y with %x umin %y if either:
// * %y being poison implies %x is also poison.
@@ -5933,18 +5925,21 @@ const SCEV *ScalarEvolution::createAddRecFromPHI(PHINode *PN) {
// We can generalize this saying that i is the shifted value of BEValue
// by one iteration:
// PHI(f(0), f({1,+,1})) --> f({0,+,1})
- const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this);
- const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false);
- if (Shifted != getCouldNotCompute() &&
- Start != getCouldNotCompute()) {
- const SCEV *StartVal = getSCEV(StartValueV);
- if (Start == StartVal) {
- // Okay, for the entire analysis of this edge we assumed the PHI
- // to be symbolic. We now need to go back and purge all of the
- // entries for the scalars that use the symbolic expression.
- forgetMemoizedResults(SymbolicName);
- insertValueToMap(PN, Shifted);
- return Shifted;
+
+ // Do not allow refinement in rewriting of BEValue.
+ if (isGuaranteedNotToCauseUB(BEValue)) {
+ const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this);
+ const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false);
+ if (Shifted != getCouldNotCompute() && Start != getCouldNotCompute()) {
+ const SCEV *StartVal = getSCEV(StartValueV);
+ if (Start == StartVal) {
+ // Okay, for the entire analysis of this edge we assumed the PHI
+ // to be symbolic. We now need to go back and purge all of the
+ // entries for the scalars that use the symbolic expression.
+ forgetMemoizedResults(SymbolicName);
+ insertValueToMap(PN, Shifted);
+ return Shifted;
+ }
}
}
}
@@ -7322,6 +7317,16 @@ bool ScalarEvolution::isGuaranteedNotToBePoison(const SCEV *Op) {
return PC.MaybePoison.empty();
}
+bool ScalarEvolution::isGuaranteedNotToCauseUB(const SCEV *Op) {
+ return !SCEVExprContains(Op, [this](const SCEV *S) {
+ auto *UDiv = dyn_cast<SCEVUDivExpr>(S);
+ // The UDiv may be UB if the divisor is poison or zero. Unless the divisor
+ // is a non-zero constant, we have to assume the UDiv may be UB.
+ return UDiv && (!isKnownNonZero(UDiv->getOperand(1)) ||
+ !isGuaranteedNotToBePoison(UDiv->getOperand(1)));
+ });
+}
+
bool ScalarEvolution::isSCEVExprNeverPoison(const Instruction *I) {
// Only proceed if we can prove that I does not yield poison.
if (!programUndefinedIfPoison(I))
diff --git a/llvm/test/Analysis/ScalarEvolution/fold.ll b/llvm/test/Analysis/ScalarEvolution/fold.ll
index 670523ca1bb5b9..5fde3b18da9fe9 100644
--- a/llvm/test/Analysis/ScalarEvolution/fold.ll
+++ b/llvm/test/Analysis/ScalarEvolution/fold.ll
@@ -214,7 +214,7 @@ define i64 @test10(i64 %a, i64 %b) {
ret i64 %t2
}
-define i64 @test11(i64 %a) {
+define i64 @test11(i64 noundef range(i64 1, 0) %a) {
; CHECK-LABEL: 'test11'
; CHECK-NEXT: Classifying expressions for: @test11
; CHECK-NEXT: %t0 = udiv i64 0, %a
diff --git a/llvm/test/Analysis/ScalarEvolution/pr117133.ll b/llvm/test/Analysis/ScalarEvolution/pr117133.ll
index ab8c952b0e5c84..75f15055ce3d94 100644
--- a/llvm/test/Analysis/ScalarEvolution/pr117133.ll
+++ b/llvm/test/Analysis/ScalarEvolution/pr117133.ll
@@ -5,7 +5,7 @@ define i32 @widget() {
; CHECK-LABEL: 'widget'
; CHECK-NEXT: Classifying expressions for: @widget
; CHECK-NEXT: %phi = phi i32 [ 0, %b ], [ %udiv6, %b5 ]
-; CHECK-NEXT: --> ({0,+,1}<nuw><nsw><%b1> /u 0) U: empty-set S: empty-set Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
+; CHECK-NEXT: --> %phi U: [0,1) S: [0,1) Exits: <<Unknown>> LoopDispositions: { %b1: Variant }
; CHECK-NEXT: %phi2 = phi i32 [ 1, %b ], [ %add, %b5 ]
; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%b1> U: [1,2) S: [1,2) Exits: <<Unknown>> LoopDispositions: { %b1: Computable }
; CHECK-NEXT: %udiv = udiv i32 10, %phi2
diff --git a/llvm/test/Analysis/ScalarEvolution/udiv-of-x-xsmaxone-fold.ll b/llvm/test/Analysis/ScalarEvolution/udiv-of-x-xsmaxone-fold.ll
index 9405c0f726ac7f..5694a505ccb316 100644
--- a/llvm/test/Analysis/ScalarEvolution/udiv-of-x-xsmaxone-fold.ll
+++ b/llvm/test/Analysis/ScalarEvolution/udiv-of-x-xsmaxone-fold.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -disable-output -passes="print<scalar-evolution>" < %s 2>&1 | FileCheck %s
-define i32 @test_expr_with_constant_1(i32 %x) {
+define i32 @test_expr_with_constant_1(i32 noundef range(i32 1, 0) %x) {
; CHECK-LABEL: 'test_expr_with_constant_1'
; CHECK-NEXT: Classifying expressions for: @test_expr_with_constant_1
; CHECK-NEXT: %smax = tail call i32 @llvm.smax.i32(i32 %x, i32 1)
@@ -20,7 +20,7 @@ entry:
}
; Non-1 constant: (-2 + (2 smax %x)) /u %x
-define i32 @test_expr_with_constant_2(i32 %x) {
+define i32 @test_expr_with_constant_2(i32 noundef range(i32 1, 0) %x) {
; CHECK-LABEL: 'test_expr_with_constant_2'
; CHECK-NEXT: Classifying expressions for: @test_expr_with_constant_2
; CHECK-NEXT: %smax = tail call i32 @llvm.smax.i32(i32 %x, i32 2)
diff --git a/llvm/test/Transforms/IndVarSimplify/pr117133.ll b/llvm/test/Transforms/IndVarSimplify/pr117133.ll
index bb9f1cf4d82cdf..31545ecba94cdb 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr117133.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr117133.ll
@@ -7,7 +7,7 @@ define i32 @widget() {
; CHECK-NEXT: [[B:.*:]]
; CHECK-NEXT: br label %[[B1:.*]]
; CHECK: [[B1]]:
-; CHECK-NEXT: br i1 false, label %[[B3:.*]], label %[[B8:.*]]
+; CHECK-NEXT: br i1 true, label %[[B3:.*]], label %[[B8:.*]]
; CHECK: [[B3]]:
; CHECK-NEXT: br i1 true, label %[[B7:.*]], label %[[B5:.*]]
; CHECK: [[B5]]:
>From 137ff32ab98e48b2386c4fa65db7a0d08e6ae641 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Thu, 21 Nov 2024 23:13:14 +0800
Subject: [PATCH 3/5] Remove newline
---
llvm/test/Transforms/IndVarSimplify/pr117133.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/Transforms/IndVarSimplify/pr117133.ll b/llvm/test/Transforms/IndVarSimplify/pr117133.ll
index 31545ecba94cdb..f62dc3f04a0966 100644
--- a/llvm/test/Transforms/IndVarSimplify/pr117133.ll
+++ b/llvm/test/Transforms/IndVarSimplify/pr117133.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes=indvars < %s | FileCheck %s
-
define i32 @widget() {
; CHECK-LABEL: define i32 @widget() {
; CHECK-NEXT: [[B:.*:]]
>From b16665eb9a2383799d139023f963239d6a6ac5c0 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Fri, 29 Nov 2024 23:57:29 +0800
Subject: [PATCH 4/5] [SCEV] Add poison check.
---
llvm/lib/Analysis/ScalarEvolution.cpp | 3 +-
.../LoopAccessAnalysis/noalias-scope-decl.ll | 2 +-
.../arm_cmplx_dot_prod_f32.ll | 2 +-
.../CodeGen/Thumb2/mve-float16regloops.ll | 72 ++++++++++---------
.../CodeGen/Thumb2/mve-float32regloops.ll | 8 ++-
.../IndVarSimplify/no-iv-rewrite.ll | 2 +-
.../LoopVectorize/RISCV/induction-costs.ll | 4 +-
.../LoopVectorize/X86/induction-costs.ll | 12 ++--
.../LoopVectorize/X86/masked-store-cost.ll | 8 +--
9 files changed, 60 insertions(+), 53 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 091a0762fad212..bf41bfcad0c39e 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -5927,7 +5927,8 @@ const SCEV *ScalarEvolution::createAddRecFromPHI(PHINode *PN) {
// PHI(f(0), f({1,+,1})) --> f({0,+,1})
// Do not allow refinement in rewriting of BEValue.
- if (isGuaranteedNotToCauseUB(BEValue)) {
+ if (isGuaranteedNotToCauseUB(BEValue) &&
+ isGuaranteedNotToBePoison(BEValue)) {
const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this);
const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false);
if (Shifted != getCouldNotCompute() && Start != getCouldNotCompute()) {
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll b/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
index fb296f5089422d..29840f6e293875 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
@@ -4,7 +4,7 @@
; PR79137: If the noalias.scope.decl is located inside the loop, we cannot
; assume that the accesses don't alias across iterations.
-define void @test_scope_in_loop(ptr %arg, i64 %num) {
+define void @test_scope_in_loop(ptr noundef %arg, i64 %num) {
; CHECK-LABEL: 'test_scope_in_loop'
; CHECK-NEXT: loop:
; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
index 13080fcfa13574..1b6b3c901fc975 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
-define void @arm_cmplx_dot_prod_f32(ptr %pSrcA, ptr %pSrcB, i32 %numSamples, ptr nocapture %realResult, ptr nocapture %imagResult) {
+define void @arm_cmplx_dot_prod_f32(ptr noundef %pSrcA, ptr noundef %pSrcB, i32 %numSamples, ptr nocapture %realResult, ptr nocapture %imagResult) {
; CHECK-LABEL: arm_cmplx_dot_prod_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr}
diff --git a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
index 1c95d28b5eed1b..be7e017818bb8a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
@@ -1004,22 +1004,22 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph
; CHECK-NEXT: ldrh r4, [r0]
; CHECK-NEXT: movs r1, #1
-; CHECK-NEXT: ldrd r5, r3, [r0, #4]
+; CHECK-NEXT: ldrd r5, r7, [r0, #4]
; CHECK-NEXT: sub.w r0, r4, #8
-; CHECK-NEXT: add.w r7, r0, r0, lsr #29
+; CHECK-NEXT: add.w r3, r0, r0, lsr #29
; CHECK-NEXT: and r0, r0, #7
-; CHECK-NEXT: asrs r6, r7, #3
+; CHECK-NEXT: asrs r6, r3, #3
; CHECK-NEXT: cmp r6, #1
; CHECK-NEXT: it gt
-; CHECK-NEXT: asrgt r1, r7, #3
-; CHECK-NEXT: add.w r7, r5, r4, lsl #1
+; CHECK-NEXT: asrgt r1, r3, #3
+; CHECK-NEXT: add.w r3, r5, r4, lsl #1
; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
-; CHECK-NEXT: subs r1, r7, #2
-; CHECK-NEXT: rsbs r7, r4, #0
-; CHECK-NEXT: str r7, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: add.w r7, r3, #16
+; CHECK-NEXT: subs r1, r3, #2
+; CHECK-NEXT: rsbs r3, r4, #0
+; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: add.w r3, r7, #16
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: str r7, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: b .LBB16_6
; CHECK-NEXT: .LBB16_3: @ %while.end.loopexit
@@ -1045,36 +1045,36 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ Child Loop BB16_8 Depth 2
; CHECK-NEXT: @ Child Loop BB16_11 Depth 2
; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
-; CHECK-NEXT: ldrh.w lr, [r3, #14]
+; CHECK-NEXT: ldrh.w lr, [r7, #14]
; CHECK-NEXT: vldrw.u32 q0, [r0], #8
-; CHECK-NEXT: ldrh.w r8, [r3, #12]
-; CHECK-NEXT: ldrh r7, [r3, #10]
-; CHECK-NEXT: ldrh r4, [r3, #8]
-; CHECK-NEXT: ldrh r6, [r3, #6]
-; CHECK-NEXT: ldrh.w r9, [r3, #4]
-; CHECK-NEXT: ldrh.w r11, [r3, #2]
-; CHECK-NEXT: ldrh.w r10, [r3]
+; CHECK-NEXT: ldrh.w r9, [r7, #12]
+; CHECK-NEXT: ldrh.w r10, [r7, #10]
+; CHECK-NEXT: ldrh r4, [r7, #8]
+; CHECK-NEXT: ldrh r3, [r7, #6]
+; CHECK-NEXT: ldrh r6, [r7, #4]
+; CHECK-NEXT: ldrh.w r11, [r7, #2]
+; CHECK-NEXT: ldrh.w r8, [r7]
; CHECK-NEXT: vstrb.8 q0, [r1], #8
; CHECK-NEXT: vldrw.u32 q0, [r5]
; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: adds r0, r5, #2
; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: vmul.f16 q0, q0, r10
+; CHECK-NEXT: vmul.f16 q0, q0, r8
; CHECK-NEXT: adds r0, r5, #6
; CHECK-NEXT: vfma.f16 q0, q1, r11
; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
-; CHECK-NEXT: vfma.f16 q0, q1, r9
+; CHECK-NEXT: vfma.f16 q0, q1, r6
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: add.w r0, r5, #10
-; CHECK-NEXT: vfma.f16 q0, q1, r6
+; CHECK-NEXT: vfma.f16 q0, q1, r3
; CHECK-NEXT: vldrw.u32 q1, [r5, #8]
; CHECK-NEXT: vfma.f16 q0, q1, r4
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: add.w r0, r5, #14
-; CHECK-NEXT: vfma.f16 q0, q1, r7
+; CHECK-NEXT: vfma.f16 q0, q1, r10
; CHECK-NEXT: vldrw.u32 q1, [r5, #12]
; CHECK-NEXT: adds r5, #16
-; CHECK-NEXT: vfma.f16 q0, q1, r8
+; CHECK-NEXT: vfma.f16 q0, q1, r9
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vfma.f16 q0, q1, lr
@@ -1083,40 +1083,44 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ %bb.7: @ %for.body.preheader
; CHECK-NEXT: @ in Loop: Header=BB16_6 Depth=1
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: dls lr, r0
; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: .LBB16_8: @ %for.body
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: ldrh r0, [r6], #16
+; CHECK-NEXT: ldrh r0, [r3, #16]
; CHECK-NEXT: vldrw.u32 q1, [r5]
; CHECK-NEXT: adds r4, r5, #2
+; CHECK-NEXT: mov r9, r6
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: vldrw.u32 q1, [r4]
-; CHECK-NEXT: ldrh r0, [r6, #-14]
+; CHECK-NEXT: ldrh r0, [r3, #18]
; CHECK-NEXT: adds r4, r5, #6
+; CHECK-NEXT: adds r6, #16
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: ldrh r0, [r6, #-12]
+; CHECK-NEXT: ldrh r0, [r3, #20]
; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: vldrw.u32 q1, [r4]
-; CHECK-NEXT: ldrh r0, [r6, #-10]
+; CHECK-NEXT: ldrh r0, [r3, #22]
; CHECK-NEXT: add.w r4, r5, #10
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: ldrh r0, [r6, #-8]
+; CHECK-NEXT: ldrh r0, [r3, #24]
; CHECK-NEXT: vldrw.u32 q1, [r5, #8]
; CHECK-NEXT: vfma.f16 q0, q1, r0
+; CHECK-NEXT: ldrh r0, [r3, #26]
; CHECK-NEXT: vldrw.u32 q1, [r4]
-; CHECK-NEXT: ldrh r0, [r6, #-6]
-; CHECK-NEXT: ldrh r4, [r6, #-2]
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: ldrh r0, [r6, #-4]
+; CHECK-NEXT: ldrh r0, [r3, #28]
; CHECK-NEXT: vldrw.u32 q1, [r5, #12]
+; CHECK-NEXT: ldrh r3, [r3, #30]
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: add.w r0, r5, #14
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: adds r5, #16
-; CHECK-NEXT: vfma.f16 q0, q1, r4
+; CHECK-NEXT: vfma.f16 q0, q1, r3
+; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: le lr, .LBB16_8
; CHECK-NEXT: b .LBB16_4
; CHECK-NEXT: .LBB16_9: @ in Loop: Header=BB16_6 Depth=1
@@ -1128,9 +1132,9 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: .LBB16_11: @ %while.body76
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: ldrh r4, [r6], #2
+; CHECK-NEXT: ldrh r3, [r6], #2
; CHECK-NEXT: vldrh.u16 q1, [r0], #2
-; CHECK-NEXT: vfma.f16 q0, q1, r4
+; CHECK-NEXT: vfma.f16 q0, q1, r3
; CHECK-NEXT: le lr, .LBB16_11
; CHECK-NEXT: b .LBB16_3
; CHECK-NEXT: .LBB16_12: @ %if.end
diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
index 808626d9a0aebe..b74776811ab610 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
-define arm_aapcs_vfpcc void @test_fadd(ptr noalias nocapture readonly %A, float %B, ptr noalias nocapture %C, i32 %n) {
+define arm_aapcs_vfpcc void @test_fadd(ptr noalias nocapture readonly noundef %A, float %B, ptr noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fadd:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1
@@ -1119,9 +1119,9 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: bx lr
entry:
%pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 1
- %i = load ptr, ptr %pState1, align 4
+ %i = load ptr, ptr %pState1, align 4, !noundef !0
%pCoeffs2 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 2
- %i1 = load ptr, ptr %pCoeffs2, align 4
+ %i1 = load ptr, ptr %pCoeffs2, align 4, !noundef !0
%numTaps3 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 0
%i2 = load i16, ptr %numTaps3, align 4
%conv = zext i16 %i2 to i32
@@ -2117,3 +2117,5 @@ declare void @llvm.assume(i1)
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>)
+
+!0 = !{}
diff --git a/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll b/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
index 5bd28470ef76be..f09726f7abde94 100644
--- a/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
+++ b/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
@@ -371,7 +371,7 @@ return:
; Two phis should remain, one starting at %init, and one at %init1.
; Two increments should remain, one by %step and one by %step1.
; Five live-outs should remain.
-define i32 @isomorphic(i32 %init, i32 %step, i32 %lim) nounwind {
+define i32 @isomorphic(i32 noundef %init, i32 noundef %step, i32 %lim) nounwind {
; CHECK-LABEL: @isomorphic(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STEP1:%.*]] = add i32 [[STEP:%.*]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
index 49e9abcd9f9192..49591ff3770ca8 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
@@ -5,9 +5,9 @@ target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"
; Test case for https://github.com/llvm/llvm-project/issues/106417.
-define void @skip_free_iv_truncate(i16 %x, ptr %A) #0 {
+define void @skip_free_iv_truncate(i16 noundef %x, ptr %A) #0 {
; CHECK-LABEL: define void @skip_free_iv_truncate(
-; CHECK-SAME: i16 [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: i16 noundef [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[X_I32:%.*]] = sext i16 [[X]] to i32
; CHECK-NEXT: [[X_I64:%.*]] = sext i16 [[X]] to i64
diff --git a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
index bc74742d952abe..aae2274926fef7 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
@@ -706,9 +706,9 @@ exit:
ret void
}
-define void @wombat(i32 %arg, ptr %dst) #1 {
+define void @wombat(i32 noundef %arg, ptr %dst) #1 {
; CHECK-LABEL: define void @wombat(
-; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1:[0-9]+]] {
+; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
@@ -780,9 +780,9 @@ exit:
ret void
}
-define void @wombat2(i32 %arg, ptr %dst) #1 {
+define void @wombat2(i32 noundef %arg, ptr %dst) #1 {
; CHECK-LABEL: define void @wombat2(
-; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
+; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
@@ -857,9 +857,9 @@ exit:
}
-define void @with_dead_use(i32 %arg, ptr %dst) #1 {
+define void @with_dead_use(i32 noundef %arg, ptr %dst) #1 {
; CHECK-LABEL: define void @with_dead_use(
-; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
+; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
diff --git a/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
index 7cf36fc669f37d..6d219fd341b3b8 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
@@ -128,9 +128,9 @@ exit:
ret i32 0
}
-define void @test_scalar_cost_single_store_loop_invariant_cond(ptr %dst, i1 %c) #0 {
+define void @test_scalar_cost_single_store_loop_invariant_cond(ptr noundef %dst, i1 %c) #0 {
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_invariant_cond(
-; CHECK-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr noundef [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
@@ -191,9 +191,9 @@ exit:
ret void
}
-define void @test_scalar_cost_single_store_loop_varying_cond(ptr %dst, ptr noalias %src) #0 {
+define void @test_scalar_cost_single_store_loop_varying_cond(ptr noundef %dst, ptr noalias %src) #0 {
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_varying_cond(
-; CHECK-SAME: ptr [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr noundef [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
>From 47c612677695e14f2bae7b60992df1a2d8e63e10 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sat, 30 Nov 2024 00:37:03 +0800
Subject: [PATCH 5/5] [SCEV] Use `impliesPoison`
---
llvm/lib/Analysis/ScalarEvolution.cpp | 6 +-
.../LoopAccessAnalysis/noalias-scope-decl.ll | 2 +-
.../arm_cmplx_dot_prod_f32.ll | 2 +-
.../CodeGen/Thumb2/mve-float16regloops.ll | 72 +++++++++----------
.../CodeGen/Thumb2/mve-float32regloops.ll | 8 +--
.../IndVarSimplify/no-iv-rewrite.ll | 2 +-
.../LoopVectorize/RISCV/induction-costs.ll | 4 +-
.../LoopVectorize/X86/induction-costs.ll | 12 ++--
.../LoopVectorize/X86/masked-store-cost.ll | 8 +--
9 files changed, 55 insertions(+), 61 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index bf41bfcad0c39e..1af8f681cfee39 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -5927,11 +5927,11 @@ const SCEV *ScalarEvolution::createAddRecFromPHI(PHINode *PN) {
// PHI(f(0), f({1,+,1})) --> f({0,+,1})
// Do not allow refinement in rewriting of BEValue.
- if (isGuaranteedNotToCauseUB(BEValue) &&
- isGuaranteedNotToBePoison(BEValue)) {
+ if (isGuaranteedNotToCauseUB(BEValue)) {
const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this);
const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false);
- if (Shifted != getCouldNotCompute() && Start != getCouldNotCompute()) {
+ if (Shifted != getCouldNotCompute() && Start != getCouldNotCompute() &&
+ ::impliesPoison(BEValue, Start)) {
const SCEV *StartVal = getSCEV(StartValueV);
if (Start == StartVal) {
// Okay, for the entire analysis of this edge we assumed the PHI
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll b/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
index 29840f6e293875..fb296f5089422d 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
@@ -4,7 +4,7 @@
; PR79137: If the noalias.scope.decl is located inside the loop, we cannot
; assume that the accesses don't alias across iterations.
-define void @test_scope_in_loop(ptr noundef %arg, i64 %num) {
+define void @test_scope_in_loop(ptr %arg, i64 %num) {
; CHECK-LABEL: 'test_scope_in_loop'
; CHECK-NEXT: loop:
; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
index 1b6b3c901fc975..13080fcfa13574 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
-define void @arm_cmplx_dot_prod_f32(ptr noundef %pSrcA, ptr noundef %pSrcB, i32 %numSamples, ptr nocapture %realResult, ptr nocapture %imagResult) {
+define void @arm_cmplx_dot_prod_f32(ptr %pSrcA, ptr %pSrcB, i32 %numSamples, ptr nocapture %realResult, ptr nocapture %imagResult) {
; CHECK-LABEL: arm_cmplx_dot_prod_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr}
diff --git a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
index be7e017818bb8a..1c95d28b5eed1b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
@@ -1004,22 +1004,22 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph
; CHECK-NEXT: ldrh r4, [r0]
; CHECK-NEXT: movs r1, #1
-; CHECK-NEXT: ldrd r5, r7, [r0, #4]
+; CHECK-NEXT: ldrd r5, r3, [r0, #4]
; CHECK-NEXT: sub.w r0, r4, #8
-; CHECK-NEXT: add.w r3, r0, r0, lsr #29
+; CHECK-NEXT: add.w r7, r0, r0, lsr #29
; CHECK-NEXT: and r0, r0, #7
-; CHECK-NEXT: asrs r6, r3, #3
+; CHECK-NEXT: asrs r6, r7, #3
; CHECK-NEXT: cmp r6, #1
; CHECK-NEXT: it gt
-; CHECK-NEXT: asrgt r1, r3, #3
-; CHECK-NEXT: add.w r3, r5, r4, lsl #1
+; CHECK-NEXT: asrgt r1, r7, #3
+; CHECK-NEXT: add.w r7, r5, r4, lsl #1
; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
-; CHECK-NEXT: subs r1, r3, #2
-; CHECK-NEXT: rsbs r3, r4, #0
-; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: add.w r3, r7, #16
+; CHECK-NEXT: subs r1, r7, #2
+; CHECK-NEXT: rsbs r7, r4, #0
+; CHECK-NEXT: str r7, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: add.w r7, r3, #16
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r7, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: b .LBB16_6
; CHECK-NEXT: .LBB16_3: @ %while.end.loopexit
@@ -1045,36 +1045,36 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ Child Loop BB16_8 Depth 2
; CHECK-NEXT: @ Child Loop BB16_11 Depth 2
; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
-; CHECK-NEXT: ldrh.w lr, [r7, #14]
+; CHECK-NEXT: ldrh.w lr, [r3, #14]
; CHECK-NEXT: vldrw.u32 q0, [r0], #8
-; CHECK-NEXT: ldrh.w r9, [r7, #12]
-; CHECK-NEXT: ldrh.w r10, [r7, #10]
-; CHECK-NEXT: ldrh r4, [r7, #8]
-; CHECK-NEXT: ldrh r3, [r7, #6]
-; CHECK-NEXT: ldrh r6, [r7, #4]
-; CHECK-NEXT: ldrh.w r11, [r7, #2]
-; CHECK-NEXT: ldrh.w r8, [r7]
+; CHECK-NEXT: ldrh.w r8, [r3, #12]
+; CHECK-NEXT: ldrh r7, [r3, #10]
+; CHECK-NEXT: ldrh r4, [r3, #8]
+; CHECK-NEXT: ldrh r6, [r3, #6]
+; CHECK-NEXT: ldrh.w r9, [r3, #4]
+; CHECK-NEXT: ldrh.w r11, [r3, #2]
+; CHECK-NEXT: ldrh.w r10, [r3]
; CHECK-NEXT: vstrb.8 q0, [r1], #8
; CHECK-NEXT: vldrw.u32 q0, [r5]
; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: adds r0, r5, #2
; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: vmul.f16 q0, q0, r8
+; CHECK-NEXT: vmul.f16 q0, q0, r10
; CHECK-NEXT: adds r0, r5, #6
; CHECK-NEXT: vfma.f16 q0, q1, r11
; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
-; CHECK-NEXT: vfma.f16 q0, q1, r6
+; CHECK-NEXT: vfma.f16 q0, q1, r9
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: add.w r0, r5, #10
-; CHECK-NEXT: vfma.f16 q0, q1, r3
+; CHECK-NEXT: vfma.f16 q0, q1, r6
; CHECK-NEXT: vldrw.u32 q1, [r5, #8]
; CHECK-NEXT: vfma.f16 q0, q1, r4
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: add.w r0, r5, #14
-; CHECK-NEXT: vfma.f16 q0, q1, r10
+; CHECK-NEXT: vfma.f16 q0, q1, r7
; CHECK-NEXT: vldrw.u32 q1, [r5, #12]
; CHECK-NEXT: adds r5, #16
-; CHECK-NEXT: vfma.f16 q0, q1, r9
+; CHECK-NEXT: vfma.f16 q0, q1, r8
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vfma.f16 q0, q1, lr
@@ -1083,44 +1083,40 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ %bb.7: @ %for.body.preheader
; CHECK-NEXT: @ in Loop: Header=BB16_6 Depth=1
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
-; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: dls lr, r0
; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: .LBB16_8: @ %for.body
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: ldrh r0, [r3, #16]
+; CHECK-NEXT: ldrh r0, [r6], #16
; CHECK-NEXT: vldrw.u32 q1, [r5]
; CHECK-NEXT: adds r4, r5, #2
-; CHECK-NEXT: mov r9, r6
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: vldrw.u32 q1, [r4]
-; CHECK-NEXT: ldrh r0, [r3, #18]
+; CHECK-NEXT: ldrh r0, [r6, #-14]
; CHECK-NEXT: adds r4, r5, #6
-; CHECK-NEXT: adds r6, #16
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: ldrh r0, [r3, #20]
+; CHECK-NEXT: ldrh r0, [r6, #-12]
; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: vldrw.u32 q1, [r4]
-; CHECK-NEXT: ldrh r0, [r3, #22]
+; CHECK-NEXT: ldrh r0, [r6, #-10]
; CHECK-NEXT: add.w r4, r5, #10
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: ldrh r0, [r3, #24]
+; CHECK-NEXT: ldrh r0, [r6, #-8]
; CHECK-NEXT: vldrw.u32 q1, [r5, #8]
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: ldrh r0, [r3, #26]
; CHECK-NEXT: vldrw.u32 q1, [r4]
+; CHECK-NEXT: ldrh r0, [r6, #-6]
+; CHECK-NEXT: ldrh r4, [r6, #-2]
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: ldrh r0, [r3, #28]
+; CHECK-NEXT: ldrh r0, [r6, #-4]
; CHECK-NEXT: vldrw.u32 q1, [r5, #12]
-; CHECK-NEXT: ldrh r3, [r3, #30]
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: add.w r0, r5, #14
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: adds r5, #16
-; CHECK-NEXT: vfma.f16 q0, q1, r3
-; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: vfma.f16 q0, q1, r4
; CHECK-NEXT: le lr, .LBB16_8
; CHECK-NEXT: b .LBB16_4
; CHECK-NEXT: .LBB16_9: @ in Loop: Header=BB16_6 Depth=1
@@ -1132,9 +1128,9 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: .LBB16_11: @ %while.body76
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: ldrh r3, [r6], #2
+; CHECK-NEXT: ldrh r4, [r6], #2
; CHECK-NEXT: vldrh.u16 q1, [r0], #2
-; CHECK-NEXT: vfma.f16 q0, q1, r3
+; CHECK-NEXT: vfma.f16 q0, q1, r4
; CHECK-NEXT: le lr, .LBB16_11
; CHECK-NEXT: b .LBB16_3
; CHECK-NEXT: .LBB16_12: @ %if.end
diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
index b74776811ab610..808626d9a0aebe 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
-define arm_aapcs_vfpcc void @test_fadd(ptr noalias nocapture readonly noundef %A, float %B, ptr noalias nocapture %C, i32 %n) {
+define arm_aapcs_vfpcc void @test_fadd(ptr noalias nocapture readonly %A, float %B, ptr noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fadd:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1
@@ -1119,9 +1119,9 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: bx lr
entry:
%pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 1
- %i = load ptr, ptr %pState1, align 4, !noundef !0
+ %i = load ptr, ptr %pState1, align 4
%pCoeffs2 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 2
- %i1 = load ptr, ptr %pCoeffs2, align 4, !noundef !0
+ %i1 = load ptr, ptr %pCoeffs2, align 4
%numTaps3 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 0
%i2 = load i16, ptr %numTaps3, align 4
%conv = zext i16 %i2 to i32
@@ -2117,5 +2117,3 @@ declare void @llvm.assume(i1)
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>)
-
-!0 = !{}
diff --git a/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll b/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
index f09726f7abde94..5bd28470ef76be 100644
--- a/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
+++ b/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
@@ -371,7 +371,7 @@ return:
; Two phis should remain, one starting at %init, and one at %init1.
; Two increments should remain, one by %step and one by %step1.
; Five live-outs should remain.
-define i32 @isomorphic(i32 noundef %init, i32 noundef %step, i32 %lim) nounwind {
+define i32 @isomorphic(i32 %init, i32 %step, i32 %lim) nounwind {
; CHECK-LABEL: @isomorphic(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STEP1:%.*]] = add i32 [[STEP:%.*]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
index 49591ff3770ca8..49e9abcd9f9192 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
@@ -5,9 +5,9 @@ target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"
; Test case for https://github.com/llvm/llvm-project/issues/106417.
-define void @skip_free_iv_truncate(i16 noundef %x, ptr %A) #0 {
+define void @skip_free_iv_truncate(i16 %x, ptr %A) #0 {
; CHECK-LABEL: define void @skip_free_iv_truncate(
-; CHECK-SAME: i16 noundef [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: i16 [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[X_I32:%.*]] = sext i16 [[X]] to i32
; CHECK-NEXT: [[X_I64:%.*]] = sext i16 [[X]] to i64
diff --git a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
index aae2274926fef7..bc74742d952abe 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
@@ -706,9 +706,9 @@ exit:
ret void
}
-define void @wombat(i32 noundef %arg, ptr %dst) #1 {
+define void @wombat(i32 %arg, ptr %dst) #1 {
; CHECK-LABEL: define void @wombat(
-; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1:[0-9]+]] {
+; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
@@ -780,9 +780,9 @@ exit:
ret void
}
-define void @wombat2(i32 noundef %arg, ptr %dst) #1 {
+define void @wombat2(i32 %arg, ptr %dst) #1 {
; CHECK-LABEL: define void @wombat2(
-; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
+; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
@@ -857,9 +857,9 @@ exit:
}
-define void @with_dead_use(i32 noundef %arg, ptr %dst) #1 {
+define void @with_dead_use(i32 %arg, ptr %dst) #1 {
; CHECK-LABEL: define void @with_dead_use(
-; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
+; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
diff --git a/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
index 6d219fd341b3b8..7cf36fc669f37d 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
@@ -128,9 +128,9 @@ exit:
ret i32 0
}
-define void @test_scalar_cost_single_store_loop_invariant_cond(ptr noundef %dst, i1 %c) #0 {
+define void @test_scalar_cost_single_store_loop_invariant_cond(ptr %dst, i1 %c) #0 {
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_invariant_cond(
-; CHECK-SAME: ptr noundef [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
@@ -191,9 +191,9 @@ exit:
ret void
}
-define void @test_scalar_cost_single_store_loop_varying_cond(ptr noundef %dst, ptr noalias %src) #0 {
+define void @test_scalar_cost_single_store_loop_varying_cond(ptr %dst, ptr noalias %src) #0 {
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_varying_cond(
-; CHECK-SAME: ptr noundef [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
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