[llvm] [AArch64] Fix frame-pointer offset with hazard padding (PR #118091)

[Sander de Smalen via llvm-commits]

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@@ -3167,11 +3167,21 @@ static void computeCalleeSaveRegisterPairs(
             (RPI.isScalable() && RPI.Offset >= -256 && RPI.Offset <= 255)) &&
            "Offset out of bounds for LDP/STP immediate");
 
+    auto isFrameRecord = [&] {
+      if (RPI.isPaired())
+        return IsWindows ? RPI.Reg1 == AArch64::FP && RPI.Reg2 == AArch64::LR
+                         : RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP;
+      // -aarch64-stack-hazard-size=<val> disables register pairing, so look
+      // for the frame record as two unpaired registers.
+      if (AFI->hasStackHazardSlotIndex())
+        return i > 0 && RPI.Reg1 == AArch64::FP &&
+               CSI[i - 1].getReg() == AArch64::LR;
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sdesmalen-arm wrote:

> > Also, as it stands, your code would need updating to make this work for windows, for example.
> 
> I did check this on Windows and it's correct (probably should add a test 😅) On Linux this matches current reg = FP, previous reg = LR, on Windows it matches current reg = FP, next reg = LR, which works out as the correct offset in both cases (as Linux needs the post-increment offset, and Windows the pre-increment offset).

Right, that's probably because of the order they're iterated over is different. In that case, could we still remove the check for `hasStackHazardSlotIndex`?

https://github.com/llvm/llvm-project/pull/118091