[llvm] [AArch64] Fix frame-pointer offset with hazard padding (PR #118091)

[Sander de Smalen via llvm-commits]

================
@@ -3167,11 +3167,21 @@ static void computeCalleeSaveRegisterPairs(
             (RPI.isScalable() && RPI.Offset >= -256 && RPI.Offset <= 255)) &&
            "Offset out of bounds for LDP/STP immediate");
 
+    auto isFrameRecord = [&] {
+      if (RPI.isPaired())
+        return IsWindows ? RPI.Reg1 == AArch64::FP && RPI.Reg2 == AArch64::LR
+                         : RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP;
+      // -aarch64-stack-hazard-size=<val> disables register pairing, so look
+      // for the frame record as two unpaired registers.
+      if (AFI->hasStackHazardSlotIndex())
+        return i > 0 && RPI.Reg1 == AArch64::FP &&
+               CSI[i - 1].getReg() == AArch64::LR;
----------------
sdesmalen-arm wrote:

nit: Is it worth rewriting such that it doesn't depend on the reason why `RPI.isPaired()` is `false`?
Also, as it stands, your code would need updating to make this work for windows, for example.

I haven't tested the code below, but I'm thinking something like this:
```
unsigned Reg1, Reg2;
if (RPI.isPaired()) {
  Reg1 = RPI.Reg1;
  Reg2 = RPI.Reg2;
} else if (i > 0) {
  Reg1 = CSI[i-1].getReg();
  Reg2 = RPI.Reg1;
} else
  return false;
return IsWindows ? Reg1 == AArch64::FP && Reg2 == AArch64::LR
                 : Reg1 == AArch64::LR && Reg2 == AArch64::FP;
```

https://github.com/llvm/llvm-project/pull/118091