[llvm] [RISCV][Xqcicsr] Instructions have Side Effects (PR #118089)

[Sam Elliott via llvm-commits]

https://github.com/lenary created https://github.com/llvm/llvm-project/pull/118089

Xqcicsr was added in #117169. I missed that `hasSideEffects` was set to 0, rather than 1 (which all other CSR-modifying instructions have).

This has no effect on the current assembly-only support, but I think is worth fixing before I forget. I accidentally fixed the closing comment in 9300274a12d758368c036812d903b73d70d64ea4.

>From f758ec8040cb9f14b5f41799a127da78574db34b Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Fri, 29 Nov 2024 04:53:23 -0800
Subject: [PATCH] [RISCV][Xqcicsr] Instructions have Side Effects

Xqcicsr was added in #117169. I missed that `hasSideEffects` was set to
0, rather than 1 (which all other CSR-modifying instructions have).

This has no effect on the current assembly-only support, but I think is
worth fixing before I forget. I accidentally fixed the closing comment
in 9300274a12d758368c036812d903b73d70d64ea4.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 80d83fce038b29..3f53165d5235e6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -50,7 +50,7 @@ class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
   def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd),
                           (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
                           "$rd, $rs1, $rs2">;