[llvm] 9300274 - [RISCV][NFCI] Fix Xqci Line Endings
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 29 04:51:38 PST 2024
Author: Sam Elliott
Date: 2024-11-29T04:50:08-08:00
New Revision: 9300274a12d758368c036812d903b73d70d64ea4
URL: https://github.com/llvm/llvm-project/commit/9300274a12d758368c036812d903b73d70d64ea4
DIFF: https://github.com/llvm/llvm-project/commit/9300274a12d758368c036812d903b73d70d64ea4.diff
LOG: [RISCV][NFCI] Fix Xqci Line Endings
Changes the new files for `Xqci`, including `Xqcicsr` and `Xqcisls`, to
use Unix line endings rather than Windows line endings.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
llvm/test/MC/RISCV/xqcicsr-invalid.s
llvm/test/MC/RISCV/xqcicsr-valid.s
llvm/test/MC/RISCV/xqcisls-invalid.s
llvm/test/MC/RISCV/xqcisls-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 5f560aa0cc7bc0..80d83fce038b29 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1,74 +1,74 @@
-//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the vendor extensions defined by QUALCOMM.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Operand and SDNode transformation definitions.
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Instruction Formats
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Instruction Class Templates
-//===----------------------------------------------------------------------===//
-
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-class QCILoad_ScaleIdx<bits<4> func4, string opcodestr>
- : RVInstRBase<0b111, OPC_CUSTOM_0,
- (outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
- opcodestr, "$rd, $rs1, $rs2, $shamt"> {
- bits<3> shamt;
- let Inst{31-28} = func4;
- let Inst{27-25} = shamt;
-}
-}
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-// rd corresponds to the source for the store 'rs3' described in the spec.
-class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
- : RVInstRBase<0b110, OPC_CUSTOM_1, (outs),
- (ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
- opcodestr, "$rd, $rs1, $rs2, $shamt"> {
- bits<3> shamt;
- let Inst{31-28} = func4;
- let Inst{27-25} = shamt;
-}
-}
-
-//===----------------------------------------------------------------------===//
-// Instructions
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
- def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd),
- (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
- "$rd, $rs1, $rs2">;
-
- def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd),
- (ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri",
- "$rd, $rs1, $rs2">;
-} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
-} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr"
-
-let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in {
- def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">;
- def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">;
- def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">;
- def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">;
- def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">;
-
- def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">;
- def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">;
- def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">;
-} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls"
+//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by QUALCOMM.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction Formats
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+class QCILoad_ScaleIdx<bits<4> func4, string opcodestr>
+ : RVInstRBase<0b111, OPC_CUSTOM_0,
+ (outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
+ opcodestr, "$rd, $rs1, $rs2, $shamt"> {
+ bits<3> shamt;
+ let Inst{31-28} = func4;
+ let Inst{27-25} = shamt;
+}
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+// rd corresponds to the source for the store 'rs3' described in the spec.
+class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
+ : RVInstRBase<0b110, OPC_CUSTOM_1, (outs),
+ (ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
+ opcodestr, "$rd, $rs1, $rs2, $shamt"> {
+ bits<3> shamt;
+ let Inst{31-28} = func4;
+ let Inst{27-25} = shamt;
+}
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd),
+ (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
+ "$rd, $rs1, $rs2">;
+
+ def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd),
+ (ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri",
+ "$rd, $rs1, $rs2">;
+} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
+} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr"
+
+let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in {
+ def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">;
+ def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">;
+ def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">;
+ def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">;
+ def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">;
+
+ def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">;
+ def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">;
+ def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">;
+} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls"
diff --git a/llvm/test/MC/RISCV/xqcicsr-invalid.s b/llvm/test/MC/RISCV/xqcicsr-invalid.s
index 26fa26f7ff95f1..6d3d62d4b4b41f 100644
--- a/llvm/test/MC/RISCV/xqcicsr-invalid.s
+++ b/llvm/test/MC/RISCV/xqcicsr-invalid.s
@@ -1,27 +1,27 @@
-# Xqcicsr - Qualcomm uC CSR Extension
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicsr < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
-# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
-
-# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.csrrwr x10, x5, x0
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.csrrwr x10, x5
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
-qc.csrrwr x10, x5, x20
-
-
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.csrrwri x20, 31, x0
-
-# CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be an integer in the range [0, 31]
-qc.csrrwri x20, 45, x12
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.csrrwri x20, 23
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
-qc.csrrwri x30, 31, x12
+# Xqcicsr - Qualcomm uC CSR Extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicsr < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+
+# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
+qc.csrrwr x10, x5, x0
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.csrrwr x10, x5
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
+qc.csrrwr x10, x5, x20
+
+
+# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+qc.csrrwri x20, 31, x0
+
+# CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be an integer in the range [0, 31]
+qc.csrrwri x20, 45, x12
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.csrrwri x20, 23
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
+qc.csrrwri x30, 31, x12
diff --git a/llvm/test/MC/RISCV/xqcicsr-valid.s b/llvm/test/MC/RISCV/xqcicsr-valid.s
index a73e0079622578..1236dd622703d3 100644
--- a/llvm/test/MC/RISCV/xqcicsr-valid.s
+++ b/llvm/test/MC/RISCV/xqcicsr-valid.s
@@ -1,19 +1,19 @@
-# Xqcicsr - Qualcomm uC CSR Extension
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -riscv-no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-xqcicsr -M no-aliases --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-xqcicsr --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
-
-# CHECK-INST: qc.csrrwr a0, t0, s4
-# CHECK-ENC: encoding: [0x73,0x85,0x42,0x8d]
-qc.csrrwr x10, x5, x20
-
-# CHECK-INST: qc.csrrwri s4, 31, a2
-# CHECK-ENC: encoding: [0x73,0x8a,0xcf,0x8e]
-qc.csrrwri x20, 31, x12
+# Xqcicsr - Qualcomm uC CSR Extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcicsr -M no-aliases --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcicsr --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: qc.csrrwr a0, t0, s4
+# CHECK-ENC: encoding: [0x73,0x85,0x42,0x8d]
+qc.csrrwr x10, x5, x20
+
+# CHECK-INST: qc.csrrwri s4, 31, a2
+# CHECK-ENC: encoding: [0x73,0x8a,0xcf,0x8e]
+qc.csrrwri x20, 31, x12
diff --git a/llvm/test/MC/RISCV/xqcisls-invalid.s b/llvm/test/MC/RISCV/xqcisls-invalid.s
index 4cd2a14975a946..5e9e54812fee8f 100644
--- a/llvm/test/MC/RISCV/xqcisls-invalid.s
+++ b/llvm/test/MC/RISCV/xqcisls-invalid.s
@@ -1,132 +1,132 @@
-# Xqcisls - Qualcomm uC Scaled Load Store Extension
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisls < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
-# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisls < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
-
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.lrb x5, x2, x0, 4
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.lrb x5, x2, x4
-
-# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7]
-qc.lrb x5, x2, x4, 12
-
-# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
-qc.lrb x5, 2, x4, 4
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.lrb x5, x2, x4, 4
-
-
-# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
-qc.lrh x1, x12, x0, 2
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.lrh x1, x12, x6
-
-# CHECK-PLUS: :[[@LINE+1]]:21: error: immediate must be an integer in the range [0, 7]
-qc.lrh x1, x12, x6, 22
-
-# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
-qc.lrh x1, 12, x6, 2
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.lrh x1, x12, x6, 2
-
-
-# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
-qc.lrw x15, x7, x0, 1
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.lrw x15, x7, x14
-
-# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
-qc.lrw x15, x7, x14, 11
-
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
-qc.lrw x15, 7, x14, 1
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.lrw x15, x7, x14, 1
-
-
-# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
-qc.lrbu x9, x11, x0, 7
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.lrbu x9, x11, x4
-
-# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
-qc.lrbu x9, x11, x4, 37
-
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
-qc.lrbu x9, 11, x4, 7
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.lrbu x9, x11, x4, 7
-
-
-# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
-qc.lrhu x16, x6, x0, 4
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.lrhu x16, x6, x10
-
-# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7]
-qc.lrhu x16, x6, x10, 44
-
-# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
-qc.lrhu x16, 6, x10, 4
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.lrhu x16, x6, x10, 4
-
-
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.srb x0, x2, x0, 3
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.srb x0, x2, x8
-
-# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7]
-qc.srb x0, x2, x8, 93
-
-# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
-qc.srb x0, 2, x8, 3
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.srb x0, x2, x8, 3
-
-
-# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
-qc.srh x13, x0, x0, 6
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.srh x13, x0, x20
-
-# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
-qc.srh x13, x0, x20, 76
-
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
-qc.srh x13, 0, x20, 6
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.srh x13, x0, x20, 6
-
-
-# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
-qc.srw x17, x18, x0, 0
-
-# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.srw x17, x18, x19
-
-# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7]
-qc.srw x17, x18, x19, 10
-
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
-qc.srw x17, 18, x19, 0
-
-# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-qc.srw x17, x18, x19, 0
+# Xqcisls - Qualcomm uC Scaled Load Store Extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisls < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisls < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.lrb x5, x2, x0, 4
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.lrb x5, x2, x4
+
+# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7]
+qc.lrb x5, x2, x4, 12
+
+# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.lrb x5, 2, x4, 4
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.lrb x5, x2, x4, 4
+
+
+# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.lrh x1, x12, x0, 2
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.lrh x1, x12, x6
+
+# CHECK-PLUS: :[[@LINE+1]]:21: error: immediate must be an integer in the range [0, 7]
+qc.lrh x1, x12, x6, 22
+
+# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.lrh x1, 12, x6, 2
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.lrh x1, x12, x6, 2
+
+
+# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.lrw x15, x7, x0, 1
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.lrw x15, x7, x14
+
+# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
+qc.lrw x15, x7, x14, 11
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.lrw x15, 7, x14, 1
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.lrw x15, x7, x14, 1
+
+
+# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+qc.lrbu x9, x11, x0, 7
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.lrbu x9, x11, x4
+
+# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
+qc.lrbu x9, x11, x4, 37
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.lrbu x9, 11, x4, 7
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.lrbu x9, x11, x4, 7
+
+
+# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+qc.lrhu x16, x6, x0, 4
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.lrhu x16, x6, x10
+
+# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7]
+qc.lrhu x16, x6, x10, 44
+
+# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+qc.lrhu x16, 6, x10, 4
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.lrhu x16, x6, x10, 4
+
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.srb x0, x2, x0, 3
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.srb x0, x2, x8
+
+# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7]
+qc.srb x0, x2, x8, 93
+
+# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.srb x0, 2, x8, 3
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.srb x0, x2, x8, 3
+
+
+# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.srh x13, x0, x0, 6
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.srh x13, x0, x20
+
+# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
+qc.srh x13, x0, x20, 76
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.srh x13, 0, x20, 6
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.srh x13, x0, x20, 6
+
+
+# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+qc.srw x17, x18, x0, 0
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.srw x17, x18, x19
+
+# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7]
+qc.srw x17, x18, x19, 10
+
+# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.srw x17, 18, x19, 0
+
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+qc.srw x17, x18, x19, 0
diff --git a/llvm/test/MC/RISCV/xqcisls-valid.s b/llvm/test/MC/RISCV/xqcisls-valid.s
index ae8370afc6c6e2..32f64a82985ce6 100644
--- a/llvm/test/MC/RISCV/xqcisls-valid.s
+++ b/llvm/test/MC/RISCV/xqcisls-valid.s
@@ -1,43 +1,43 @@
-# Xqcisls - Qualcomm uC Scaled Load Store Extension
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -riscv-no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \
-# RUN: | llvm-objdump --mattr=+experimental-xqcisls -M no-aliases --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \
-# RUN: | llvm-objdump --mattr=+experimental-xqcisls --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
-
-# CHECK-INST: qc.lrb t0, sp, tp, 4
-# CHECK-ENC: encoding: [0x8b,0x72,0x41,0x88]
-qc.lrb x5, x2, x4, 4
-
-# CHECK-INST: qc.lrh ra, a2, t1, 2
-# CHECK-ENC: encoding: [0x8b,0x70,0x66,0x94]
-qc.lrh x1, x12, x6, 2
-
-# CHECK-INST: qc.lrw a5, t2, a4, 1
-# CHECK-ENC: encoding: [0x8b,0xf7,0xe3,0xa2]
-qc.lrw x15, x7, x14, 1
-
-# CHECK-INST: qc.lrbu s1, a1, tp, 7
-# CHECK-ENC: encoding: [0x8b,0xf4,0x45,0xbe]
-qc.lrbu x9, x11, x4, 7
-
-# CHECK-INST: qc.lrhu a6, t1, a0, 4
-# CHECK-ENC: encoding: [0x0b,0x78,0xa3,0xc8]
-qc.lrhu x16, x6, x10, 4
-
-# CHECK-INST: qc.srb zero, sp, s0, 3
-# CHECK-ENC: encoding: [0x2b,0x60,0x81,0xd6]
-qc.srb x0, x2, x8, 3
-
-# CHECK-INST: qc.srh a3, zero, s4, 6
-# CHECK-ENC: encoding: [0xab,0x66,0x40,0xed]
-qc.srh x13, x0, x20, 6
-
-# CHECK-INST: qc.srw a7, s2, s3, 0
-# CHECK-ENC: encoding: [0xab,0x68,0x39,0xf1]
-qc.srw x17, x18, x19, 0
+# Xqcisls - Qualcomm uC Scaled Load Store Extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcisls -M no-aliases --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcisls --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: qc.lrb t0, sp, tp, 4
+# CHECK-ENC: encoding: [0x8b,0x72,0x41,0x88]
+qc.lrb x5, x2, x4, 4
+
+# CHECK-INST: qc.lrh ra, a2, t1, 2
+# CHECK-ENC: encoding: [0x8b,0x70,0x66,0x94]
+qc.lrh x1, x12, x6, 2
+
+# CHECK-INST: qc.lrw a5, t2, a4, 1
+# CHECK-ENC: encoding: [0x8b,0xf7,0xe3,0xa2]
+qc.lrw x15, x7, x14, 1
+
+# CHECK-INST: qc.lrbu s1, a1, tp, 7
+# CHECK-ENC: encoding: [0x8b,0xf4,0x45,0xbe]
+qc.lrbu x9, x11, x4, 7
+
+# CHECK-INST: qc.lrhu a6, t1, a0, 4
+# CHECK-ENC: encoding: [0x0b,0x78,0xa3,0xc8]
+qc.lrhu x16, x6, x10, 4
+
+# CHECK-INST: qc.srb zero, sp, s0, 3
+# CHECK-ENC: encoding: [0x2b,0x60,0x81,0xd6]
+qc.srb x0, x2, x8, 3
+
+# CHECK-INST: qc.srh a3, zero, s4, 6
+# CHECK-ENC: encoding: [0xab,0x66,0x40,0xed]
+qc.srh x13, x0, x20, 6
+
+# CHECK-INST: qc.srw a7, s2, s3, 0
+# CHECK-ENC: encoding: [0xab,0x68,0x39,0xf1]
+qc.srw x17, x18, x19, 0
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