[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

I've not had chance to look at the PR yet but from a high level I think having an ISD node that matches the definition of the intrinsic this closely is going to make legalisation and selection harder than necessary.  I was expecting the ISD node(s) to be signed operations because then you open the possibility of the operands having different element types which will make it much easier to legalise efficiently as well as providing a route to potentially isel directly.

Specifically, I'm suggesting you follow a similar idiom as used by other nodes where implicitly extension is beneficial (e.g. MULH, ABD) and implement `PARTIAL_VECREDUCE_SADD` and `PARTIAL_VECREDUCE_UADD`.

https://github.com/llvm/llvm-project/pull/117185