[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Benjamin Maxwell via llvm-commits]

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@@ -1595,10 +1595,11 @@ class SelectionDAG {
   /// the target's desired shift amount type.
   SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
 
-  /// Create the DAG equivalent of vector_partial_reduce where Op1 and Op2 are
-  /// its operands and ReducedTY is the intrinsic's return type.
-  SDValue getPartialReduceAdd(SDLoc DL, EVT ReducedTy, SDValue Op1,
-                              SDValue Op2);
+  /// Expands PARTIAL_REDUCE_ADD nodes which can't be lowered.
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MacDue wrote:

nit: I don't think "which can't be lowered" is relevant to this function, I think it's better to say what the function does. Maybe something "Expands PARTIAL_REDUCE_ADD nodes to a sequence of subvector extracts followed by vector adds"

https://github.com/llvm/llvm-project/pull/117185