[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)
Benjamin Maxwell via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 28 02:16:53 PST 2024
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@@ -1595,10 +1595,10 @@ class SelectionDAG {
/// the target's desired shift amount type.
SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
- /// Create the DAG equivalent of vector_partial_reduce where Op1 and Op2 are
- /// its operands and ReducedTY is the intrinsic's return type.
- SDValue getPartialReduceAdd(SDLoc DL, EVT ReducedTy, SDValue Op1,
- SDValue Op2);
+ /// Expands partial reduce node which can't be lowered to wide add or dot
+ /// product instruction(s)
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MacDue wrote:
SelectionDAG.h is not target specific, so I don't think this should mention the wide add/dot product lowering (which is only for AArch64). Also, could you document the operands (ReducedTY, Op1, Op2)?
https://github.com/llvm/llvm-project/pull/117185
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