[llvm] 93f7398 - [RISCV] Add TuneDisableLatencySchedHeuristic

via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 27 23:16:27 PST 2024


Author: Pengcheng Wang
Date: 2024-11-28T15:16:23+08:00
New Revision: 93f7398bdba9d1547df21156db4d5393f0ab5ec8

URL: https://github.com/llvm/llvm-project/commit/93f7398bdba9d1547df21156db4d5393f0ab5ec8
DIFF: https://github.com/llvm/llvm-project/commit/93f7398bdba9d1547df21156db4d5393f0ab5ec8.diff

LOG: [RISCV] Add TuneDisableLatencySchedHeuristic

This tune feature will disable latency scheduling heuristic.

This can reduce the number of spills/reloads but will cause some
regressions on some cores.

CPU may add this tune feature if they find it's profitable.

Reviewers: lukel97, michaelmaitland, asb, preames, mshockwave, topperc

Reviewed By: michaelmaitland, mshockwave, topperc

Pull Request: https://github.com/llvm/llvm-project/pull/115858

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFeatures.td
    llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a579d9d0282d52..48ae378c0e67ef 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1401,6 +1401,10 @@ def FeatureUnalignedVectorMem
 def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 
+def TuneDisableLatencySchedHeuristic
+    : SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
+                       "Disable latency scheduling heuristic">;
+
 def TunePredictableSelectIsExpensive
     : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
                        "Prefer likely predicted branches over selects">;

diff  --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 426d3682049046..38443e8646de40 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -203,6 +203,10 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
   Policy.OnlyTopDown = false;
   Policy.OnlyBottomUp = false;
 
+  // Disabling the latency heuristic can reduce the number of spills/reloads but
+  // will cause some regressions on some cores.
+  Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
+
   // Spilling is generally expensive on all RISC-V cores, so always enable
   // register-pressure tracking. This will increase compile time.
   Policy.ShouldTrackPressure = true;


        


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