[llvm] [RegAlloc][RISCV] Increase the spill weight by target factor (PR #113675)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 27 13:21:51 PST 2024
================
@@ -763,11 +757,7 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: fsrm a1
-; CHECK-NEXT: addi a1, sp, 16
----------------
preames wrote:
This is weird? Is fsrm maybe marked as invalidating vector registers? We have a spill immediately before a fill from the same address a few lines later?
https://github.com/llvm/llvm-project/pull/113675
More information about the llvm-commits
mailing list