[llvm] dae9cf3 - [RISCV] Move scalar llvm.exp10 tests into half/float/double-intrinsics.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 27 10:25:35 PST 2024
Author: Craig Topper
Date: 2024-11-27T10:24:33-08:00
New Revision: dae9cf3816bbb2b4589d258a82e6ac90fad71485
URL: https://github.com/llvm/llvm-project/commit/dae9cf3816bbb2b4589d258a82e6ac90fad71485
DIFF: https://github.com/llvm/llvm-project/commit/dae9cf3816bbb2b4589d258a82e6ac90fad71485.diff
LOG: [RISCV] Move scalar llvm.exp10 tests into half/float/double-intrinsics.ll. NFC
Improves coverage for more configurations.
Added:
Modified:
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/float-intrinsics.ll
llvm/test/CodeGen/RISCV/half-intrinsics.ll
llvm/test/CodeGen/RISCV/llvm.exp10.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index ebeca7c0c362ae..8980520e557066 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -453,6 +453,45 @@ define double @exp2_f64(double %a) nounwind {
ret double %1
}
+define double @exp10_f64(double %a) nounwind {
+; CHECKIFD-LABEL: exp10_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: tail exp10
+;
+; RV32IZFINXZDINX-LABEL: exp10_f64:
+; RV32IZFINXZDINX: # %bb.0:
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: call exp10
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: ret
+;
+; RV64IZFINXZDINX-LABEL: exp10_f64:
+; RV64IZFINXZDINX: # %bb.0:
+; RV64IZFINXZDINX-NEXT: tail exp10
+;
+; RV32I-LABEL: exp10_f64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call exp10
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: exp10_f64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call exp10
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %1 = call double @llvm.exp10.f64(double %a)
+ ret double %1
+}
+
declare double @llvm.log.f64(double)
define double @log_f64(double %a) nounwind {
@@ -844,16 +883,16 @@ define double @floor_f64(double %a) nounwind {
;
; RV64IFD-LABEL: floor_f64:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI17_0)
-; RV64IFD-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
+; RV64IFD-NEXT: lui a0, %hi(.LCPI18_0)
+; RV64IFD-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV64IFD-NEXT: fabs.d fa4, fa0
; RV64IFD-NEXT: flt.d a0, fa4, fa5
-; RV64IFD-NEXT: beqz a0, .LBB17_2
+; RV64IFD-NEXT: beqz a0, .LBB18_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
; RV64IFD-NEXT: fcvt.d.l fa5, a0, rdn
; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0
-; RV64IFD-NEXT: .LBB17_2:
+; RV64IFD-NEXT: .LBB18_2:
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: floor_f64:
@@ -871,12 +910,12 @@ define double @floor_f64(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
-; RV64IZFINXZDINX-NEXT: beqz a1, .LBB17_2
+; RV64IZFINXZDINX-NEXT: beqz a1, .LBB18_2
; RV64IZFINXZDINX-NEXT: # %bb.1:
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rdn
; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rdn
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT: .LBB17_2:
+; RV64IZFINXZDINX-NEXT: .LBB18_2:
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: floor_f64:
@@ -909,16 +948,16 @@ define double @ceil_f64(double %a) nounwind {
;
; RV64IFD-LABEL: ceil_f64:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI18_0)
-; RV64IFD-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
+; RV64IFD-NEXT: lui a0, %hi(.LCPI19_0)
+; RV64IFD-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV64IFD-NEXT: fabs.d fa4, fa0
; RV64IFD-NEXT: flt.d a0, fa4, fa5
-; RV64IFD-NEXT: beqz a0, .LBB18_2
+; RV64IFD-NEXT: beqz a0, .LBB19_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup
; RV64IFD-NEXT: fcvt.d.l fa5, a0, rup
; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0
-; RV64IFD-NEXT: .LBB18_2:
+; RV64IFD-NEXT: .LBB19_2:
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: ceil_f64:
@@ -936,12 +975,12 @@ define double @ceil_f64(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
-; RV64IZFINXZDINX-NEXT: beqz a1, .LBB18_2
+; RV64IZFINXZDINX-NEXT: beqz a1, .LBB19_2
; RV64IZFINXZDINX-NEXT: # %bb.1:
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rup
; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rup
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT: .LBB18_2:
+; RV64IZFINXZDINX-NEXT: .LBB19_2:
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: ceil_f64:
@@ -974,16 +1013,16 @@ define double @trunc_f64(double %a) nounwind {
;
; RV64IFD-LABEL: trunc_f64:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI19_0)
-; RV64IFD-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
+; RV64IFD-NEXT: lui a0, %hi(.LCPI20_0)
+; RV64IFD-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV64IFD-NEXT: fabs.d fa4, fa0
; RV64IFD-NEXT: flt.d a0, fa4, fa5
-; RV64IFD-NEXT: beqz a0, .LBB19_2
+; RV64IFD-NEXT: beqz a0, .LBB20_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: fcvt.d.l fa5, a0, rtz
; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0
-; RV64IFD-NEXT: .LBB19_2:
+; RV64IFD-NEXT: .LBB20_2:
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: trunc_f64:
@@ -1001,12 +1040,12 @@ define double @trunc_f64(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
-; RV64IZFINXZDINX-NEXT: beqz a1, .LBB19_2
+; RV64IZFINXZDINX-NEXT: beqz a1, .LBB20_2
; RV64IZFINXZDINX-NEXT: # %bb.1:
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rtz
; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rtz
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT: .LBB19_2:
+; RV64IZFINXZDINX-NEXT: .LBB20_2:
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: trunc_f64:
@@ -1039,16 +1078,16 @@ define double @rint_f64(double %a) nounwind {
;
; RV64IFD-LABEL: rint_f64:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI20_0)
-; RV64IFD-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
+; RV64IFD-NEXT: lui a0, %hi(.LCPI21_0)
+; RV64IFD-NEXT: fld fa5, %lo(.LCPI21_0)(a0)
; RV64IFD-NEXT: fabs.d fa4, fa0
; RV64IFD-NEXT: flt.d a0, fa4, fa5
-; RV64IFD-NEXT: beqz a0, .LBB20_2
+; RV64IFD-NEXT: beqz a0, .LBB21_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0
; RV64IFD-NEXT: fcvt.d.l fa5, a0
; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0
-; RV64IFD-NEXT: .LBB20_2:
+; RV64IFD-NEXT: .LBB21_2:
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: rint_f64:
@@ -1066,12 +1105,12 @@ define double @rint_f64(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
-; RV64IZFINXZDINX-NEXT: beqz a1, .LBB20_2
+; RV64IZFINXZDINX-NEXT: beqz a1, .LBB21_2
; RV64IZFINXZDINX-NEXT: # %bb.1:
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0
; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT: .LBB20_2:
+; RV64IZFINXZDINX-NEXT: .LBB21_2:
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: rint_f64:
@@ -1145,16 +1184,16 @@ define double @round_f64(double %a) nounwind {
;
; RV64IFD-LABEL: round_f64:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI22_0)
-; RV64IFD-NEXT: fld fa5, %lo(.LCPI22_0)(a0)
+; RV64IFD-NEXT: lui a0, %hi(.LCPI23_0)
+; RV64IFD-NEXT: fld fa5, %lo(.LCPI23_0)(a0)
; RV64IFD-NEXT: fabs.d fa4, fa0
; RV64IFD-NEXT: flt.d a0, fa4, fa5
-; RV64IFD-NEXT: beqz a0, .LBB22_2
+; RV64IFD-NEXT: beqz a0, .LBB23_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
; RV64IFD-NEXT: fcvt.d.l fa5, a0, rmm
; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0
-; RV64IFD-NEXT: .LBB22_2:
+; RV64IFD-NEXT: .LBB23_2:
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: round_f64:
@@ -1172,12 +1211,12 @@ define double @round_f64(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
-; RV64IZFINXZDINX-NEXT: beqz a1, .LBB22_2
+; RV64IZFINXZDINX-NEXT: beqz a1, .LBB23_2
; RV64IZFINXZDINX-NEXT: # %bb.1:
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rmm
; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rmm
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT: .LBB22_2:
+; RV64IZFINXZDINX-NEXT: .LBB23_2:
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: round_f64:
@@ -1210,16 +1249,16 @@ define double @roundeven_f64(double %a) nounwind {
;
; RV64IFD-LABEL: roundeven_f64:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI23_0)
-; RV64IFD-NEXT: fld fa5, %lo(.LCPI23_0)(a0)
+; RV64IFD-NEXT: lui a0, %hi(.LCPI24_0)
+; RV64IFD-NEXT: fld fa5, %lo(.LCPI24_0)(a0)
; RV64IFD-NEXT: fabs.d fa4, fa0
; RV64IFD-NEXT: flt.d a0, fa4, fa5
-; RV64IFD-NEXT: beqz a0, .LBB23_2
+; RV64IFD-NEXT: beqz a0, .LBB24_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne
; RV64IFD-NEXT: fcvt.d.l fa5, a0, rne
; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0
-; RV64IFD-NEXT: .LBB23_2:
+; RV64IFD-NEXT: .LBB24_2:
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: roundeven_f64:
@@ -1237,12 +1276,12 @@ define double @roundeven_f64(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: slli a1, a1, 52
; RV64IZFINXZDINX-NEXT: fabs.d a2, a0
; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1
-; RV64IZFINXZDINX-NEXT: beqz a1, .LBB23_2
+; RV64IZFINXZDINX-NEXT: beqz a1, .LBB24_2
; RV64IZFINXZDINX-NEXT: # %bb.1:
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rne
; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rne
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT: .LBB23_2:
+; RV64IZFINXZDINX-NEXT: .LBB24_2:
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: roundeven_f64:
@@ -1524,11 +1563,11 @@ define i1 @isnan_d_fpclass(double %x) {
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: lui a2, 524032
-; RV32I-NEXT: beq a1, a2, .LBB29_2
+; RV32I-NEXT: beq a1, a2, .LBB30_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a2, a1
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB29_2:
+; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index d42afd504e5dc5..ec6aa54ec1e414 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -420,6 +420,44 @@ define float @exp2_f32(float %a) nounwind {
ret float %1
}
+define float @exp10_f32(float %a) nounwind {
+; RV32IF-LABEL: exp10_f32:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: tail exp10f
+;
+; RV32IZFINX-LABEL: exp10_f32:
+; RV32IZFINX: # %bb.0:
+; RV32IZFINX-NEXT: tail exp10f
+;
+; RV64IF-LABEL: exp10_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: tail exp10f
+;
+; RV64IZFINX-LABEL: exp10_f32:
+; RV64IZFINX: # %bb.0:
+; RV64IZFINX-NEXT: tail exp10f
+;
+; RV32I-LABEL: exp10_f32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call exp10f
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: exp10_f32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call exp10f
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %1 = call float @llvm.exp10.f32(float %a)
+ ret float %1
+}
+
declare float @llvm.log.f32(float)
define float @log_f32(float %a) nounwind {
@@ -834,12 +872,12 @@ define float @floor_f32(float %a) nounwind {
; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5
-; RV32IF-NEXT: beqz a0, .LBB17_2
+; RV32IF-NEXT: beqz a0, .LBB18_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn
; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV32IF-NEXT: .LBB17_2:
+; RV32IF-NEXT: .LBB18_2:
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: floor_f32:
@@ -847,12 +885,12 @@ define float @floor_f32(float %a) nounwind {
; RV32IZFINX-NEXT: lui a1, 307200
; RV32IZFINX-NEXT: fabs.s a2, a0
; RV32IZFINX-NEXT: flt.s a1, a2, a1
-; RV32IZFINX-NEXT: beqz a1, .LBB17_2
+; RV32IZFINX-NEXT: beqz a1, .LBB18_2
; RV32IZFINX-NEXT: # %bb.1:
; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rdn
; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rdn
; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV32IZFINX-NEXT: .LBB17_2:
+; RV32IZFINX-NEXT: .LBB18_2:
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: floor_f32:
@@ -861,12 +899,12 @@ define float @floor_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x fa5, a0
; RV64IF-NEXT: fabs.s fa4, fa0
; RV64IF-NEXT: flt.s a0, fa4, fa5
-; RV64IF-NEXT: beqz a0, .LBB17_2
+; RV64IF-NEXT: beqz a0, .LBB18_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV64IF-NEXT: fcvt.s.w fa5, a0, rdn
; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV64IF-NEXT: .LBB17_2:
+; RV64IF-NEXT: .LBB18_2:
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: floor_f32:
@@ -874,12 +912,12 @@ define float @floor_f32(float %a) nounwind {
; RV64IZFINX-NEXT: lui a1, 307200
; RV64IZFINX-NEXT: fabs.s a2, a0
; RV64IZFINX-NEXT: flt.s a1, a2, a1
-; RV64IZFINX-NEXT: beqz a1, .LBB17_2
+; RV64IZFINX-NEXT: beqz a1, .LBB18_2
; RV64IZFINX-NEXT: # %bb.1:
; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rdn
; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rdn
; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV64IZFINX-NEXT: .LBB17_2:
+; RV64IZFINX-NEXT: .LBB18_2:
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: floor_f32:
@@ -912,12 +950,12 @@ define float @ceil_f32(float %a) nounwind {
; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5
-; RV32IF-NEXT: beqz a0, .LBB18_2
+; RV32IF-NEXT: beqz a0, .LBB19_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
; RV32IF-NEXT: fcvt.s.w fa5, a0, rup
; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV32IF-NEXT: .LBB18_2:
+; RV32IF-NEXT: .LBB19_2:
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: ceil_f32:
@@ -925,12 +963,12 @@ define float @ceil_f32(float %a) nounwind {
; RV32IZFINX-NEXT: lui a1, 307200
; RV32IZFINX-NEXT: fabs.s a2, a0
; RV32IZFINX-NEXT: flt.s a1, a2, a1
-; RV32IZFINX-NEXT: beqz a1, .LBB18_2
+; RV32IZFINX-NEXT: beqz a1, .LBB19_2
; RV32IZFINX-NEXT: # %bb.1:
; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rup
; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rup
; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV32IZFINX-NEXT: .LBB18_2:
+; RV32IZFINX-NEXT: .LBB19_2:
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: ceil_f32:
@@ -939,12 +977,12 @@ define float @ceil_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x fa5, a0
; RV64IF-NEXT: fabs.s fa4, fa0
; RV64IF-NEXT: flt.s a0, fa4, fa5
-; RV64IF-NEXT: beqz a0, .LBB18_2
+; RV64IF-NEXT: beqz a0, .LBB19_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rup
; RV64IF-NEXT: fcvt.s.w fa5, a0, rup
; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV64IF-NEXT: .LBB18_2:
+; RV64IF-NEXT: .LBB19_2:
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: ceil_f32:
@@ -952,12 +990,12 @@ define float @ceil_f32(float %a) nounwind {
; RV64IZFINX-NEXT: lui a1, 307200
; RV64IZFINX-NEXT: fabs.s a2, a0
; RV64IZFINX-NEXT: flt.s a1, a2, a1
-; RV64IZFINX-NEXT: beqz a1, .LBB18_2
+; RV64IZFINX-NEXT: beqz a1, .LBB19_2
; RV64IZFINX-NEXT: # %bb.1:
; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rup
; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rup
; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV64IZFINX-NEXT: .LBB18_2:
+; RV64IZFINX-NEXT: .LBB19_2:
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: ceil_f32:
@@ -990,12 +1028,12 @@ define float @trunc_f32(float %a) nounwind {
; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5
-; RV32IF-NEXT: beqz a0, .LBB19_2
+; RV32IF-NEXT: beqz a0, .LBB20_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz
; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV32IF-NEXT: .LBB19_2:
+; RV32IF-NEXT: .LBB20_2:
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: trunc_f32:
@@ -1003,12 +1041,12 @@ define float @trunc_f32(float %a) nounwind {
; RV32IZFINX-NEXT: lui a1, 307200
; RV32IZFINX-NEXT: fabs.s a2, a0
; RV32IZFINX-NEXT: flt.s a1, a2, a1
-; RV32IZFINX-NEXT: beqz a1, .LBB19_2
+; RV32IZFINX-NEXT: beqz a1, .LBB20_2
; RV32IZFINX-NEXT: # %bb.1:
; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rtz
; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rtz
; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV32IZFINX-NEXT: .LBB19_2:
+; RV32IZFINX-NEXT: .LBB20_2:
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: trunc_f32:
@@ -1017,12 +1055,12 @@ define float @trunc_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x fa5, a0
; RV64IF-NEXT: fabs.s fa4, fa0
; RV64IF-NEXT: flt.s a0, fa4, fa5
-; RV64IF-NEXT: beqz a0, .LBB19_2
+; RV64IF-NEXT: beqz a0, .LBB20_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: fcvt.s.w fa5, a0, rtz
; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV64IF-NEXT: .LBB19_2:
+; RV64IF-NEXT: .LBB20_2:
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: trunc_f32:
@@ -1030,12 +1068,12 @@ define float @trunc_f32(float %a) nounwind {
; RV64IZFINX-NEXT: lui a1, 307200
; RV64IZFINX-NEXT: fabs.s a2, a0
; RV64IZFINX-NEXT: flt.s a1, a2, a1
-; RV64IZFINX-NEXT: beqz a1, .LBB19_2
+; RV64IZFINX-NEXT: beqz a1, .LBB20_2
; RV64IZFINX-NEXT: # %bb.1:
; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rtz
; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rtz
; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV64IZFINX-NEXT: .LBB19_2:
+; RV64IZFINX-NEXT: .LBB20_2:
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: trunc_f32:
@@ -1068,12 +1106,12 @@ define float @rint_f32(float %a) nounwind {
; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5
-; RV32IF-NEXT: beqz a0, .LBB20_2
+; RV32IF-NEXT: beqz a0, .LBB21_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0
; RV32IF-NEXT: fcvt.s.w fa5, a0
; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV32IF-NEXT: .LBB20_2:
+; RV32IF-NEXT: .LBB21_2:
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: rint_f32:
@@ -1081,12 +1119,12 @@ define float @rint_f32(float %a) nounwind {
; RV32IZFINX-NEXT: lui a1, 307200
; RV32IZFINX-NEXT: fabs.s a2, a0
; RV32IZFINX-NEXT: flt.s a1, a2, a1
-; RV32IZFINX-NEXT: beqz a1, .LBB20_2
+; RV32IZFINX-NEXT: beqz a1, .LBB21_2
; RV32IZFINX-NEXT: # %bb.1:
; RV32IZFINX-NEXT: fcvt.w.s a1, a0
; RV32IZFINX-NEXT: fcvt.s.w a1, a1
; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV32IZFINX-NEXT: .LBB20_2:
+; RV32IZFINX-NEXT: .LBB21_2:
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: rint_f32:
@@ -1095,12 +1133,12 @@ define float @rint_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x fa5, a0
; RV64IF-NEXT: fabs.s fa4, fa0
; RV64IF-NEXT: flt.s a0, fa4, fa5
-; RV64IF-NEXT: beqz a0, .LBB20_2
+; RV64IF-NEXT: beqz a0, .LBB21_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0
; RV64IF-NEXT: fcvt.s.w fa5, a0
; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV64IF-NEXT: .LBB20_2:
+; RV64IF-NEXT: .LBB21_2:
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: rint_f32:
@@ -1108,12 +1146,12 @@ define float @rint_f32(float %a) nounwind {
; RV64IZFINX-NEXT: lui a1, 307200
; RV64IZFINX-NEXT: fabs.s a2, a0
; RV64IZFINX-NEXT: flt.s a1, a2, a1
-; RV64IZFINX-NEXT: beqz a1, .LBB20_2
+; RV64IZFINX-NEXT: beqz a1, .LBB21_2
; RV64IZFINX-NEXT: # %bb.1:
; RV64IZFINX-NEXT: fcvt.w.s a1, a0
; RV64IZFINX-NEXT: fcvt.s.w a1, a1
; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV64IZFINX-NEXT: .LBB20_2:
+; RV64IZFINX-NEXT: .LBB21_2:
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: rint_f32:
@@ -1186,12 +1224,12 @@ define float @round_f32(float %a) nounwind {
; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5
-; RV32IF-NEXT: beqz a0, .LBB22_2
+; RV32IF-NEXT: beqz a0, .LBB23_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm
; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV32IF-NEXT: .LBB22_2:
+; RV32IF-NEXT: .LBB23_2:
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: round_f32:
@@ -1199,12 +1237,12 @@ define float @round_f32(float %a) nounwind {
; RV32IZFINX-NEXT: lui a1, 307200
; RV32IZFINX-NEXT: fabs.s a2, a0
; RV32IZFINX-NEXT: flt.s a1, a2, a1
-; RV32IZFINX-NEXT: beqz a1, .LBB22_2
+; RV32IZFINX-NEXT: beqz a1, .LBB23_2
; RV32IZFINX-NEXT: # %bb.1:
; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rmm
; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rmm
; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV32IZFINX-NEXT: .LBB22_2:
+; RV32IZFINX-NEXT: .LBB23_2:
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: round_f32:
@@ -1213,12 +1251,12 @@ define float @round_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x fa5, a0
; RV64IF-NEXT: fabs.s fa4, fa0
; RV64IF-NEXT: flt.s a0, fa4, fa5
-; RV64IF-NEXT: beqz a0, .LBB22_2
+; RV64IF-NEXT: beqz a0, .LBB23_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV64IF-NEXT: fcvt.s.w fa5, a0, rmm
; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV64IF-NEXT: .LBB22_2:
+; RV64IF-NEXT: .LBB23_2:
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: round_f32:
@@ -1226,12 +1264,12 @@ define float @round_f32(float %a) nounwind {
; RV64IZFINX-NEXT: lui a1, 307200
; RV64IZFINX-NEXT: fabs.s a2, a0
; RV64IZFINX-NEXT: flt.s a1, a2, a1
-; RV64IZFINX-NEXT: beqz a1, .LBB22_2
+; RV64IZFINX-NEXT: beqz a1, .LBB23_2
; RV64IZFINX-NEXT: # %bb.1:
; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rmm
; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rmm
; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV64IZFINX-NEXT: .LBB22_2:
+; RV64IZFINX-NEXT: .LBB23_2:
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: round_f32:
@@ -1264,12 +1302,12 @@ define float @roundeven_f32(float %a) nounwind {
; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5
-; RV32IF-NEXT: beqz a0, .LBB23_2
+; RV32IF-NEXT: beqz a0, .LBB24_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
; RV32IF-NEXT: fcvt.s.w fa5, a0, rne
; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV32IF-NEXT: .LBB23_2:
+; RV32IF-NEXT: .LBB24_2:
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: roundeven_f32:
@@ -1277,12 +1315,12 @@ define float @roundeven_f32(float %a) nounwind {
; RV32IZFINX-NEXT: lui a1, 307200
; RV32IZFINX-NEXT: fabs.s a2, a0
; RV32IZFINX-NEXT: flt.s a1, a2, a1
-; RV32IZFINX-NEXT: beqz a1, .LBB23_2
+; RV32IZFINX-NEXT: beqz a1, .LBB24_2
; RV32IZFINX-NEXT: # %bb.1:
; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rne
; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rne
; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV32IZFINX-NEXT: .LBB23_2:
+; RV32IZFINX-NEXT: .LBB24_2:
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: roundeven_f32:
@@ -1291,12 +1329,12 @@ define float @roundeven_f32(float %a) nounwind {
; RV64IF-NEXT: fmv.w.x fa5, a0
; RV64IF-NEXT: fabs.s fa4, fa0
; RV64IF-NEXT: flt.s a0, fa4, fa5
-; RV64IF-NEXT: beqz a0, .LBB23_2
+; RV64IF-NEXT: beqz a0, .LBB24_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rne
; RV64IF-NEXT: fcvt.s.w fa5, a0, rne
; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
-; RV64IF-NEXT: .LBB23_2:
+; RV64IF-NEXT: .LBB24_2:
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: roundeven_f32:
@@ -1304,12 +1342,12 @@ define float @roundeven_f32(float %a) nounwind {
; RV64IZFINX-NEXT: lui a1, 307200
; RV64IZFINX-NEXT: fabs.s a2, a0
; RV64IZFINX-NEXT: flt.s a1, a2, a1
-; RV64IZFINX-NEXT: beqz a1, .LBB23_2
+; RV64IZFINX-NEXT: beqz a1, .LBB24_2
; RV64IZFINX-NEXT: # %bb.1:
; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rne
; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rne
; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
-; RV64IZFINX-NEXT: .LBB23_2:
+; RV64IZFINX-NEXT: .LBB24_2:
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: roundeven_f32:
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index 8f194247427759..1ecf2c886be40f 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -1213,6 +1213,124 @@ define half @exp2_f16(half %a) nounwind {
ret half %1
}
+define half @exp10_f16(half %a) nounwind {
+; RV32IZFH-LABEL: exp10_f16:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi sp, sp, -16
+; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: call exp10f
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: exp10_f16:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addi sp, sp, -16
+; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: call exp10f
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFH-NEXT: addi sp, sp, 16
+; RV64IZFH-NEXT: ret
+;
+; RV32IZHINX-LABEL: exp10_f16:
+; RV32IZHINX: # %bb.0:
+; RV32IZHINX-NEXT: addi sp, sp, -16
+; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT: fcvt.s.h a0, a0
+; RV32IZHINX-NEXT: call exp10f
+; RV32IZHINX-NEXT: fcvt.h.s a0, a0
+; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT: addi sp, sp, 16
+; RV32IZHINX-NEXT: ret
+;
+; RV64IZHINX-LABEL: exp10_f16:
+; RV64IZHINX: # %bb.0:
+; RV64IZHINX-NEXT: addi sp, sp, -16
+; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT: fcvt.s.h a0, a0
+; RV64IZHINX-NEXT: call exp10f
+; RV64IZHINX-NEXT: fcvt.h.s a0, a0
+; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT: addi sp, sp, 16
+; RV64IZHINX-NEXT: ret
+;
+; RV32I-LABEL: exp10_f16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srli a0, a0, 16
+; RV32I-NEXT: call __extendhfsf2
+; RV32I-NEXT: call exp10f
+; RV32I-NEXT: call __truncsfhf2
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: exp10_f16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srli a0, a0, 48
+; RV64I-NEXT: call __extendhfsf2
+; RV64I-NEXT: call exp10f
+; RV64I-NEXT: call __truncsfhf2
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV32IZFHMIN-LABEL: exp10_f16:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFHMIN-NEXT: call exp10f
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: exp10_f16:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFHMIN-NEXT: call exp10f
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: exp10_f16:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: call exp10f
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: exp10_f16:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: call exp10f
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
+ %1 = call half @llvm.exp10.f16(half %a)
+ ret half %1
+}
+
declare half @llvm.log.f16(half)
define half @log_f16(half %a) nounwind {
@@ -2121,16 +2239,16 @@ declare half @llvm.floor.f16(half)
define half @floor_f16(half %a) nounwind {
; CHECKIZFH-LABEL: floor_f16:
; CHECKIZFH: # %bb.0:
-; CHECKIZFH-NEXT: lui a0, %hi(.LCPI17_0)
-; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI17_0)(a0)
+; CHECKIZFH-NEXT: lui a0, %hi(.LCPI18_0)
+; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI18_0)(a0)
; CHECKIZFH-NEXT: fabs.h fa4, fa0
; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
-; CHECKIZFH-NEXT: beqz a0, .LBB17_2
+; CHECKIZFH-NEXT: beqz a0, .LBB18_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rdn
; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; CHECKIZFH-NEXT: .LBB17_2:
+; CHECKIZFH-NEXT: .LBB18_2:
; CHECKIZFH-NEXT: ret
;
; CHECKIZHINX-LABEL: floor_f16:
@@ -2139,12 +2257,12 @@ define half @floor_f16(half %a) nounwind {
; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
-; CHECKIZHINX-NEXT: beqz a1, .LBB17_2
+; CHECKIZHINX-NEXT: beqz a1, .LBB18_2
; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
-; CHECKIZHINX-NEXT: .LBB17_2:
+; CHECKIZHINX-NEXT: .LBB18_2:
; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: floor_f16:
@@ -2180,12 +2298,12 @@ define half @floor_f16(half %a) nounwind {
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
-; CHECKIZFHMIN-NEXT: beqz a0, .LBB17_2
+; CHECKIZFHMIN-NEXT: beqz a0, .LBB18_2
; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
-; CHECKIZFHMIN-NEXT: .LBB17_2:
+; CHECKIZFHMIN-NEXT: .LBB18_2:
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
@@ -2195,12 +2313,12 @@ define half @floor_f16(half %a) nounwind {
; CHECKIZHINXMIN-NEXT: lui a1, 307200
; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
-; CHECKIZHINXMIN-NEXT: beqz a1, .LBB17_2
+; CHECKIZHINXMIN-NEXT: beqz a1, .LBB18_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT: .LBB17_2:
+; CHECKIZHINXMIN-NEXT: .LBB18_2:
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.floor.f16(half %a)
@@ -2212,16 +2330,16 @@ declare half @llvm.ceil.f16(half)
define half @ceil_f16(half %a) nounwind {
; CHECKIZFH-LABEL: ceil_f16:
; CHECKIZFH: # %bb.0:
-; CHECKIZFH-NEXT: lui a0, %hi(.LCPI18_0)
-; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI18_0)(a0)
+; CHECKIZFH-NEXT: lui a0, %hi(.LCPI19_0)
+; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0)
; CHECKIZFH-NEXT: fabs.h fa4, fa0
; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
-; CHECKIZFH-NEXT: beqz a0, .LBB18_2
+; CHECKIZFH-NEXT: beqz a0, .LBB19_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rup
; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; CHECKIZFH-NEXT: .LBB18_2:
+; CHECKIZFH-NEXT: .LBB19_2:
; CHECKIZFH-NEXT: ret
;
; CHECKIZHINX-LABEL: ceil_f16:
@@ -2230,12 +2348,12 @@ define half @ceil_f16(half %a) nounwind {
; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
-; CHECKIZHINX-NEXT: beqz a1, .LBB18_2
+; CHECKIZHINX-NEXT: beqz a1, .LBB19_2
; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
-; CHECKIZHINX-NEXT: .LBB18_2:
+; CHECKIZHINX-NEXT: .LBB19_2:
; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: ceil_f16:
@@ -2271,12 +2389,12 @@ define half @ceil_f16(half %a) nounwind {
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
-; CHECKIZFHMIN-NEXT: beqz a0, .LBB18_2
+; CHECKIZFHMIN-NEXT: beqz a0, .LBB19_2
; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
-; CHECKIZFHMIN-NEXT: .LBB18_2:
+; CHECKIZFHMIN-NEXT: .LBB19_2:
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
@@ -2286,12 +2404,12 @@ define half @ceil_f16(half %a) nounwind {
; CHECKIZHINXMIN-NEXT: lui a1, 307200
; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
-; CHECKIZHINXMIN-NEXT: beqz a1, .LBB18_2
+; CHECKIZHINXMIN-NEXT: beqz a1, .LBB19_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT: .LBB18_2:
+; CHECKIZHINXMIN-NEXT: .LBB19_2:
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.ceil.f16(half %a)
@@ -2303,16 +2421,16 @@ declare half @llvm.trunc.f16(half)
define half @trunc_f16(half %a) nounwind {
; CHECKIZFH-LABEL: trunc_f16:
; CHECKIZFH: # %bb.0:
-; CHECKIZFH-NEXT: lui a0, %hi(.LCPI19_0)
-; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0)
+; CHECKIZFH-NEXT: lui a0, %hi(.LCPI20_0)
+; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI20_0)(a0)
; CHECKIZFH-NEXT: fabs.h fa4, fa0
; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
-; CHECKIZFH-NEXT: beqz a0, .LBB19_2
+; CHECKIZFH-NEXT: beqz a0, .LBB20_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rtz
; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; CHECKIZFH-NEXT: .LBB19_2:
+; CHECKIZFH-NEXT: .LBB20_2:
; CHECKIZFH-NEXT: ret
;
; CHECKIZHINX-LABEL: trunc_f16:
@@ -2321,12 +2439,12 @@ define half @trunc_f16(half %a) nounwind {
; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
-; CHECKIZHINX-NEXT: beqz a1, .LBB19_2
+; CHECKIZHINX-NEXT: beqz a1, .LBB20_2
; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
-; CHECKIZHINX-NEXT: .LBB19_2:
+; CHECKIZHINX-NEXT: .LBB20_2:
; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: trunc_f16:
@@ -2362,12 +2480,12 @@ define half @trunc_f16(half %a) nounwind {
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
-; CHECKIZFHMIN-NEXT: beqz a0, .LBB19_2
+; CHECKIZFHMIN-NEXT: beqz a0, .LBB20_2
; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
-; CHECKIZFHMIN-NEXT: .LBB19_2:
+; CHECKIZFHMIN-NEXT: .LBB20_2:
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
@@ -2377,12 +2495,12 @@ define half @trunc_f16(half %a) nounwind {
; CHECKIZHINXMIN-NEXT: lui a1, 307200
; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
-; CHECKIZHINXMIN-NEXT: beqz a1, .LBB19_2
+; CHECKIZHINXMIN-NEXT: beqz a1, .LBB20_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT: .LBB19_2:
+; CHECKIZHINXMIN-NEXT: .LBB20_2:
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.trunc.f16(half %a)
@@ -2394,16 +2512,16 @@ declare half @llvm.rint.f16(half)
define half @rint_f16(half %a) nounwind {
; CHECKIZFH-LABEL: rint_f16:
; CHECKIZFH: # %bb.0:
-; CHECKIZFH-NEXT: lui a0, %hi(.LCPI20_0)
-; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI20_0)(a0)
+; CHECKIZFH-NEXT: lui a0, %hi(.LCPI21_0)
+; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI21_0)(a0)
; CHECKIZFH-NEXT: fabs.h fa4, fa0
; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
-; CHECKIZFH-NEXT: beqz a0, .LBB20_2
+; CHECKIZFH-NEXT: beqz a0, .LBB21_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0
; CHECKIZFH-NEXT: fcvt.h.w fa5, a0
; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; CHECKIZFH-NEXT: .LBB20_2:
+; CHECKIZFH-NEXT: .LBB21_2:
; CHECKIZFH-NEXT: ret
;
; CHECKIZHINX-LABEL: rint_f16:
@@ -2412,12 +2530,12 @@ define half @rint_f16(half %a) nounwind {
; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
-; CHECKIZHINX-NEXT: beqz a1, .LBB20_2
+; CHECKIZHINX-NEXT: beqz a1, .LBB21_2
; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: fcvt.w.h a1, a0
; CHECKIZHINX-NEXT: fcvt.h.w a1, a1
; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
-; CHECKIZHINX-NEXT: .LBB20_2:
+; CHECKIZHINX-NEXT: .LBB21_2:
; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: rint_f16:
@@ -2453,12 +2571,12 @@ define half @rint_f16(half %a) nounwind {
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
-; CHECKIZFHMIN-NEXT: beqz a0, .LBB20_2
+; CHECKIZFHMIN-NEXT: beqz a0, .LBB21_2
; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5
; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0
; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
-; CHECKIZFHMIN-NEXT: .LBB20_2:
+; CHECKIZFHMIN-NEXT: .LBB21_2:
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
@@ -2468,12 +2586,12 @@ define half @rint_f16(half %a) nounwind {
; CHECKIZHINXMIN-NEXT: lui a1, 307200
; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
-; CHECKIZHINXMIN-NEXT: beqz a1, .LBB20_2
+; CHECKIZHINXMIN-NEXT: beqz a1, .LBB21_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0
; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1
; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT: .LBB20_2:
+; CHECKIZHINXMIN-NEXT: .LBB21_2:
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.rint.f16(half %a)
@@ -2605,16 +2723,16 @@ declare half @llvm.round.f16(half)
define half @round_f16(half %a) nounwind {
; CHECKIZFH-LABEL: round_f16:
; CHECKIZFH: # %bb.0:
-; CHECKIZFH-NEXT: lui a0, %hi(.LCPI22_0)
-; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI22_0)(a0)
+; CHECKIZFH-NEXT: lui a0, %hi(.LCPI23_0)
+; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
; CHECKIZFH-NEXT: fabs.h fa4, fa0
; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
-; CHECKIZFH-NEXT: beqz a0, .LBB22_2
+; CHECKIZFH-NEXT: beqz a0, .LBB23_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rmm
; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; CHECKIZFH-NEXT: .LBB22_2:
+; CHECKIZFH-NEXT: .LBB23_2:
; CHECKIZFH-NEXT: ret
;
; CHECKIZHINX-LABEL: round_f16:
@@ -2623,12 +2741,12 @@ define half @round_f16(half %a) nounwind {
; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
-; CHECKIZHINX-NEXT: beqz a1, .LBB22_2
+; CHECKIZHINX-NEXT: beqz a1, .LBB23_2
; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
-; CHECKIZHINX-NEXT: .LBB22_2:
+; CHECKIZHINX-NEXT: .LBB23_2:
; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: round_f16:
@@ -2664,12 +2782,12 @@ define half @round_f16(half %a) nounwind {
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
-; CHECKIZFHMIN-NEXT: beqz a0, .LBB22_2
+; CHECKIZFHMIN-NEXT: beqz a0, .LBB23_2
; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
-; CHECKIZFHMIN-NEXT: .LBB22_2:
+; CHECKIZFHMIN-NEXT: .LBB23_2:
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
@@ -2679,12 +2797,12 @@ define half @round_f16(half %a) nounwind {
; CHECKIZHINXMIN-NEXT: lui a1, 307200
; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
-; CHECKIZHINXMIN-NEXT: beqz a1, .LBB22_2
+; CHECKIZHINXMIN-NEXT: beqz a1, .LBB23_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT: .LBB22_2:
+; CHECKIZHINXMIN-NEXT: .LBB23_2:
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.round.f16(half %a)
@@ -2696,16 +2814,16 @@ declare half @llvm.roundeven.f16(half)
define half @roundeven_f16(half %a) nounwind {
; CHECKIZFH-LABEL: roundeven_f16:
; CHECKIZFH: # %bb.0:
-; CHECKIZFH-NEXT: lui a0, %hi(.LCPI23_0)
-; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
+; CHECKIZFH-NEXT: lui a0, %hi(.LCPI24_0)
+; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI24_0)(a0)
; CHECKIZFH-NEXT: fabs.h fa4, fa0
; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
-; CHECKIZFH-NEXT: beqz a0, .LBB23_2
+; CHECKIZFH-NEXT: beqz a0, .LBB24_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rne
; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; CHECKIZFH-NEXT: .LBB23_2:
+; CHECKIZFH-NEXT: .LBB24_2:
; CHECKIZFH-NEXT: ret
;
; CHECKIZHINX-LABEL: roundeven_f16:
@@ -2714,12 +2832,12 @@ define half @roundeven_f16(half %a) nounwind {
; CHECKIZHINX-NEXT: slli a1, a1, 10
; CHECKIZHINX-NEXT: fabs.h a2, a0
; CHECKIZHINX-NEXT: flt.h a1, a2, a1
-; CHECKIZHINX-NEXT: beqz a1, .LBB23_2
+; CHECKIZHINX-NEXT: beqz a1, .LBB24_2
; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
-; CHECKIZHINX-NEXT: .LBB23_2:
+; CHECKIZHINX-NEXT: .LBB24_2:
; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: roundeven_f16:
@@ -2755,12 +2873,12 @@ define half @roundeven_f16(half %a) nounwind {
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
-; CHECKIZFHMIN-NEXT: beqz a0, .LBB23_2
+; CHECKIZFHMIN-NEXT: beqz a0, .LBB24_2
; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
-; CHECKIZFHMIN-NEXT: .LBB23_2:
+; CHECKIZFHMIN-NEXT: .LBB24_2:
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
@@ -2770,12 +2888,12 @@ define half @roundeven_f16(half %a) nounwind {
; CHECKIZHINXMIN-NEXT: lui a1, 307200
; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
-; CHECKIZHINXMIN-NEXT: beqz a1, .LBB23_2
+; CHECKIZHINXMIN-NEXT: beqz a1, .LBB24_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT: .LBB23_2:
+; CHECKIZHINXMIN-NEXT: .LBB24_2:
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.roundeven.f16(half %a)
diff --git a/llvm/test/CodeGen/RISCV/llvm.exp10.ll b/llvm/test/CodeGen/RISCV/llvm.exp10.ll
index 15a123400fd4fa..7b199504837e89 100644
--- a/llvm/test/CodeGen/RISCV/llvm.exp10.ll
+++ b/llvm/test/CodeGen/RISCV/llvm.exp10.ll
@@ -6,64 +6,19 @@
; RUN: -verify-machineinstrs -target-abi=lp64d < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IFD %s
-declare half @llvm.exp10.f16(half)
declare <1 x half> @llvm.exp10.v1f16(<1 x half>)
declare <2 x half> @llvm.exp10.v2f16(<2 x half>)
declare <3 x half> @llvm.exp10.v3f16(<3 x half>)
declare <4 x half> @llvm.exp10.v4f16(<4 x half>)
-declare float @llvm.exp10.f32(float)
declare <1 x float> @llvm.exp10.v1f32(<1 x float>)
declare <2 x float> @llvm.exp10.v2f32(<2 x float>)
declare <3 x float> @llvm.exp10.v3f32(<3 x float>)
declare <4 x float> @llvm.exp10.v4f32(<4 x float>)
-declare double @llvm.exp10.f64(double)
declare <1 x double> @llvm.exp10.v1f64(<1 x double>)
declare <2 x double> @llvm.exp10.v2f64(<2 x double>)
declare <3 x double> @llvm.exp10.v3f64(<3 x double>)
declare <4 x double> @llvm.exp10.v4f64(<4 x double>)
-define half @exp10_f16(half %x) {
-; RV32IFD-LABEL: exp10_f16:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: addi sp, sp, -16
-; RV32IFD-NEXT: .cfi_def_cfa_offset 16
-; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: .cfi_offset ra, -4
-; RV32IFD-NEXT: call __extendhfsf2
-; RV32IFD-NEXT: call exp10f
-; RV32IFD-NEXT: call __truncsfhf2
-; RV32IFD-NEXT: fmv.x.w a0, fa0
-; RV32IFD-NEXT: lui a1, 1048560
-; RV32IFD-NEXT: or a0, a0, a1
-; RV32IFD-NEXT: fmv.w.x fa0, a0
-; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IFD-NEXT: .cfi_restore ra
-; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: .cfi_def_cfa_offset 0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: exp10_f16:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: addi sp, sp, -16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 16
-; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFD-NEXT: .cfi_offset ra, -8
-; RV64IFD-NEXT: call __extendhfsf2
-; RV64IFD-NEXT: call exp10f
-; RV64IFD-NEXT: call __truncsfhf2
-; RV64IFD-NEXT: fmv.x.w a0, fa0
-; RV64IFD-NEXT: lui a1, 1048560
-; RV64IFD-NEXT: or a0, a0, a1
-; RV64IFD-NEXT: fmv.w.x fa0, a0
-; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64IFD-NEXT: .cfi_restore ra
-; RV64IFD-NEXT: addi sp, sp, 16
-; RV64IFD-NEXT: .cfi_def_cfa_offset 0
-; RV64IFD-NEXT: ret
- %r = call half @llvm.exp10.f16(half %x)
- ret half %r
-}
-
define <1 x half> @exp10_v1f16(<1 x half> %x) {
; RV32IFD-LABEL: exp10_v1f16:
; RV32IFD: # %bb.0:
@@ -443,14 +398,6 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) {
ret <4 x half> %r
}
-define float @exp10_f32(float %x) {
-; CHECK-LABEL: exp10_f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: tail exp10f
- %r = call float @llvm.exp10.f32(float %x)
- ret float %r
-}
-
define <1 x float> @exp10_v1f32(<1 x float> %x) {
; RV32IFD-LABEL: exp10_v1f32:
; RV32IFD: # %bb.0:
@@ -733,14 +680,6 @@ define <4 x float> @exp10_v4f32(<4 x float> %x) {
ret <4 x float> %r
}
-define double @exp10_f64(double %x) {
-; CHECK-LABEL: exp10_f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: tail exp10
- %r = call double @llvm.exp10.f64(double %x)
- ret double %r
-}
-
; FIXME: Broken
; define <1 x double> @exp10_v1f64(<1 x double> %x) {
; %r = call <1 x double> @llvm.exp10.v1f64(<1 x double> %x)
@@ -994,3 +933,5 @@ define <4 x double> @exp10_v4f64(<4 x double> %x) {
%r = call <4 x double> @llvm.exp10.v4f64(<4 x double> %x)
ret <4 x double> %r
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
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