[llvm] [AArch64] Guard against getRegisterBitWidth returning zero in vector instr cost. (PR #117749)

[Sushant Gokhale via llvm-commits]

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@@ -3248,19 +3248,18 @@ InstructionCost AArch64TTIImpl::getVectorInstrCostHelper(
     // Check if the extractelement user is scalar fmul.
     auto IsUserFMulScalarTy = [](const Value *EEUser) {
       // Check if the user is scalar fmul.
-      const auto *BO = dyn_cast_if_present<BinaryOperator>(EEUser);
+      const auto *BO = dyn_cast<BinaryOperator>(EEUser);
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sushgokh wrote:

sorry, my bad. You are right. (if_present was required in one of the earlier revisions of the original patch and that lasted till end)

https://github.com/llvm/llvm-project/pull/117749