[llvm] [RegAlloc][RISCV] Increase the spill weight by target factor (PR #113675)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> Have you tried taking LaneBitMask into account? The LaneBitMask indicates regunits occupied by the RegClass.

Yes, I tried it before. It is just the same as https://github.com/lukel97/llvm-project/commit/65bd27ec3db908ee24abd40539508875800165df I think.

https://github.com/llvm/llvm-project/pull/113675