[llvm] [RegAlloc][RISCV] Increase the spill weight by target factor (PR #113675)

[Kai Luo via llvm-commits]

bzEq wrote:

Have you tried taking LaneBitMask into account rather than adding the `Factor`? The LaneBitMask indicates concrete regunits occupied by the RegClass.

https://github.com/llvm/llvm-project/pull/113675