[llvm] [AArch64] Generate zeroing forms of certain SVE2.2 instructions (2/11) (PR #116828)

[via llvm-commits]

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@@ -571,6 +576,11 @@ multiclass SVE_3_Op_Undef_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1
             (inst $Op1, $Op2, $Op3)>;
 }
 
+class SVE_3_Op_UndefZero_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
+                             ValueType vt2, ValueType vt3, Instruction inst>
+  : Pat<(vtd (op (vt1 (SVEDup0Undef)), vt2:$Op1, vt3:$Op2)),
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CarolineConcatto wrote:

 Can we do something like
Pat<(vtd (op (vt1 (SVEDup0Undef:$Op0)), vt2:$Op1, vt3:$Op2)),
         (inst $Op0, $Op1, $Op2)>;
?
I believe 3_Op are for the intrinsics, and not for  the instruction. But I spend sometime looking at other patterns to understand what 3_Op was about.

https://github.com/llvm/llvm-project/pull/116828