[llvm] 712ef7d - [AArch64][GlobalISel] Fix smull and umull intrinsics.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 27 02:11:13 PST 2024
Author: David Green
Date: 2024-11-27T10:11:06Z
New Revision: 712ef7d0baf9b7b6c2a3f01f0c02305a0e0160e9
URL: https://github.com/llvm/llvm-project/commit/712ef7d0baf9b7b6c2a3f01f0c02305a0e0160e9
DIFF: https://github.com/llvm/llvm-project/commit/712ef7d0baf9b7b6c2a3f01f0c02305a0e0160e9.diff
LOG: [AArch64][GlobalISel] Fix smull and umull intrinsics.
These were the wrong way around somehow, with aarch64_neon_umull being converted
to G_SMULL.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/aarch64-smull.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index ad31f29c045990..619a041c273cd8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1727,9 +1727,9 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_fminnm:
return LowerBinOp(TargetOpcode::G_FMINNUM);
case Intrinsic::aarch64_neon_smull:
- return LowerBinOp(AArch64::G_UMULL);
- case Intrinsic::aarch64_neon_umull:
return LowerBinOp(AArch64::G_SMULL);
+ case Intrinsic::aarch64_neon_umull:
+ return LowerBinOp(AArch64::G_UMULL);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MachineIRBuilder MIB(MI);
diff --git a/llvm/test/CodeGen/AArch64/aarch64-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
index 0fe2bbe2c449f2..3b589d3480179f 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
@@ -2032,7 +2032,7 @@ define void @smlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3) {
; CHECK-GI-NEXT: ldr q2, [x1, #16]
; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
-; CHECK-GI-NEXT: umlsl v1.8h, v0.8b, v2.8b
+; CHECK-GI-NEXT: smlsl v1.8h, v0.8b, v2.8b
; CHECK-GI-NEXT: str q1, [x0]
; CHECK-GI-NEXT: ret
%5 = getelementptr inbounds i32, ptr %3, i64 4
@@ -2067,7 +2067,7 @@ define void @umlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3) {
; CHECK-GI-NEXT: ldr q2, [x1, #16]
; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
-; CHECK-GI-NEXT: smlsl v1.8h, v0.8b, v2.8b
+; CHECK-GI-NEXT: umlsl v1.8h, v0.8b, v2.8b
; CHECK-GI-NEXT: str q1, [x0]
; CHECK-GI-NEXT: ret
%5 = getelementptr inbounds i32, ptr %3, i64 4
@@ -2102,7 +2102,7 @@ define void @smlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3) {
; CHECK-GI-NEXT: ldr q2, [x1, #16]
; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
-; CHECK-GI-NEXT: umlsl v1.4s, v0.4h, v2.4h
+; CHECK-GI-NEXT: smlsl v1.4s, v0.4h, v2.4h
; CHECK-GI-NEXT: str q1, [x0]
; CHECK-GI-NEXT: ret
%5 = getelementptr inbounds i32, ptr %3, i64 4
@@ -2137,7 +2137,7 @@ define void @umlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3) {
; CHECK-GI-NEXT: ldr q2, [x1, #16]
; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
-; CHECK-GI-NEXT: smlsl v1.4s, v0.4h, v2.4h
+; CHECK-GI-NEXT: umlsl v1.4s, v0.4h, v2.4h
; CHECK-GI-NEXT: str q1, [x0]
; CHECK-GI-NEXT: ret
%5 = getelementptr inbounds i32, ptr %3, i64 4
@@ -2202,8 +2202,8 @@ define void @smlsl_smlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3,
; CHECK-GI-NEXT: mov d3, v0.d[1]
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: xtn v4.8b, v4.8h
-; CHECK-GI-NEXT: umull v2.8h, v3.8b, v2.8b
-; CHECK-GI-NEXT: umlal v2.8h, v0.8b, v4.8b
+; CHECK-GI-NEXT: smull v2.8h, v3.8b, v2.8b
+; CHECK-GI-NEXT: smlal v2.8h, v0.8b, v4.8b
; CHECK-GI-NEXT: sub v0.8h, v1.8h, v2.8h
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
@@ -2248,8 +2248,8 @@ define void @umlsl_umlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3,
; CHECK-GI-NEXT: mov d3, v0.d[1]
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: xtn v4.8b, v4.8h
-; CHECK-GI-NEXT: smull v2.8h, v3.8b, v2.8b
-; CHECK-GI-NEXT: smlal v2.8h, v0.8b, v4.8b
+; CHECK-GI-NEXT: umull v2.8h, v3.8b, v2.8b
+; CHECK-GI-NEXT: umlal v2.8h, v0.8b, v4.8b
; CHECK-GI-NEXT: sub v0.8h, v1.8h, v2.8h
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
@@ -2294,8 +2294,8 @@ define void @smlsl_smlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3,
; CHECK-GI-NEXT: mov d3, v0.d[1]
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
; CHECK-GI-NEXT: xtn v4.4h, v4.4s
-; CHECK-GI-NEXT: umull v2.4s, v3.4h, v2.4h
-; CHECK-GI-NEXT: umlal v2.4s, v0.4h, v4.4h
+; CHECK-GI-NEXT: smull v2.4s, v3.4h, v2.4h
+; CHECK-GI-NEXT: smlal v2.4s, v0.4h, v4.4h
; CHECK-GI-NEXT: sub v0.4s, v1.4s, v2.4s
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
@@ -2340,8 +2340,8 @@ define void @umlsl_umlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3,
; CHECK-GI-NEXT: mov d3, v0.d[1]
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
; CHECK-GI-NEXT: xtn v4.4h, v4.4s
-; CHECK-GI-NEXT: smull v2.4s, v3.4h, v2.4h
-; CHECK-GI-NEXT: smlal v2.4s, v0.4h, v4.4h
+; CHECK-GI-NEXT: umull v2.4s, v3.4h, v2.4h
+; CHECK-GI-NEXT: umlal v2.4s, v0.4h, v4.4h
; CHECK-GI-NEXT: sub v0.4s, v1.4s, v2.4s
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
@@ -2382,7 +2382,7 @@ define <2 x i32> @do_stuff(<2 x i64> %0, <2 x i64> %1) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
; CHECK-GI-NEXT: mov d2, v1.d[1]
-; CHECK-GI-NEXT: umull v0.2d, v2.2s, v0.2s
+; CHECK-GI-NEXT: smull v0.2d, v2.2s, v0.2s
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
; CHECK-GI-NEXT: add v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
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