[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[David Green via llvm-commits]

================
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 %s -o - | FileCheck %s
----------------
davemgreen wrote:

Is it worth having a +sve and a +sve2 run line.

https://github.com/llvm/llvm-project/pull/117007