[llvm] 5322415 - [PowerPC] Use getSignedConstant() in SelectOptimalAddrMode()
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 26 05:35:50 PST 2024
Author: Nikita Popov
Date: 2024-11-26T14:34:30+01:00
New Revision: 5322415f92fe44a9dac29c95da5ed434efbbba7e
URL: https://github.com/llvm/llvm-project/commit/5322415f92fe44a9dac29c95da5ed434efbbba7e
DIFF: https://github.com/llvm/llvm-project/commit/5322415f92fe44a9dac29c95da5ed434efbbba7e.diff
LOG: [PowerPC] Use getSignedConstant() in SelectOptimalAddrMode()
All of these immediates are signed, as the surrounding comments
indicate. This fixes an assertion failure in
CodeGen/Generic/dag-combine-ossfuzz-crash.ll when run with a
powerpc-aix triple.
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f4d3668726164b..5451035b500846 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -18928,7 +18928,7 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
SDValue Op1 = N.getOperand(1);
int16_t Imm = Op1->getAsZExtVal();
if (!Align || isAligned(*Align, Imm)) {
- Disp = DAG.getTargetConstant(Imm, DL, N.getValueType());
+ Disp = DAG.getSignedTargetConstant(Imm, DL, N.getValueType());
Base = Op0;
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0)) {
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
@@ -18959,7 +18959,7 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
// this as "d, 0".
int16_t Imm;
if (isIntS16Immediate(CN, Imm) && (!Align || isAligned(*Align, Imm))) {
- Disp = DAG.getTargetConstant(Imm, DL, CNType);
+ Disp = DAG.getSignedTargetConstant(Imm, DL, CNType);
Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
CNType);
break;
@@ -18992,14 +18992,14 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
if (((Opcode == ISD::ADD) || (Opcode == ISD::OR)) &&
(isIntS34Immediate(N.getOperand(1), Imm34))) {
// N is an Add/OR Node, and it's operand is a 34-bit signed immediate.
- Disp = DAG.getTargetConstant(Imm34, DL, N.getValueType());
+ Disp = DAG.getSignedTargetConstant(Imm34, DL, N.getValueType());
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
else
Base = N.getOperand(0);
} else if (isIntS34Immediate(N, Imm34)) {
// The address is a 34-bit signed immediate.
- Disp = DAG.getTargetConstant(Imm34, DL, N.getValueType());
+ Disp = DAG.getSignedTargetConstant(Imm34, DL, N.getValueType());
Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
}
break;
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