[llvm] [NVPTX] Add TMA bulk tensor reduction intrinsics (PR #116854)

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git-clang-format --diff 90df66455b2ff6a3b3754a56afafc05935a05e15 67da5e51c1d074154740ad1a93e1e872ba2b5e9f --extensions cpp,h -- llvm/include/llvm/IR/NVVMIntrinsicFlags.h llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
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diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index de0089575c..e1fb2d7fce 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -4178,7 +4178,7 @@ bool NVPTXScopes::empty() const { return Scopes.size() == 0; }
     if (is_mc)                                                                 \
       return CP_ASYNC_BULK_TENSOR_OPCODE(G2S, dim, mode, is_s32, _MC);         \
     return CP_ASYNC_BULK_TENSOR_OPCODE(G2S, dim, mode, is_s32, );              \
-  }()                                                                          \
+  }()
 
 #define GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(dim, mode, is_ch)             \
   (is_ch ? NVPTX::CP_ASYNC_BULK_TENSOR_PREFETCH_##dim##_##mode##_CH            \

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https://github.com/llvm/llvm-project/pull/116854