[llvm] [RISC-V] Support fixed vector type for inline asm (#117098) (PR #117100)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

I agree with @topperc that this looks like a front end problem and when it converts the inline asm to LLVM IR the front end should handle the VLS types the same way as it does for function calls.

The problem with trying to defer this until code generation is that only the front end fully understands how the VLS types are represented.  Boolean/predicate vectors are a good example of where this is more complex that it might seem, where for SVE the scalable type is an i1 vector but the VLS equivalent is an i8 vector.

https://github.com/llvm/llvm-project/pull/117100