[llvm] [RISCV] Handle zeroinitializer of vector tuple Type (PR #113995)

[Brandon Wu via llvm-commits]

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@@ -57,6 +57,28 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
 
     SDValue Result;
     switch (N->getOpcode()) {
+    case ISD::BITCAST: {
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4vtomat wrote:

I think it can't, it needs both src and dst registers to be in same register class

https://github.com/llvm/llvm-project/pull/113995