[llvm] [RISCV] Handle zeroinitializer of vector tuple Type (PR #113995)

[Craig Topper via llvm-commits]

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@@ -57,6 +57,28 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
 
     SDValue Result;
     switch (N->getOpcode()) {
+    case ISD::BITCAST: {
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topperc wrote:

> But I think we don't model the hierarchy like VRN2M2 <-> VRM4 right?

`copyPhysReg` might work if it just looks up the start and number of registers for each of the register classes. But there's no equivalence when NF is not a power of 2.

https://github.com/llvm/llvm-project/pull/113995