[llvm] 935da49 - AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo (#117449)

[via llvm-commits]

Author: Matt Arsenault
Date: 2024-11-25T14:21:52-08:00
New Revision: 935da49a4d02316cbd0458d09d5913b6d1cabddc

URL: https://github.com/llvm/llvm-project/commit/935da49a4d02316cbd0458d09d5913b6d1cabddc
DIFF: https://github.com/llvm/llvm-project/commit/935da49a4d02316cbd0458d09d5913b6d1cabddc.diff

LOG: AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo (#117449)

I haven't figured out how to do anything useful with this yet,
but it seems you are supposed to pass this to the subtarget
constructor.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 246ef7ad481ab7..049f4af4dd2f93 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -319,7 +319,8 @@ struct SGPRSpillBuilder {
 
 SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
     : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour(),
-                            ST.getAMDGPUDwarfFlavour()),
+                            ST.getAMDGPUDwarfFlavour(),
+                            /*PC=*/0, ST.getHwMode()),
       ST(ST), SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
 
   assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&