[llvm] c537c75 - [AArch64][GlobalISel] Scalarize i128 vector sadd_sat/uadd_sat/etc.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 25 01:55:51 PST 2024
Author: David Green
Date: 2024-11-25T09:55:46Z
New Revision: c537c752787e9da8bd8762dd5298a152f546861b
URL: https://github.com/llvm/llvm-project/commit/c537c752787e9da8bd8762dd5298a152f546861b
DIFF: https://github.com/llvm/llvm-project/commit/c537c752787e9da8bd8762dd5298a152f546861b.diff
LOG: [AArch64][GlobalISel] Scalarize i128 vector sadd_sat/uadd_sat/etc.
As with other operations we scalarize any vectors with larger types to let the
scalare legalization kick in.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
llvm/test/CodeGen/AArch64/usub_sat_vec.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 9c1bbafd337e93..ad31f29c045990 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1303,6 +1303,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampMaxNumElements(0, s64, 2)
+ .scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.moreElementsToNextPow2(0)
.lower();
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index 6a4ab837fc4720..531562d3aa678e 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -4,7 +4,6 @@
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
@@ -498,21 +497,45 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
}
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
-; CHECK-LABEL: v2i128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: adds x8, x0, x4
-; CHECK-NEXT: adcs x9, x1, x5
-; CHECK-NEXT: asr x10, x9, #63
-; CHECK-NEXT: eor x11, x10, #0x8000000000000000
-; CHECK-NEXT: csel x0, x10, x8, vs
-; CHECK-NEXT: csel x1, x11, x9, vs
-; CHECK-NEXT: adds x8, x2, x6
-; CHECK-NEXT: adcs x9, x3, x7
-; CHECK-NEXT: asr x10, x9, #63
-; CHECK-NEXT: eor x11, x10, #0x8000000000000000
-; CHECK-NEXT: csel x2, x10, x8, vs
-; CHECK-NEXT: csel x3, x11, x9, vs
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v2i128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: adds x8, x0, x4
+; CHECK-SD-NEXT: adcs x9, x1, x5
+; CHECK-SD-NEXT: asr x10, x9, #63
+; CHECK-SD-NEXT: eor x11, x10, #0x8000000000000000
+; CHECK-SD-NEXT: csel x0, x10, x8, vs
+; CHECK-SD-NEXT: csel x1, x11, x9, vs
+; CHECK-SD-NEXT: adds x8, x2, x6
+; CHECK-SD-NEXT: adcs x9, x3, x7
+; CHECK-SD-NEXT: asr x10, x9, #63
+; CHECK-SD-NEXT: eor x11, x10, #0x8000000000000000
+; CHECK-SD-NEXT: csel x2, x10, x8, vs
+; CHECK-SD-NEXT: csel x3, x11, x9, vs
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v2i128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adds x9, x0, x4
+; CHECK-GI-NEXT: mov w8, wzr
+; CHECK-GI-NEXT: mov x13, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: adcs x10, x1, x5
+; CHECK-GI-NEXT: asr x11, x10, #63
+; CHECK-GI-NEXT: cset w12, vs
+; CHECK-GI-NEXT: cmp w8, #1
+; CHECK-GI-NEXT: adc x14, x11, x13
+; CHECK-GI-NEXT: tst w12, #0x1
+; CHECK-GI-NEXT: csel x0, x11, x9, ne
+; CHECK-GI-NEXT: csel x1, x14, x10, ne
+; CHECK-GI-NEXT: adds x9, x2, x6
+; CHECK-GI-NEXT: adcs x10, x3, x7
+; CHECK-GI-NEXT: asr x11, x10, #63
+; CHECK-GI-NEXT: cset w12, vs
+; CHECK-GI-NEXT: cmp w8, #1
+; CHECK-GI-NEXT: adc x8, x11, x13
+; CHECK-GI-NEXT: tst w12, #0x1
+; CHECK-GI-NEXT: csel x2, x11, x9, ne
+; CHECK-GI-NEXT: csel x3, x8, x10, ne
+; CHECK-GI-NEXT: ret
%z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z
}
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index 86a503038766c6..be4a5843e8215a 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -4,7 +4,6 @@
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
@@ -501,21 +500,45 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
}
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
-; CHECK-LABEL: v2i128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: subs x8, x0, x4
-; CHECK-NEXT: sbcs x9, x1, x5
-; CHECK-NEXT: asr x10, x9, #63
-; CHECK-NEXT: eor x11, x10, #0x8000000000000000
-; CHECK-NEXT: csel x0, x10, x8, vs
-; CHECK-NEXT: csel x1, x11, x9, vs
-; CHECK-NEXT: subs x8, x2, x6
-; CHECK-NEXT: sbcs x9, x3, x7
-; CHECK-NEXT: asr x10, x9, #63
-; CHECK-NEXT: eor x11, x10, #0x8000000000000000
-; CHECK-NEXT: csel x2, x10, x8, vs
-; CHECK-NEXT: csel x3, x11, x9, vs
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v2i128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: subs x8, x0, x4
+; CHECK-SD-NEXT: sbcs x9, x1, x5
+; CHECK-SD-NEXT: asr x10, x9, #63
+; CHECK-SD-NEXT: eor x11, x10, #0x8000000000000000
+; CHECK-SD-NEXT: csel x0, x10, x8, vs
+; CHECK-SD-NEXT: csel x1, x11, x9, vs
+; CHECK-SD-NEXT: subs x8, x2, x6
+; CHECK-SD-NEXT: sbcs x9, x3, x7
+; CHECK-SD-NEXT: asr x10, x9, #63
+; CHECK-SD-NEXT: eor x11, x10, #0x8000000000000000
+; CHECK-SD-NEXT: csel x2, x10, x8, vs
+; CHECK-SD-NEXT: csel x3, x11, x9, vs
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v2i128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: subs x9, x0, x4
+; CHECK-GI-NEXT: mov w8, wzr
+; CHECK-GI-NEXT: mov x13, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: sbcs x10, x1, x5
+; CHECK-GI-NEXT: asr x11, x10, #63
+; CHECK-GI-NEXT: cset w12, vs
+; CHECK-GI-NEXT: cmp w8, #1
+; CHECK-GI-NEXT: adc x14, x11, x13
+; CHECK-GI-NEXT: tst w12, #0x1
+; CHECK-GI-NEXT: csel x0, x11, x9, ne
+; CHECK-GI-NEXT: csel x1, x14, x10, ne
+; CHECK-GI-NEXT: subs x9, x2, x6
+; CHECK-GI-NEXT: sbcs x10, x3, x7
+; CHECK-GI-NEXT: asr x11, x10, #63
+; CHECK-GI-NEXT: cset w12, vs
+; CHECK-GI-NEXT: cmp w8, #1
+; CHECK-GI-NEXT: adc x8, x11, x13
+; CHECK-GI-NEXT: tst w12, #0x1
+; CHECK-GI-NEXT: csel x2, x11, x9, ne
+; CHECK-GI-NEXT: csel x3, x8, x10, ne
+; CHECK-GI-NEXT: ret
%z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z
}
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
index d4587c3439967a..924bd3981779ea 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
@@ -4,7 +4,6 @@
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
@@ -492,17 +491,33 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
}
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
-; CHECK-LABEL: v2i128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: adds x8, x0, x4
-; CHECK-NEXT: adcs x9, x1, x5
-; CHECK-NEXT: csinv x0, x8, xzr, lo
-; CHECK-NEXT: csinv x1, x9, xzr, lo
-; CHECK-NEXT: adds x8, x2, x6
-; CHECK-NEXT: adcs x9, x3, x7
-; CHECK-NEXT: csinv x2, x8, xzr, lo
-; CHECK-NEXT: csinv x3, x9, xzr, lo
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v2i128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: adds x8, x0, x4
+; CHECK-SD-NEXT: adcs x9, x1, x5
+; CHECK-SD-NEXT: csinv x0, x8, xzr, lo
+; CHECK-SD-NEXT: csinv x1, x9, xzr, lo
+; CHECK-SD-NEXT: adds x8, x2, x6
+; CHECK-SD-NEXT: adcs x9, x3, x7
+; CHECK-SD-NEXT: csinv x2, x8, xzr, lo
+; CHECK-SD-NEXT: csinv x3, x9, xzr, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v2i128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adds x8, x0, x4
+; CHECK-GI-NEXT: adcs x9, x1, x5
+; CHECK-GI-NEXT: cset w10, hs
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csinv x0, x8, xzr, eq
+; CHECK-GI-NEXT: csinv x1, x9, xzr, eq
+; CHECK-GI-NEXT: adds x8, x2, x6
+; CHECK-GI-NEXT: adcs x9, x3, x7
+; CHECK-GI-NEXT: cset w10, hs
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csinv x2, x8, xzr, eq
+; CHECK-GI-NEXT: csinv x3, x9, xzr, eq
+; CHECK-GI-NEXT: ret
%z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z
}
diff --git a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
index 123f4280bd8ff2..a623eb554cac79 100644
--- a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
@@ -4,7 +4,6 @@
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.usub.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>)
@@ -490,17 +489,33 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
}
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
-; CHECK-LABEL: v2i128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: subs x8, x0, x4
-; CHECK-NEXT: sbcs x9, x1, x5
-; CHECK-NEXT: csel x0, xzr, x8, lo
-; CHECK-NEXT: csel x1, xzr, x9, lo
-; CHECK-NEXT: subs x8, x2, x6
-; CHECK-NEXT: sbcs x9, x3, x7
-; CHECK-NEXT: csel x2, xzr, x8, lo
-; CHECK-NEXT: csel x3, xzr, x9, lo
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: v2i128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: subs x8, x0, x4
+; CHECK-SD-NEXT: sbcs x9, x1, x5
+; CHECK-SD-NEXT: csel x0, xzr, x8, lo
+; CHECK-SD-NEXT: csel x1, xzr, x9, lo
+; CHECK-SD-NEXT: subs x8, x2, x6
+; CHECK-SD-NEXT: sbcs x9, x3, x7
+; CHECK-SD-NEXT: csel x2, xzr, x8, lo
+; CHECK-SD-NEXT: csel x3, xzr, x9, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: v2i128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: subs x8, x0, x4
+; CHECK-GI-NEXT: sbcs x9, x1, x5
+; CHECK-GI-NEXT: cset w10, lo
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x0, xzr, x8, ne
+; CHECK-GI-NEXT: csel x1, xzr, x9, ne
+; CHECK-GI-NEXT: subs x8, x2, x6
+; CHECK-GI-NEXT: sbcs x9, x3, x7
+; CHECK-GI-NEXT: cset w10, lo
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x2, xzr, x8, ne
+; CHECK-GI-NEXT: csel x3, xzr, x9, ne
+; CHECK-GI-NEXT: ret
%z = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z
}
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