[llvm] [Mips] Support llvm.readcyclecounter intrinsic (PR #114953)

[YunQiang Su via llvm-commits]

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@@ -2092,6 +2095,42 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
   return exitMBB;
 }
 
+SDValue MipsTargetLowering::lowerREADCYCLECOUNTER(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  SmallVector<SDValue, 3> Results;
+  SDLoc DL(Op);
+  unsigned RdhwrOpc, DestReg;
+
+  if (Subtarget.hasMips64()) {
+    RdhwrOpc = Mips::RDHWR64;
+    DestReg = Mips::V1_64;
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wzssyqa wrote:

Why can V1 can hardcoded here?
If the IR is quite long, will it overwrite some previous value?

https://github.com/llvm/llvm-project/pull/114953