[llvm] [BOLT][AArch64] Adds tls relocations support (PR #117465)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-bolt

Author: Alexey Moksyakov (yavtuk)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/117465.diff


3 Files Affected:

- (modified) bolt/lib/Core/Relocation.cpp (+14) 
- (modified) bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp (+2) 
- (added) bolt/test/AArch64/r_aarch64_tls.s (+60) 


``````````diff
diff --git a/bolt/lib/Core/Relocation.cpp b/bolt/lib/Core/Relocation.cpp
index 4e888a5b147aca..d4b3168c8a139f 100644
--- a/bolt/lib/Core/Relocation.cpp
+++ b/bolt/lib/Core/Relocation.cpp
@@ -75,6 +75,8 @@ static bool isSupportedAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
@@ -183,6 +185,8 @@ static size_t getSizeForTypeAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
@@ -480,6 +484,12 @@ static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents,
     Contents &= ~0xffffffffffc003ffU;
     return Contents >> (10 - 0);
   }
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: {
+    // 16 bits immediate goes in [20:5] bits
+    Contents &= ~0xffffffffffe0001fU;
+    return Contents >> 5;
+  }
   case ELF::R_AARCH64_LDST128_ABS_LO12_NC: {
     // Immediate goes in bits 21:10 of ADD instruction, taken
     // from bits 11:4 of Symbol address
@@ -651,6 +661,8 @@ static bool isTLSAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
   case ELF::R_AARCH64_TLSDESC_CALL:
@@ -716,6 +728,8 @@ static bool isPCRelativeAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12:
   case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0:
+  case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index 7e08e5c81d26ff..679c9774c767f7 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -1449,6 +1449,8 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
     case ELF::R_AARCH64_TLSDESC_LD64_LO12:
     case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
     case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+    case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0:
+    case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
     case ELF::R_AARCH64_MOVW_UABS_G0:
     case ELF::R_AARCH64_MOVW_UABS_G0_NC:
     case ELF::R_AARCH64_MOVW_UABS_G1:
diff --git a/bolt/test/AArch64/r_aarch64_tls.s b/bolt/test/AArch64/r_aarch64_tls.s
new file mode 100644
index 00000000000000..aa83162ada5959
--- /dev/null
+++ b/bolt/test/AArch64/r_aarch64_tls.s
@@ -0,0 +1,60 @@
+## This test checks processing of tls relocations
+##
+## R_AARCH64_TLSLE_MOVW_TPREL_G0, TPREL(S + A)
+## R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, TPREL(S + A)
+
+# REQUIRES: system-linux
+
+# RUN: %clang %cflags -nostartfiles -nostdlib %s -o %t.exe -mlittle-endian \
+# RUN:     -Wl,-q
+# RUN: llvm-readelf -Wr %t.exe | FileCheck %s -check-prefix=CHECKTLS
+
+# CHECKTLS:       R_AARCH64_TLSLE_MOVW_TPREL_G0      {{.*}} .tprel_tls_var + 0
+# CHECKTLS-NEXT:  R_AARCH64_TLSLE_MOVW_TPREL_G0_NC   {{.*}} .tprel_tls_var + 4
+
+# RUN: llvm-bolt %t.exe -o %t.bolt
+# RUN: llvm-objdump -D %t.bolt | FileCheck %s --check-prefix=CHECKBOLT
+
+# CHECKBOLT: Disassembly of section .tdata
+# CHECKBOLT: [[#%x,DATATABLEADDR:]] <.tdata
+# CHECKBOLT-NEXT: [[#DATATABLEADDR]]: 000000aa
+# CHECKBOLT-NEXT: [[#DATATABLEADDR + 4]]: 000000bb
+
+.section .tdata
+.align 4
+.tprel_tls_var:
+.word 0xaa
+.word 0xbb
+
+.section .text
+.align 4
+.globl _start
+.type _start, %function
+_start:
+  mrs x0, TPIDR_EL0
+  movz x1, #:tprel_g0:.tprel_tls_var
+  add x0, x0, x1
+  ldr w2, [x0]
+  cmp w2, 0xaa
+  bne exit_failure
+
+  mrs x0, TPIDR_EL0
+  movk x1, #:tprel_g0_nc:.tprel_tls_var
+  add x0, x0, x1
+  ldr w2, [x0]
+  cmp w2, 0xbb
+  bne exit_failure
+
+exit_success:
+  mov x0, #0
+  b exit
+
+exit_failure:
+  mov x0, #1
+  b exit
+
+exit:
+  mov x8, #93
+  svc #0
+
+.size _start, .-_start

``````````

</details>


https://github.com/llvm/llvm-project/pull/117465