[llvm] AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo (PR #117449)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117449

I haven't figured out how to do anything useful with this yet,
but it seems you are supposed to pass this to the subtarget
constructor.

>From 87463319139e25fa30fd1402756bf19709f3b700 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sat, 23 Nov 2024 10:23:37 -0800
Subject: [PATCH] AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo

I haven't figured out how to do anything useful with this yet,
but it seems you are supposed to pass this to the subtarget
constructor.
---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 246ef7ad481ab7..049f4af4dd2f93 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -319,7 +319,8 @@ struct SGPRSpillBuilder {
 
 SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
     : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour(),
-                            ST.getAMDGPUDwarfFlavour()),
+                            ST.getAMDGPUDwarfFlavour(),
+                            /*PC=*/0, ST.getHwMode()),
       ST(ST), SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
 
   assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&