[llvm] [LoongArch] Use div.w/mod.w to eliminate unnecessary sign-extend for sdiv/srem i32. (PR #117298)

[Craig Topper via llvm-commits]

================
@@ -44,6 +44,8 @@ enum NodeType : unsigned {
   ROTR_W,
 
   // unsigned 32-bit integer division
+  DIV_W,
+  MOD_W,
----------------
topperc wrote:

Do you really need MOD_W? RISC-V doesn't have REMW. We use default promotion for signed remainder and use this isel pattern.

```
def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),             
          (REMW GPR:$rs1, GPR:$rs2)>;
```

https://github.com/llvm/llvm-project/pull/117298