[llvm] [LLVM][NVPTX] Add support for div.full instruction (PR #116482)

[Pradeep Kumar via llvm-commits]

https://github.com/schwarzschild-radius updated https://github.com/llvm/llvm-project/pull/116482

>From 8e3b135cf2de0b0a67708e5318ab41b3b6e09a38 Mon Sep 17 00:00:00 2001
From: pradeepku <pradeepku at nvidia.com>
Date: Wed, 6 Nov 2024 13:13:38 +0530
Subject: [PATCH] [LLVM][NVPTX] Add support for div.full instruction

This commit adds NVPTX support for div.full PTX instruction with test under div.ll
---
 llvm/include/llvm/IR/IntrinsicsNVVM.td   |  7 +++++++
 llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 12 ++++++++++++
 llvm/test/CodeGen/NVPTX/div.ll           | 16 ++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 llvm/test/CodeGen/NVPTX/div.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td
index 115fcee0b04f22..8802ca2534355c 100644
--- a/llvm/include/llvm/IR/IntrinsicsNVVM.td
+++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td
@@ -820,6 +820,13 @@ let TargetPrefix = "nvvm" in {
       DefaultAttrsIntrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
         [IntrNoMem]>;
 
+  def int_nvvm_div_full : ClangBuiltin<"__nvvm_div_full">,
+      DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
+        [IntrNoMem]>;
+  def int_nvvm_div_full_ftz : ClangBuiltin<"__nvvm_div_full_ftz">,
+      DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
+        [IntrNoMem]>;
+
 //
 // Sad
 //
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 5878940812f62b..5528e7b9fe0dda 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -1096,6 +1096,18 @@ def INT_NVVM_DIV_RM_D : F_MATH_2<"div.rm.f64 \t$dst, $src0, $src1;",
 def INT_NVVM_DIV_RP_D : F_MATH_2<"div.rp.f64 \t$dst, $src0, $src1;",
   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rp_d>;
 
+def : Pat<(int_nvvm_div_full Float32Regs:$a, Float32Regs:$b),
+          (FDIV32rr Float32Regs:$a, Float32Regs:$b)>;
+
+def : Pat<(int_nvvm_div_full Float32Regs:$a, fpimm:$b),
+          (FDIV32ri Float32Regs:$a, f32imm:$b)>;
+
+def : Pat<(int_nvvm_div_full_ftz Float32Regs:$a, Float32Regs:$b),
+          (FDIV32rr_ftz Float32Regs:$a, Float32Regs:$b)>;
+
+def : Pat<(int_nvvm_div_full_ftz Float32Regs:$a, fpimm:$b),
+          (FDIV32ri_ftz Float32Regs:$a, f32imm:$b)>;
+
 //
 // Sad
 //
diff --git a/llvm/test/CodeGen/NVPTX/div.ll b/llvm/test/CodeGen/NVPTX/div.ll
new file mode 100644
index 00000000000000..adff2fe85c867e
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/div.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=nvptx64 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 | %ptxas-verify %}
+
+define float @div_full(float %a, float %b) {
+  ; CHECK: div.full.f32 {{%f[0-9]+}}, {{%f[0-9]+}}, {{%f[0-9]+}}
+  %1 = call float @llvm.nvvm.div.full(float %a, float %b)
+  ; CHECK: mov.f32 {{%f[0-9]+}}, 0f40400000
+  ; CHECK: div.full.f32 {{%f[0-9]+}}, {{%f[0-9]+}}, {{%f[0-9]+}}
+  %2 = call float @llvm.nvvm.div.full(float %1, float 3.0)
+  ; CHECK: div.full.ftz.f32 {{%f[0-9]+}}, {{%f[0-9]+}}, {{%f[0-9]+}}
+  %3 = call float @llvm.nvvm.div.full.ftz(float %2, float %b)
+  ; CHECK: mov.f32 {{%f[0-9]+}}, 0f40800000
+  ; CHECK: div.full.ftz.f32 {{%f[0-9]+}}, {{%f[0-9]+}}, {{%f[0-9]+}}
+  %4 = call float @llvm.nvvm.div.full.ftz(float %3, float 4.0)
+  ret float %4
+}