[llvm] 6da8ff8 - [RISCV] Add explicit VLS test line for vector spill/fill
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 22 11:55:37 PST 2024
Author: Philip Reames
Date: 2024-11-22T11:55:24-08:00
New Revision: 6da8ff82a8a621c7d32eaf9667a845c0be03f2e6
URL: https://github.com/llvm/llvm-project/commit/6da8ff82a8a621c7d32eaf9667a845c0be03f2e6
DIFF: https://github.com/llvm/llvm-project/commit/6da8ff82a8a621c7d32eaf9667a845c0be03f2e6.diff
LOG: [RISCV] Add explicit VLS test line for vector spill/fill
I got asked about this offline and realized we didn't really have
tests specific to the VLS frame lowering.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
index 1e6ff0baddaef2..957a23f0069b89 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
@@ -3,6 +3,8 @@
; RUN: | FileCheck --check-prefix=SPILL-O0 %s
; RUN: llc -mtriple=riscv64 -mattr=+v -O2 < %s \
; RUN: | FileCheck --check-prefix=SPILL-O2 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d -mattr=+d -riscv-v-vector-bits-max=128 -O2 < %s \
+; RUN: | FileCheck --check-prefix=SPILL-O2-VLEN128 %s
define <vscale x 1 x i64> @spill_lmul_1(<vscale x 1 x i64> %va) nounwind {
; SPILL-O0-LABEL: spill_lmul_1:
@@ -35,6 +37,19 @@ define <vscale x 1 x i64> @spill_lmul_1(<vscale x 1 x i64> %va) nounwind {
; SPILL-O2-NEXT: add sp, sp, a0
; SPILL-O2-NEXT: addi sp, sp, 16
; SPILL-O2-NEXT: ret
+;
+; SPILL-O2-VLEN128-LABEL: spill_lmul_1:
+; SPILL-O2-VLEN128: # %bb.0: # %entry
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
+; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
+; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-VLEN128-NEXT: #APP
+; SPILL-O2-VLEN128-NEXT: #NO_APP
+; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
+; SPILL-O2-VLEN128-NEXT: ret
entry:
call void asm sideeffect "",
"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
@@ -77,6 +92,19 @@ define <vscale x 2 x i64> @spill_lmul_2(<vscale x 2 x i64> %va) nounwind {
; SPILL-O2-NEXT: add sp, sp, a0
; SPILL-O2-NEXT: addi sp, sp, 16
; SPILL-O2-NEXT: ret
+;
+; SPILL-O2-VLEN128-LABEL: spill_lmul_2:
+; SPILL-O2-VLEN128: # %bb.0: # %entry
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32
+; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
+; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-VLEN128-NEXT: #APP
+; SPILL-O2-VLEN128-NEXT: #NO_APP
+; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
+; SPILL-O2-VLEN128-NEXT: ret
entry:
call void asm sideeffect "",
"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
@@ -119,6 +147,19 @@ define <vscale x 4 x i64> @spill_lmul_4(<vscale x 4 x i64> %va) nounwind {
; SPILL-O2-NEXT: add sp, sp, a0
; SPILL-O2-NEXT: addi sp, sp, 16
; SPILL-O2-NEXT: ret
+;
+; SPILL-O2-VLEN128-LABEL: spill_lmul_4:
+; SPILL-O2-VLEN128: # %bb.0: # %entry
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -64
+; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
+; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-VLEN128-NEXT: #APP
+; SPILL-O2-VLEN128-NEXT: #NO_APP
+; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 64
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
+; SPILL-O2-VLEN128-NEXT: ret
entry:
call void asm sideeffect "",
"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
@@ -161,6 +202,19 @@ define <vscale x 8 x i64> @spill_lmul_8(<vscale x 8 x i64> %va) nounwind {
; SPILL-O2-NEXT: add sp, sp, a0
; SPILL-O2-NEXT: addi sp, sp, 16
; SPILL-O2-NEXT: ret
+;
+; SPILL-O2-VLEN128-LABEL: spill_lmul_8:
+; SPILL-O2-VLEN128: # %bb.0: # %entry
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, -128
+; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
+; SPILL-O2-VLEN128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-VLEN128-NEXT: #APP
+; SPILL-O2-VLEN128-NEXT: #NO_APP
+; SPILL-O2-VLEN128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 128
+; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
+; SPILL-O2-VLEN128-NEXT: ret
entry:
call void asm sideeffect "",
"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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