[llvm] 1683f84 - Revert "[InitUndef] handleSubReg should skip artificial subregs. (#116248)" (#117365)

[via llvm-commits]

Author: Vitaly Buka
Date: 2024-11-22T11:24:48-08:00
New Revision: 1683f84d289348ba6879635c4161979204f75230

URL: https://github.com/llvm/llvm-project/commit/1683f84d289348ba6879635c4161979204f75230
DIFF: https://github.com/llvm/llvm-project/commit/1683f84d289348ba6879635c4161979204f75230.diff

LOG: Revert "[InitUndef] handleSubReg should skip artificial subregs. (#116248)" (#117365)

Maybe not needed but to avoid conflicts with #117307
Without revert of this one, but reverting #117307, the
regenerated init-undef.mir became empty.

This reverts commit be15fd5085680cc5ed9ec4f4f2258b504cdd55db.

Added: 
    

Modified: 
    llvm/lib/CodeGen/InitUndef.cpp
    llvm/test/CodeGen/AArch64/init-undef.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/InitUndef.cpp b/llvm/lib/CodeGen/InitUndef.cpp
index d8b3190f31003e..d4ac131a32a959 100644
--- a/llvm/lib/CodeGen/InitUndef.cpp
+++ b/llvm/lib/CodeGen/InitUndef.cpp
@@ -164,14 +164,6 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
     TRI->getCoveringSubRegIndexes(*MRI, TargetRegClass, NeedDef,
                                   SubRegIndexNeedInsert);
 
-    // It's not possible to create the INIT_UNDEF when there is no register
-    // class associated for the subreg. This may happen for artificial subregs
-    // that are not directly addressable.
-    if (any_of(SubRegIndexNeedInsert, [&](unsigned Ind) -> bool {
-          return !TRI->getSubRegisterClass(TargetRegClass, Ind);
-        }))
-      continue;
-
     Register LatestReg = Reg;
     for (auto ind : SubRegIndexNeedInsert) {
       Changed = true;

diff  --git a/llvm/test/CodeGen/AArch64/init-undef.mir b/llvm/test/CodeGen/AArch64/init-undef.mir
index c9d23006d35234..7935c09d7df5ec 100644
--- a/llvm/test/CodeGen/AArch64/init-undef.mir
+++ b/llvm/test/CodeGen/AArch64/init-undef.mir
@@ -1,6 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=aarch64-- -aarch64-enable-subreg-liveness-tracking=false -run-pass=init-undef -o - %s | FileCheck %s
-# RUN: llc -mtriple=aarch64-- -aarch64-enable-subreg-liveness-tracking=true -run-pass=init-undef -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -run-pass=init-undef -o - %s | FileCheck %s
 
 ---
 name:            test_stxp_undef