[llvm] [AMDGPU][MC] Allow null where 128b or larger dst reg is expected (PR #115200)

[Matt Arsenault via llvm-commits]

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@@ -9720,6 +9720,12 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
     // The following code enables it for SReg_64 operands
     // used as source and destination. Remaining source
     // operands are handled in isInlinableImm.
+    //
+    // Additionally, allow null where destination of 128-bit or larger is
+    // expected.
+  case MCK_SReg_128:
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arsenm wrote:

Missing the 96-bit case 

https://github.com/llvm/llvm-project/pull/115200