[llvm] [SystemZ] Use getSignedConstant() where necessary (PR #117181)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 22 07:03:12 PST 2024
https://github.com/nikic updated https://github.com/llvm/llvm-project/pull/117181
>From 166a39f4970e43edf3d972d3fa2c37aebe7c018b Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Thu, 21 Nov 2024 16:50:37 +0100
Subject: [PATCH 1/2] [SystemZ] Use getSignedConstant()
This will avoid assertion failures once we disable implicit
truncation in getConstant().
Inside adjustSubwordCmp() I ended up suppressing the issue with
an explicit cast, because this code deals with a mix of unsigned
and signed immediates.
---
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 7 ++++---
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 13 +++++++------
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 90d7bd934af405..403d238aa5b528 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -671,7 +671,7 @@ void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
}
// Lower the displacement to a TargetConstant.
- Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT);
+ Disp = CurDAG->getSignedTargetConstant(AM.Disp, SDLoc(Base), VT);
}
void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
@@ -2024,8 +2024,9 @@ SDValue SystemZDAGToDAGISel::expandSelectBoolean(SDNode *Node) {
CurDAG->getConstant(IPM.XORValue, DL, MVT::i32));
if (IPM.AddValue)
- Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
- CurDAG->getConstant(IPM.AddValue, DL, MVT::i32));
+ Result =
+ CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
+ CurDAG->getSignedConstant(IPM.AddValue, DL, MVT::i32));
EVT VT = Node->getValueType(0);
if (VT == MVT::i32 && IPM.Bit == 31) {
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 78d91299a357dd..abeabab69cb9c9 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1444,15 +1444,15 @@ void SystemZTargetLowering::LowerAsmOperandForConstraint(
case 'K': // Signed 16-bit constant
if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isInt<16>(C->getSExtValue()))
- Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
- Op.getValueType()));
+ Ops.push_back(DAG.getSignedTargetConstant(
+ C->getSExtValue(), SDLoc(Op), Op.getValueType()));
return;
case 'L': // Signed 20-bit displacement (on all targets we support)
if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isInt<20>(C->getSExtValue()))
- Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
- Op.getValueType()));
+ Ops.push_back(DAG.getSignedTargetConstant(
+ C->getSExtValue(), SDLoc(Op), Op.getValueType()));
return;
case 'M': // 0x7fffffff
@@ -2578,7 +2578,7 @@ static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
// Make sure that the second operand is an i32 with the right value.
if (C.Op1.getValueType() != MVT::i32 ||
Value != ConstOp1->getZExtValue())
- C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
+ C.Op1 = DAG.getConstant((uint32_t)Value, DL, MVT::i32);
}
// Return true if Op is either an unextended load, or a load suitable
@@ -4623,7 +4623,8 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
Opcode = SystemZISD::ATOMIC_LOADW_ADD;
- Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
+ Src2 = DAG.getSignedConstant(-Const->getSExtValue(), DL,
+ Src2.getValueType());
}
SDValue AlignedAddr, BitShift, NegBitShift;
>From e2ebadde527400ccf35b66b66ff634e37d47bf15 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Fri, 22 Nov 2024 15:56:20 +0100
Subject: [PATCH 2/2] Adjust more places
---
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 8 ++++----
llvm/lib/Target/SystemZ/SystemZOperands.td | 16 ++++++++--------
.../Target/SystemZ/SystemZSelectionDAGInfo.cpp | 2 +-
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index abeabab69cb9c9..8f505b7e198cfa 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -3410,7 +3410,7 @@ SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
}
if (Invert) {
SDValue Mask =
- DAG.getSplatBuildVector(VT, DL, DAG.getConstant(-1, DL, MVT::i64));
+ DAG.getSplatBuildVector(VT, DL, DAG.getAllOnesConstant(DL, MVT::i64));
Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
}
if (Chain && Chain.getNode() != Cmp.getNode()) {
@@ -3571,7 +3571,7 @@ SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
// addition for it.
if (Offset != 0)
Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
- DAG.getConstant(Offset, DL, PtrVT));
+ DAG.getSignedConstant(Offset, DL, PtrVT));
return Result;
}
@@ -3834,7 +3834,7 @@ SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
const auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
int Offset = TFL->getReturnAddressOffset(MF);
SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, FrameAddr,
- DAG.getConstant(Offset, DL, PtrVT));
+ DAG.getSignedConstant(Offset, DL, PtrVT));
return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr,
MachinePointerInfo());
}
@@ -4584,7 +4584,7 @@ static void getCSAddressAndShifts(SDValue Addr, SelectionDAG &DAG, SDLoc DL,
// Get the address of the containing word.
AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
- DAG.getConstant(-4, DL, PtrVT));
+ DAG.getSignedConstant(-4, DL, PtrVT));
// Get the number of bits that the word must be rotated left in order
// to bring the field to the top bits of a GR32.
diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td
index 0221e2c53f2f49..64345ca3a1394e 100644
--- a/llvm/lib/Target/SystemZ/SystemZOperands.td
+++ b/llvm/lib/Target/SystemZ/SystemZOperands.td
@@ -220,8 +220,8 @@ def NEGLF32 : SDNodeXForm<imm, [{
// Truncate an immediate to a 8-bit signed quantity.
def SIMM8 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
- MVT::i64);
+ return CurDAG->getSignedTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
+ MVT::i64);
}]>;
// Truncate an immediate to a 8-bit unsigned quantity.
@@ -244,14 +244,14 @@ def UIMM12 : SDNodeXForm<imm, [{
// Truncate an immediate to a 16-bit signed quantity.
def SIMM16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
- MVT::i64);
+ return CurDAG->getSignedTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
+ MVT::i64);
}]>;
// Negate and then truncate an immediate to a 16-bit signed quantity.
def NEGSIMM16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(int16_t(-N->getZExtValue()), SDLoc(N),
- MVT::i64);
+ return CurDAG->getSignedTargetConstant(int16_t(-N->getZExtValue()), SDLoc(N),
+ MVT::i64);
}]>;
// Truncate an immediate to a 16-bit unsigned quantity.
@@ -268,8 +268,8 @@ def SIMM32 : SDNodeXForm<imm, [{
// Negate and then truncate an immediate to a 32-bit unsigned quantity.
def NEGSIMM32 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(int32_t(-N->getZExtValue()), SDLoc(N),
- MVT::i64);
+ return CurDAG->getSignedTargetConstant(int32_t(-N->getZExtValue()), SDLoc(N),
+ MVT::i64);
}]>;
// Truncate an immediate to a 32-bit unsigned quantity.
diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
index 4eb58e27f7ad79..c182c9890509fb 100644
--- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
@@ -53,7 +53,7 @@ static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op,
int64_t Adj = getMemMemLenAdj(Op);
SDValue LenAdj = DAG.getNode(ISD::ADD, DL, MVT::i64,
DAG.getZExtOrTrunc(Size, DL, MVT::i64),
- DAG.getConstant(0 - Adj, DL, MVT::i64));
+ DAG.getSignedConstant(0 - Adj, DL, MVT::i64));
return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte);
}
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