[llvm] 8b49091 - [Sparc] Use getSignedConstant() where necessary
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 22 05:59:20 PST 2024
Author: Nikita Popov
Date: 2024-11-22T14:58:26+01:00
New Revision: 8b4909111228e30ca3abdf3e40b04b9de9690714
URL: https://github.com/llvm/llvm-project/commit/8b4909111228e30ca3abdf3e40b04b9de9690714
DIFF: https://github.com/llvm/llvm-project/commit/8b4909111228e30ca3abdf3e40b04b9de9690714.diff
LOG: [Sparc] Use getSignedConstant() where necessary
This avoids assertion failures once we disable implicit
truncation in getConstant().
Added:
Modified:
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/lib/Target/Sparc/SparcISelLowering.cpp
llvm/lib/Target/Sparc/SparcInstr64Bit.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 67b498252197d2..461f859957041f 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -106,8 +106,8 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
} else {
Base = Addr.getOperand(0);
}
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
- MVT::i32);
+ Offset = CurDAG->getSignedTargetConstant(CN->getSExtValue(),
+ SDLoc(Addr), MVT::i32);
return true;
}
}
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 9bfc0fc1c3e32d..03a74b62543006 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2820,7 +2820,7 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
SDValue AlignedPtr =
IsOveraligned
? DAG.getNode(ISD::AND, dl, VT, AllocatedPtr,
- DAG.getConstant(-MaybeAlignment->value(), dl, VT))
+ DAG.getSignedConstant(-MaybeAlignment->value(), dl, VT))
: AllocatedPtr;
// Now that we are done, restore the bias and reserved spill area.
@@ -3367,8 +3367,8 @@ void SparcTargetLowering::LowerAsmOperandForConstraint(
case 'I':
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
if (isInt<13>(C->getSExtValue())) {
- Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
- Op.getValueType());
+ Result = DAG.getSignedTargetConstant(C->getSExtValue(), SDLoc(Op),
+ Op.getValueType());
break;
}
return;
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index 6b781374516509..56fab2f26a19e6 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -67,7 +67,7 @@ def : Pat<(i64 0), (COPY (i64 G0))>,
// The ALU instructions want their simm13 operands as i32 immediates.
// FIXME: This is no longer true, they are now pointer-sized.
def as_i32imm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
}]>;
def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
@@ -91,8 +91,8 @@ def HIX22 : SDNodeXForm<imm, [{
}]>;
// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
def LOX10 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N),
- MVT::i32);
+ return CurDAG->getSignedTargetConstant(~(~N->getZExtValue() & 0x3ff),
+ SDLoc(N), MVT::i32);
}]>;
def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
Requires<[Is64Bit]>;
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