[llvm] [RISCV] Add mvendorid/marchid/mimpid to CPU definitions (PR #116202)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `lld-x86_64-ubuntu-fast` running on `as-builder-4` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/33/builds/6998

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
11.963 [1500/64/2278] Building PPCGenSubtargetInfo.inc...
11.998 [1499/64/2279] Building SparcGenDAGISel.inc...
12.295 [1498/64/2280] Building PPCGenGlobalISel.inc...
12.440 [1497/64/2281] Building AArch64GenDAGISel.inc...
12.455 [1496/64/2282] Building SparcGenSearchableTables.inc...
12.464 [1495/64/2283] Building PPCGenFastISel.inc...
12.504 [1494/64/2284] Building NVPTXGenDAGISel.inc...
12.532 [1493/64/2285] Building SparcGenDisassemblerTables.inc...
12.540 [1492/64/2286] Building SparcGenRegisterInfo.inc...
12.580 [1491/64/2287] Building CXX object lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o
FAILED: lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o 
CCACHE_CPP2=yes CCACHE_HASHDIR=yes /usr/bin/ccache /usr/bin/c++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/lib/IR -I/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/lib/IR -I/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/include -I/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -fno-lifetime-dse -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wno-misleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG  -fno-exceptions -funwind-tables -fno-rtti -UNDEBUG -std=c++17 -MD -MT lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o -MF lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o.d -o lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o -c /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/lib/IR/Type.cpp
In file included from /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/lib/IR/Type.cpp:29:
/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:46:12: error: declaration of ‘llvm::RISCV::CPUModel llvm::RISCV::CPUInfo::CPUModel’ changes meaning of ‘CPUModel’ [-fpermissive]
   46 |   CPUModel CPUModel;
      |            ^~~~~~~~
/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:35:8: note: ‘CPUModel’ declared here as ‘struct llvm::RISCV::CPUModel’
   35 | struct CPUModel {
      |        ^~~~~~~~
12.617 [1491/63/2288] Building SparcGenSubtargetInfo.inc...
12.723 [1491/62/2289] Building PPCGenInstrInfo.inc...
12.794 [1491/61/2290] Building SystemZGenCallingConv.inc...
12.806 [1491/60/2291] Building SystemZGenHLASMAsmWriter.inc...
12.854 [1491/59/2292] Building PPCGenDAGISel.inc...
12.919 [1491/58/2293] Building SystemZGenDisassemblerTables.inc...
12.982 [1491/57/2294] Building SystemZGenMCCodeEmitter.inc...
12.983 [1491/56/2295] Building SystemZGenRegisterInfo.inc...
13.004 [1491/55/2296] Building SystemZGenAsmMatcher.inc...
13.017 [1491/54/2297] Building NVPTXGenInstrInfo.inc...
13.034 [1491/53/2298] Building SystemZGenGNUAsmWriter.inc...
13.114 [1491/52/2299] Building SystemZGenDAGISel.inc...
13.494 [1491/51/2300] Building CXX object lib/Object/CMakeFiles/LLVMObject.dir/IRSymtab.cpp.o
13.684 [1491/50/2301] Building RISCVGenMCPseudoLowering.inc...
13.690 [1491/49/2302] Building VEGenCallingConv.inc...
13.792 [1491/48/2303] Building VEGenAsmMatcher.inc...
13.809 [1491/47/2304] Building RISCVGenCompressInstEmitter.inc...
13.974 [1491/46/2305] Building VEGenRegisterInfo.inc...
13.974 [1491/45/2306] Building RISCVGenRegisterBank.inc...
14.043 [1491/44/2307] Building RISCVGenO0PreLegalizeGICombiner.inc...
14.101 [1491/43/2308] Building SystemZGenSubtargetInfo.inc...
14.113 [1491/42/2309] Building RISCVGenMacroFusion.inc...
14.161 [1491/41/2310] Building RISCVGenRegisterInfo.inc...
14.167 [1491/40/2311] Building VEGenAsmWriter.inc...
14.175 [1491/39/2312] Building RISCVGenMCCodeEmitter.inc...
14.179 [1491/38/2313] Building RISCVGenPostLegalizeGICombiner.inc...
14.249 [1491/37/2314] Building RISCVGenAsmMatcher.inc...
14.321 [1491/36/2315] Building VEGenMCCodeEmitter.inc...
14.325 [1491/35/2316] Building RISCVGenAsmWriter.inc...
14.352 [1491/34/2317] Building RISCVGenDisassemblerTables.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/116202