[llvm] d1dae1e - Revert "[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)" chain
Mikhail Goncharov via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 22 05:11:15 PST 2024
Author: Mikhail Goncharov
Date: 2024-11-22T14:09:13+01:00
New Revision: d1dae1e8612a2fa69d0d731e16d07baf8ce10c85
URL: https://github.com/llvm/llvm-project/commit/d1dae1e8612a2fa69d0d731e16d07baf8ce10c85
DIFF: https://github.com/llvm/llvm-project/commit/d1dae1e8612a2fa69d0d731e16d07baf8ce10c85.diff
LOG: Revert "[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)" chain
This reverts commit b36fcf4f493ad9d30455e178076d91be99f3a7d8.
This reverts commit c11b6b1b8af7454b35eef342162dc2cddf54b4de.
This reverts commit 775148f2367600f90d28684549865ee9ea2f11be.
multiple bot build breakages, e.g. https://lab.llvm.org/buildbot/#/builders/3/builds/8076
Added:
Modified:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
llvm/include/llvm/TargetParser/RISCVTargetParser.h
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/lib/TargetParser/RISCVTargetParser.cpp
llvm/test/TableGen/riscv-target-def.td
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Removed:
clang/test/CodeGen/RISCV/builtin-cpu-is-error.c
clang/test/CodeGen/RISCV/builtin-cpu-is.c
################################################################################
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 2384b322c50f92..c61ee7ee203923 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -512,10 +512,3 @@ bool RISCVTargetInfo::validateGlobalRegisterVariable(
}
return false;
}
-
-bool RISCVTargetInfo::validateCpuIs(StringRef CPUName) const {
- assert(getTriple().isOSLinux() &&
- "__builtin_cpu_is() is only supported for Linux.");
-
- return llvm::RISCV::hasValidCPUModel(CPUName);
-}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 3544ea64cb5e77..3b418585ab4a39 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -128,10 +128,8 @@ class RISCVTargetInfo : public TargetInfo {
}
bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
- bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
bool validateCpuSupports(StringRef Feature) const override;
- bool validateCpuIs(StringRef CPUName) const override;
bool isValidFeatureName(StringRef Name) const override;
bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 4b96bdb709c777..ff7132fd8bc1e7 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -66,7 +66,6 @@
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
#include "llvm/TargetParser/RISCVISAInfo.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/X86TargetParser.h"
#include <optional>
#include <utility>
@@ -22694,47 +22693,6 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
return nullptr;
}
-Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) {
- const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
- StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
- return EmitRISCVCpuIs(CPUStr);
-}
-
-Value *CodeGenFunction::EmitRISCVCpuIs(StringRef CPUStr) {
- llvm::Type *Int32Ty = Builder.getInt32Ty();
- llvm::Type *Int64Ty = Builder.getInt64Ty();
- llvm::StructType *StructTy = llvm::StructType::get(Int32Ty, Int64Ty, Int64Ty);
- llvm::Constant *RISCVCPUModel =
- CGM.CreateRuntimeVariable(StructTy, "__riscv_cpu_model");
- cast<llvm::GlobalValue>(RISCVCPUModel)->setDSOLocal(true);
-
- auto loadRISCVCPUID = [&](unsigned Index) {
- Value *Ptr = Builder.CreateStructGEP(StructTy, RISCVCPUModel, Index);
- Value *CPUID = Builder.CreateAlignedLoad(StructTy->getTypeAtIndex(Index),
- Ptr, llvm::MaybeAlign());
- return CPUID;
- };
-
- const llvm::RISCV::CPUModel Model = llvm::RISCV::getCPUModel(CPUStr);
-
- // Compare mvendorid.
- Value *VendorID = loadRISCVCPUID(0);
- Value *Result =
- Builder.CreateICmpEQ(VendorID, Builder.getInt32(Model.MVendorID));
-
- // Compare marchid.
- Value *ArchID = loadRISCVCPUID(1);
- Result = Builder.CreateAnd(
- Result, Builder.CreateICmpEQ(ArchID, Builder.getInt64(Model.MArchID)));
-
- // Compare mimpid.
- Value *ImpID = loadRISCVCPUID(2);
- Result = Builder.CreateAnd(
- Result, Builder.CreateICmpEQ(ImpID, Builder.getInt64(Model.MImpID)));
-
- return Result;
-}
-
Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
const CallExpr *E,
ReturnValueSlot ReturnValue) {
@@ -22743,8 +22701,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
return EmitRISCVCpuSupports(E);
if (BuiltinID == Builtin::BI__builtin_cpu_init)
return EmitRISCVCpuInit();
- if (BuiltinID == Builtin::BI__builtin_cpu_is)
- return EmitRISCVCpuIs(E);
SmallVector<Value *, 4> Ops;
llvm::Type *ResultType = ConvertType(E->getType());
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
index 5c4d76c2267a77..fcc1013d7361ec 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -4730,8 +4730,6 @@ class CodeGenFunction : public CodeGenTypeCache {
llvm::Value *EmitRISCVCpuSupports(const CallExpr *E);
llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs);
llvm::Value *EmitRISCVCpuInit();
- llvm::Value *EmitRISCVCpuIs(const CallExpr *E);
- llvm::Value *EmitRISCVCpuIs(StringRef CPUStr);
void AddAMDGPUFenceAddressSpaceMMRA(llvm::Instruction *Inst,
const CallExpr *E);
diff --git a/clang/test/CodeGen/RISCV/builtin-cpu-is-error.c b/clang/test/CodeGen/RISCV/builtin-cpu-is-error.c
deleted file mode 100644
index ce5e1420f7f456..00000000000000
--- a/clang/test/CodeGen/RISCV/builtin-cpu-is-error.c
+++ /dev/null
@@ -1,7 +0,0 @@
-// RUN: not %clang_cc1 -triple riscv64-unknown-linux-gnu -emit-llvm %s -o - 2>&1 \
-// RUN: | FileCheck %s
-
-// CHECK: error: invalid cpu name for builtin
-int test_cpu_is_invalid_cpu() {
- return __builtin_cpu_is("generic-rv64");
-}
diff --git a/clang/test/CodeGen/RISCV/builtin-cpu-is.c b/clang/test/CodeGen/RISCV/builtin-cpu-is.c
deleted file mode 100644
index 3cb3558a751ae3..00000000000000
--- a/clang/test/CodeGen/RISCV/builtin-cpu-is.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
-// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm %s -o - \
-// RUN: | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
-
-// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(
-// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
-// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
-// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
-// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
-// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
-// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
-// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
-// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
-// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
-// CHECK-RV64-NEXT: ret i32 [[CONV]]
-//
-int test_cpu_is_veyron_v1() {
- return __builtin_cpu_is("veyron-v1");
-}
-
-// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_spacemit_x60(
-// CHECK-RV64-SAME: ) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
-// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1808
-// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
-// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372035378380799
-// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
-// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
-// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1152921505839391232
-// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
-// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
-// CHECK-RV64-NEXT: ret i32 [[CONV]]
-//
-int test_cpu_is_spacemit_x60() {
- return __builtin_cpu_is("spacemit-x60");
-}
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index c237e1ddd6b381..c75778952e0f51 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -32,21 +32,6 @@ struct RISCVExtensionBitmask {
};
} // namespace RISCVExtensionBitmaskTable
-struct CPUModel {
- uint32_t MVendorID;
- uint64_t MArchID;
- uint64_t MImpID;
-};
-
-struct CPUInfo {
- StringLiteral Name;
- StringLiteral DefaultMarch;
- bool FastScalarUnalignedAccess;
- bool FastVectorUnalignedAccess;
- CPUModel Model;
- bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
-};
-
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
@@ -60,8 +45,6 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
bool hasFastScalarUnalignedAccess(StringRef CPU);
bool hasFastVectorUnalignedAccess(StringRef CPU);
-bool hasValidCPUModel(StringRef CPU);
-CPUModel getCPUModel(StringRef CPU);
} // namespace RISCV
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 03a48ff3c17586..e96281bb46950e 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -49,9 +49,6 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
- int MVendorID = 0;
- int MArchID = 0;
- int MImpID = 0;
}
class RISCVTuneProcessorModel<string n,
@@ -460,11 +457,7 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion,
- TuneLDADDFusion]> {
- let MVendorID = 0x61f;
- let MArchID = 0x8000000000010000;
- let MImpID = 0x111;
-}
+ TuneLDADDFusion]>;
def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
XiangShanNanHuModel,
@@ -510,11 +503,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
[TuneDLenFactor2,
TuneOptimizedNF2SegmentLoadStore,
TuneOptimizedNF3SegmentLoadStore,
- TuneOptimizedNF4SegmentLoadStore]> {
- let MVendorID = 0x710;
- let MArchID = 0x8000000058000001;
- let MImpID = 0x1000000049772200;
-}
+ TuneOptimizedNF4SegmentLoadStore]>;
def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
NoSchedModel,
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 625645a99e12fc..da3fbc04300e2f 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -21,22 +21,24 @@ namespace RISCV {
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
- FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
+ FAST_VECTOR_UNALIGN) \
CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
+struct CPUInfo {
+ StringLiteral Name;
+ StringLiteral DefaultMarch;
+ bool FastScalarUnalignedAccess;
+ bool FastVectorUnalignedAccess;
+ bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
+};
+
constexpr CPUInfo RISCVCPUInfo[] = {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
- FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
- { \
- NAME, \
- DEFAULT_MARCH, \
- FAST_SCALAR_UNALIGN, \
- FAST_VECTOR_UNALIGN, \
- {MVENDORID, MARCHID, MIMPID}, \
- },
+ FAST_VECTOR_UNALIGN) \
+ {NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
@@ -57,18 +59,6 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {
return Info && Info->FastVectorUnalignedAccess;
}
-bool hasValidCPUModel(StringRef CPU) {
- const CPUModel Model = getCPUModel(CPU);
- return Model.MVendorID != 0 && Model.MArchID != 0 && Model.MImpID != 0;
-}
-
-CPUModel getCPUModel(StringRef CPU) {
- const CPUInfo *Info = getCPUInfoByName(CPU);
- if (!Info)
- return {0, 0, 0};
- return Info->Model;
-}
-
bool parseCPU(StringRef CPU, bool IsRV64) {
const CPUInfo *Info = getCPUInfoByName(CPU);
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index 79178731f12a75..c071cfd731cb52 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -81,9 +81,6 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
- int MVendorID = 0;
- int MArchID = 0;
- int MImpID = 0;
}
class RISCVTuneProcessorModel<string n,
@@ -163,13 +160,13 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK: #endif // GET_SUPPORTED_PROFILES
// CHECK: #ifndef PROC
-// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
+// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)
// CHECK-NEXT: #endif
-// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
-// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
-// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
-// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
+// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0)
+// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0)
+// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
+// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
// CHECK: #undef PROC
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 723f1d72b5159c..39211aab6f2d1e 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/DenseSet.h"
-#include "llvm/Support/Format.h"
#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -167,7 +166,7 @@ static void emitRISCVProfiles(const RecordKeeper &Records, raw_ostream &OS) {
static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
<< "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN"
- << ", FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)\n"
+ << ", FAST_VECTOR_UNALIGN)\n"
<< "#endif\n\n";
// Iterate on all definition records.
@@ -193,17 +192,8 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
printMArch(OS, Features);
else
OS << MArch;
-
- uint32_t MVendorID = Rec->getValueAsInt("MVendorID");
- uint64_t MArchID = Rec->getValueAsInt("MArchID");
- uint64_t MImpID = Rec->getValueAsInt("MImpID");
-
OS << "\"}, " << FastScalarUnalignedAccess << ", "
- << FastVectorUnalignedAccess;
- OS << ", " << format_hex(MVendorID, 10);
- OS << ", " << format_hex(MArchID, 18);
- OS << ", " << format_hex(MImpID, 18);
- OS << ")\n";
+ << FastVectorUnalignedAccess << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
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