[llvm] [RISCV] Add mvendorid/marchid/mimpid to CPU definitions (PR #116202)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-devrel-x86-64` running on `ml-opt-devrel-x86-64-b1` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/175/builds/8984

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
23.250 [2493/64/1179] Building CXX object lib/Target/LoongArch/TargetInfo/CMakeFiles/LLVMLoongArchInfo.dir/LoongArchTargetInfo.cpp.o
23.291 [2492/64/1180] Building CXX object lib/Target/LoongArch/MCTargetDesc/CMakeFiles/LLVMLoongArchDesc.dir/LoongArchTargetStreamer.cpp.o
23.311 [2491/64/1181] Building PPCGenDisassemblerTables.inc...
23.353 [2490/64/1182] Building PPCGenAsmMatcher.inc...
23.418 [2489/64/1183] Building NVPTXGenRegisterInfo.inc...
23.493 [2488/64/1184] Building PPCGenAsmWriter.inc...
23.578 [2487/64/1185] Building PPCGenMCCodeEmitter.inc...
23.677 [2486/64/1186] Building PPCGenRegisterBank.inc...
23.794 [2485/64/1187] Building PPCGenRegisterInfo.inc...
23.830 [2484/64/1188] Building CXX object lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o
FAILED: lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o 
ccache /usr/bin/c++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/b/ml-opt-devrel-x86-64-b1/build/lib/IR -I/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/IR -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-devrel-x86-64-b1/build/include -I/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -fno-lifetime-dse -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG  -fno-exceptions -funwind-tables -fno-rtti -UNDEBUG -std=c++17 -MD -MT lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o -MF lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o.d -o lib/IR/CMakeFiles/LLVMCore.dir/Type.cpp.o -c /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/IR/Type.cpp
In file included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/IR/Type.cpp:29:
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:46:12: error: declaration of ‘llvm::RISCV::CPUModel llvm::RISCV::CPUInfo::CPUModel’ changes meaning of ‘CPUModel’ [-fpermissive]
   46 |   CPUModel CPUModel;
      |            ^~~~~~~~
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:35:8: note: ‘CPUModel’ declared here as ‘struct llvm::RISCV::CPUModel’
   35 | struct CPUModel {
      |        ^~~~~~~~
23.877 [2484/63/1189] Building MipsGenInstrInfo.inc...
24.261 [2484/62/1190] Building SparcGenCallingConv.inc...
24.305 [2484/61/1191] Building SparcGenAsmMatcher.inc...
24.472 [2484/60/1192] Building SparcGenAsmWriter.inc...
24.533 [2484/59/1193] Building SparcGenRegisterInfo.inc...
24.572 [2484/58/1194] Building SparcGenMCCodeEmitter.inc...
24.591 [2484/57/1195] Building NVPTXGenSubtargetInfo.inc...
24.593 [2484/56/1196] Building NVPTXGenAsmWriter.inc...
24.610 [2484/55/1197] Building HexagonGenInstrInfo.inc...
25.000 [2484/54/1198] Building SparcGenSubtargetInfo.inc...
25.172 [2484/53/1199] Building PPCGenSubtargetInfo.inc...
25.375 [2484/52/1200] Building SparcGenSearchableTables.inc...
25.773 [2484/51/1201] Building SystemZGenDisassemblerTables.inc...
25.800 [2484/50/1202] Building CXX object lib/Object/CMakeFiles/LLVMObject.dir/IRSymtab.cpp.o
26.052 [2484/49/1203] Building SystemZGenCallingConv.inc...
26.258 [2484/48/1204] Building SystemZGenAsmMatcher.inc...
26.277 [2484/47/1205] Building SystemZGenGNUAsmWriter.inc...
26.509 [2484/46/1206] Building SystemZGenHLASMAsmWriter.inc...
26.764 [2484/45/1207] Building PPCGenDAGISel.inc...
26.852 [2484/44/1208] Building PPCGenGlobalISel.inc...
27.159 [2484/43/1209] Building SystemZGenDAGISel.inc...
27.286 [2484/42/1210] Building PPCGenInstrInfo.inc...
27.775 [2484/41/1211] Building NVPTXGenInstrInfo.inc...
27.913 [2484/40/1212] Building NVPTXGenDAGISel.inc...
28.285 [2484/39/1213] Building X86GenInstrMapping.inc...
29.188 [2484/38/1214] Building RISCVGenMacroFusion.inc...
29.189 [2484/37/1215] Building RISCVGenCompressInstEmitter.inc...
29.223 [2484/36/1216] Building RISCVGenRegisterBank.inc...
29.404 [2484/35/1217] Building RISCVGenMCPseudoLowering.inc...
29.668 [2484/34/1218] Building RISCVGenRegisterInfo.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/116202