[llvm] [RISCV] Add mvendorid/marchid/mimpid to CPU definitions (PR #116202)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 22 03:54:33 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116202
>From 23c84c353be3808ff92a78f06f4d03eec343d8ff Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 14 Nov 2024 18:12:01 +0800
Subject: [PATCH 1/4] [RISCV] Add mvendorid/marchid/mimpid to CPU definitions
We can get these information via `sys_riscv_hwprobe`.
This can be used to implement `__builtin_cpu_is`.
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 9 ++++++++-
llvm/lib/TargetParser/RISCVTargetParser.cpp | 17 ++++++++++++++---
llvm/test/TableGen/riscv-target-def.td | 13 ++++++++-----
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 18 ++++++++++++++++--
4 files changed, 46 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e96281bb46950e..5ec48eb0420ccd 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -49,6 +49,9 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
+ int MVendorID = 0;
+ int MArchID = 0;
+ int MImpID = 0;
}
class RISCVTuneProcessorModel<string n,
@@ -457,7 +460,11 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion,
- TuneLDADDFusion]>;
+ TuneLDADDFusion]> {
+ let MVendorID = 0x61f;
+ let MArchID = 0x8000000000010000;
+ let MImpID = 0x111;
+}
def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
XiangShanNanHuModel,
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index da3fbc04300e2f..d834771369e7c3 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -21,7 +21,7 @@ namespace RISCV {
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
- FAST_VECTOR_UNALIGN) \
+ FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
@@ -32,13 +32,24 @@ struct CPUInfo {
StringLiteral DefaultMarch;
bool FastScalarUnalignedAccess;
bool FastVectorUnalignedAccess;
+ uint32_t MVendorID;
+ uint64_t MArchID;
+ uint64_t MImpID;
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
};
constexpr CPUInfo RISCVCPUInfo[] = {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
- FAST_VECTOR_UNALIGN) \
- {NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
+ FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
+ { \
+ NAME, \
+ DEFAULT_MARCH, \
+ FAST_SCALAR_UNALIGN, \
+ FAST_VECTOR_UNALIGN, \
+ MVENDORID, \
+ MARCHID, \
+ MIMPID, \
+ },
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index c071cfd731cb52..3267c282cffda7 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -81,6 +81,9 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
+ int MVendorID = 0;
+ int MArchID = 0;
+ int MImpID = 0;
}
class RISCVTuneProcessorModel<string n,
@@ -160,13 +163,13 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK: #endif // GET_SUPPORTED_PROFILES
// CHECK: #ifndef PROC
-// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)
+// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
// CHECK-NEXT: #endif
-// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0)
-// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0)
-// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
-// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
+// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
+// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
+// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
+// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK: #undef PROC
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 39211aab6f2d1e..4ab45cfc09f133 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/DenseSet.h"
+#include "llvm/Support/Format.h"
#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -166,7 +167,7 @@ static void emitRISCVProfiles(const RecordKeeper &Records, raw_ostream &OS) {
static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
<< "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN"
- << ", FAST_VECTOR_UNALIGN)\n"
+ << ", FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)\n"
<< "#endif\n\n";
// Iterate on all definition records.
@@ -182,6 +183,10 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
return Feature->getValueAsString("Name") == "unaligned-vector-mem";
});
+ bool IsRV64 = any_of(Features, [&](auto &Feature) {
+ return Feature->getValueAsString("Name") == "64bit";
+ });
+
OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
<< "\"}, {\"";
@@ -192,8 +197,17 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
printMArch(OS, Features);
else
OS << MArch;
+
+ uint32_t MVendorID = Rec->getValueAsInt("MVendorID");
+ uint64_t MArchID = Rec->getValueAsInt("MArchID");
+ uint64_t MImpID = Rec->getValueAsInt("MImpID");
+
OS << "\"}, " << FastScalarUnalignedAccess << ", "
- << FastVectorUnalignedAccess << ")\n";
+ << FastVectorUnalignedAccess;
+ OS << ", " << format_hex(MVendorID, 10);
+ OS << ", " << format_hex(MArchID, IsRV64 ? 18 : 10);
+ OS << ", " << format_hex(MImpID, IsRV64 ? 18 : 10);
+ OS << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
>From 2e26b90ccec63a8a6fc6cdf561388c017d086c2b Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 15 Nov 2024 12:40:15 +0800
Subject: [PATCH 2/4] Add spacemit-x60
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5ec48eb0420ccd..03a48ff3c17586 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -510,7 +510,11 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
[TuneDLenFactor2,
TuneOptimizedNF2SegmentLoadStore,
TuneOptimizedNF3SegmentLoadStore,
- TuneOptimizedNF4SegmentLoadStore]>;
+ TuneOptimizedNF4SegmentLoadStore]> {
+ let MVendorID = 0x710;
+ let MArchID = 0x8000000058000001;
+ let MImpID = 0x1000000049772200;
+}
def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
NoSchedModel,
>From 721a6226d9dfc7c28af0448c0a56be547d0f4f9b Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 15 Nov 2024 12:48:07 +0800
Subject: [PATCH 3/4] Emit 64bits literal imm
---
llvm/test/TableGen/riscv-target-def.td | 4 ++--
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 8 ++------
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index 3267c282cffda7..79178731f12a75 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -166,9 +166,9 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
// CHECK-NEXT: #endif
-// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
+// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
-// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
+// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK: #undef PROC
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 4ab45cfc09f133..723f1d72b5159c 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -183,10 +183,6 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
return Feature->getValueAsString("Name") == "unaligned-vector-mem";
});
- bool IsRV64 = any_of(Features, [&](auto &Feature) {
- return Feature->getValueAsString("Name") == "64bit";
- });
-
OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
<< "\"}, {\"";
@@ -205,8 +201,8 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
OS << "\"}, " << FastScalarUnalignedAccess << ", "
<< FastVectorUnalignedAccess;
OS << ", " << format_hex(MVendorID, 10);
- OS << ", " << format_hex(MArchID, IsRV64 ? 18 : 10);
- OS << ", " << format_hex(MImpID, IsRV64 ? 18 : 10);
+ OS << ", " << format_hex(MArchID, 18);
+ OS << ", " << format_hex(MImpID, 18);
OS << ")\n";
}
OS << "\n#undef PROC\n";
>From 15720685e332b8293661e78866a9cb23b3dc932b Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 15 Nov 2024 12:56:06 +0800
Subject: [PATCH 4/4] Move CPUInfo to header and add CPUModel struct
---
.../include/llvm/TargetParser/RISCVTargetParser.h | 15 +++++++++++++++
llvm/lib/TargetParser/RISCVTargetParser.cpp | 15 +--------------
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index c75778952e0f51..a365205ba2ecb6 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -32,6 +32,21 @@ struct RISCVExtensionBitmask {
};
} // namespace RISCVExtensionBitmaskTable
+struct CPUModel {
+ uint32_t MVendorID;
+ uint64_t MArchID;
+ uint64_t MImpID;
+};
+
+struct CPUInfo {
+ StringLiteral Name;
+ StringLiteral DefaultMarch;
+ bool FastScalarUnalignedAccess;
+ bool FastVectorUnalignedAccess;
+ CPUModel CPUModel;
+ bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
+};
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index d834771369e7c3..f4d09d1e302408 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -27,17 +27,6 @@ enum CPUKind : unsigned {
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
-struct CPUInfo {
- StringLiteral Name;
- StringLiteral DefaultMarch;
- bool FastScalarUnalignedAccess;
- bool FastVectorUnalignedAccess;
- uint32_t MVendorID;
- uint64_t MArchID;
- uint64_t MImpID;
- bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
-};
-
constexpr CPUInfo RISCVCPUInfo[] = {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
@@ -46,9 +35,7 @@ constexpr CPUInfo RISCVCPUInfo[] = {
DEFAULT_MARCH, \
FAST_SCALAR_UNALIGN, \
FAST_VECTOR_UNALIGN, \
- MVENDORID, \
- MARCHID, \
- MIMPID, \
+ {MVENDORID, MARCHID, MIMPID}, \
},
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
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