[llvm] fdb1bf9 - [LoongArch] Use getSignedConstant() where necessary (#117172)
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Fri Nov 22 02:23:15 PST 2024
Author: Nikita Popov
Date: 2024-11-22T11:23:11+01:00
New Revision: fdb1bf9b5949b2a97041922405a812a060fce5f4
URL: https://github.com/llvm/llvm-project/commit/fdb1bf9b5949b2a97041922405a812a060fce5f4
DIFF: https://github.com/llvm/llvm-project/commit/fdb1bf9b5949b2a97041922405a812a060fce5f4.diff
LOG: [LoongArch] Use getSignedConstant() where necessary (#117172)
To prevent assertion failures when we disable implicit truncation in
getConstant().
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
index 70ed1e6fbdbdac..d330f953556018 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
@@ -61,7 +61,7 @@ void LoongArchDAGToDAGISel::Select(SDNode *Node) {
SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
// The instructions in the sequence are handled here.
for (LoongArchMatInt::Inst &Inst : LoongArchMatInt::generateInstSeq(Imm)) {
- SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, GRLenVT);
+ SDValue SDImm = CurDAG->getSignedTargetConstant(Inst.Imm, DL, GRLenVT);
switch (Inst.Opc) {
case LoongArch::LU12I_W:
Result = CurDAG->getMachineNode(Inst.Opc, DL, GRLenVT, SDImm);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 5c567ed4a6f724..1abb428175eea7 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -1533,7 +1533,7 @@ SDValue LoongArchTargetLowering::lowerFRAMEADDR(SDValue Op,
while (Depth--) {
int Offset = -(GRLenInBytes * 2);
SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
- DAG.getIntPtrConstant(Offset, DL));
+ DAG.getSignedConstant(Offset, DL, VT));
FrameAddr =
DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
}
@@ -2548,7 +2548,8 @@ SDValue LoongArchTargetLowering::lowerShiftLeftParts(SDValue Op,
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue One = DAG.getConstant(1, DL, VT);
- SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);
+ SDValue MinusGRLen =
+ DAG.getSignedConstant(-(int)Subtarget.getGRLen(), DL, VT);
SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
@@ -2599,7 +2600,8 @@ SDValue LoongArchTargetLowering::lowerShiftRightParts(SDValue Op,
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue One = DAG.getConstant(1, DL, VT);
- SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);
+ SDValue MinusGRLen =
+ DAG.getSignedConstant(-(int)Subtarget.getGRLen(), DL, VT);
SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
@@ -6123,8 +6125,8 @@ void LoongArchTargetLowering::LowerAsmOperandForConstraint(
if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
uint64_t CVal = C->getSExtValue();
if (isInt<16>(CVal))
- Ops.push_back(
- DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
+ Ops.push_back(DAG.getSignedTargetConstant(CVal, SDLoc(Op),
+ Subtarget.getGRLenVT()));
}
return;
case 'I':
@@ -6132,8 +6134,8 @@ void LoongArchTargetLowering::LowerAsmOperandForConstraint(
if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
uint64_t CVal = C->getSExtValue();
if (isInt<12>(CVal))
- Ops.push_back(
- DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
+ Ops.push_back(DAG.getSignedTargetConstant(CVal, SDLoc(Op),
+ Subtarget.getGRLenVT()));
}
return;
case 'J':
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index cd1500229f4aa9..7993f4f1326937 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -481,8 +481,8 @@ def simm12_plus1 : ImmLeaf<GRLenVT,
// Return the negation of an immediate value.
def NegImm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedTargetConstant(-N->getSExtValue(), SDLoc(N),
+ N->getValueType(0));
}]>;
// FP immediate patterns.
@@ -538,16 +538,16 @@ def AddiPair : PatLeaf<(imm), [{
// Return -2048 if immediate is negative or 2047 if positive.
def AddiPairImmLarge : SDNodeXForm<imm, [{
int64_t Imm = N->getSExtValue() < 0 ? -2048 : 2047;
- return CurDAG->getTargetConstant(Imm, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedTargetConstant(Imm, SDLoc(N),
+ N->getValueType(0));
}]>;
// Return imm - (imm < 0 ? -2048 : 2047).
def AddiPairImmSmall : SDNodeXForm<imm, [{
int64_t Imm = N->getSExtValue();
int64_t Adj = Imm < 0 ? -2048 : 2047;
- return CurDAG->getTargetConstant(Imm - Adj, SDLoc(N),
- N->getValueType(0));
+ return CurDAG->getSignedTargetConstant(Imm - Adj, SDLoc(N),
+ N->getValueType(0));
}]>;
// Check if (mul r, imm) can be optimized to (SLLI (ALSL r, r, i0), i1),
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 1a267b3e42a30d..ced430216b2fed 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -223,12 +223,14 @@ def f64imm_vldi : PatLeaf<(fpimm), [{
def to_f32imm_vldi : SDNodeXForm<fpimm, [{
uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue();
x = (0b11011 << 8) | (((x >> 24) & 0xc0) ^ 0x40) | ((x >> 19) & 0x3f);
- return CurDAG->getTargetConstant(SignExtend32<13>(x), SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N),
+ MVT::i32);
}]>;
def to_f64imm_vldi : SDNodeXForm<fpimm, [{
uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue();
x = (0b11100 << 8) | (((x >> 56) & 0xc0) ^ 0x40) | ((x >> 48) & 0x3f);
- return CurDAG->getTargetConstant(SignExtend32<13>(x), SDLoc(N), MVT::i32);
+ return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N),
+ MVT::i32);
}]>;
//===----------------------------------------------------------------------===//
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