[llvm] 30df659 - [GlobalISel] Correct comment about type vs register class (#116083)

via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 21 11:18:37 PST 2024


Author: Daniel Sanders
Date: 2024-11-21T11:18:34-08:00
New Revision: 30df65949598f298b508d5d32688e901c6f66a57

URL: https://github.com/llvm/llvm-project/commit/30df65949598f298b508d5d32688e901c6f66a57
DIFF: https://github.com/llvm/llvm-project/commit/30df65949598f298b508d5d32688e901c6f66a57.diff

LOG: [GlobalISel] Correct comment about type vs register class (#116083)

Type and register class aren't mutually exclusive in gMIR but there's also
no target-independent requirement (yet?) to have both on target instructions.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index 827da6a2ed8098..30cd3ce3baa502 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -148,9 +148,8 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
   LLT DstTy = MRI.getType(R);
 
   // Handle the case where this is called on a register that does not have a
-  // type constraint (i.e. it has a register class constraint instead). This is
-  // unlikely to occur except by looking through copies but it is possible for
-  // the initial register being queried to be in this state.
+  // type constraint. For example, it may be post-ISel or this target might not
+  // preserve the type when early-selecting instructions.
   if (!DstTy.isValid()) {
     Known = KnownBits();
     return;


        


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