[llvm] [AArch64] Fix STG instruction being moved past memcpy (PR #117191)
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 21 08:53:40 PST 2024
https://github.com/ostannard created https://github.com/llvm/llvm-project/pull/117191
When merging STG instructions used for AArch64 stack tagging, we were stopping on reaching a load or store instruction, but not calls, so it was possible for an STG to be moved past a call to memcpy.
This test case (reduced from fuzzer-generated C code) was the result of StackColoring merging allocas A and B into one stack slot, and StackSafetyAnalysis proving that B does not need tagging, so we end up with tagged and untagged objects in the same stack slot. The tagged object (A) is live first, so it is important that it's memory is restored to the background tag before it gets reused to hold B.
>From c0bee492b0a79d3ac49458decca7d6f9407dbfaf Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Thu, 21 Nov 2024 16:18:43 +0000
Subject: [PATCH 1/3] Add test showing bug
---
.../stack-tagging-merge-past-memcpy.mir | 242 ++++++++++++++++++
1 file changed, 242 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
new file mode 100644
index 00000000000000..4bfe3d17633d7b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
@@ -0,0 +1,242 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s
+--- |
+ source_filename = "<stdin>"
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+ target triple = "aarch64-unknown-none-elf"
+
+ @glob = global [8 x i32] zeroinitializer, align 4
+
+ define dso_local void @F78(ptr %B) {
+ entry:
+ %0 = load i32, ptr %B, align 4
+ ret void
+ }
+
+ define void @F55() #0 {
+ entry:
+ %basetag = call ptr @llvm.aarch64.irg.sp(i64 0)
+ %A = alloca i32, i32 8, align 16
+ %A.tag = call ptr @llvm.aarch64.tagp.p0(ptr %A, ptr %basetag, i64 0)
+ %B = alloca i32, i32 8, align 4
+ %C = alloca i32, i32 8, align 16
+ %C.tag = call ptr @llvm.aarch64.tagp.p0(ptr %C, ptr %basetag, i64 1)
+ call void @llvm.aarch64.settag(ptr %C.tag, i64 32)
+ call void @F56(ptr %C.tag)
+ call void @llvm.lifetime.start.p0(i64 32, ptr %A)
+ call void @llvm.aarch64.settag(ptr %A.tag, i64 32)
+ call void @F56(ptr %A.tag)
+ call void @llvm.aarch64.settag(ptr %A, i64 32)
+ call void @llvm.lifetime.end.p0(i64 32, ptr %A)
+ call void @llvm.lifetime.start.p0(i64 32, ptr %A)
+ call void @llvm.memcpy.p0.p0.i64(ptr align 4 %A, ptr align 4 @glob, i64 32, i1 false)
+ call void @F78(ptr %A)
+ call void @llvm.lifetime.end.p0(i64 32, ptr %A)
+ call void @llvm.aarch64.settag(ptr %C, i64 32)
+ ret void
+ }
+
+ declare void @F56(ptr)
+
+ declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
+
+ declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
+
+ declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2
+
+ declare void @llvm.aarch64.settag(ptr nocapture writeonly, i64) #3
+
+ declare ptr @llvm.aarch64.irg.sp(i64) #4
+
+ declare ptr @llvm.aarch64.tagp.p0(ptr, ptr, i64 immarg) #5
+
+ declare void @llvm.aarch64.settag.zero(ptr nocapture writeonly, i64) #3
+
+ declare void @llvm.aarch64.stgp(ptr nocapture writeonly, i64, i64) #3
+
+ attributes #0 = { sanitize_memtag "target-features"="+mte,+strict-align" }
+ attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
+ attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
+ attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
+ attributes #4 = { nocallback nofree nosync nounwind willreturn }
+ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(none) }
+
+...
+---
+name: F78
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: true
+isSSA: false
+noVRegs: true
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHCatchret: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: true
+registers: []
+liveins: []
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ isCalleeSavedInfoValid: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack: []
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: F78
+ ; CHECK: RET_ReallyLR
+ RET_ReallyLR
+
+...
+---
+name: F55
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: true
+isSSA: false
+noVRegs: true
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHCatchret: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: true
+registers: []
+liveins: []
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 16
+ adjustsStack: true
+ hasCalls: true
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ isCalleeSavedInfoValid: false
+ localFrameSize: 64
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: A, type: default, offset: 0, size: 32, alignment: 16,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ local-offset: -32, debug-info-variable: '', debug-info-expression: '',
+ debug-info-location: '' }
+ - { id: 2, name: C, type: default, offset: 0, size: 32, alignment: 16,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ local-offset: -64, debug-info-variable: '', debug-info-expression: '',
+ debug-info-location: '' }
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: F55
+ ; CHECK: liveins: $x19, $lr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup EMITMTETAGGED
+ ; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 80, 0
+ ; CHECK-NEXT: frame-setup STPXi killed $lr, killed $x19, $sp, 8 :: (store (s64) into %stack.3), (store (s64) into %stack.2)
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 80
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w19, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w30, -16
+ ; CHECK-NEXT: renamable $x0 = IRGstack $sp, $xzr
+ ; CHECK-NEXT: renamable $x19 = TAGPstack $x0, 2, renamable $x0, 1
+ ; CHECK-NEXT: ST2Gi renamable $x0, renamable $x0, 0 :: (store (s256) into %ir.C.tag, align 16)
+ ; CHECK-NEXT: BL @F56, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ST2Gi renamable $x19, renamable $x19, 0 :: (store (s256) into %ir.A.tag, align 16)
+ ; CHECK-NEXT: $x0 = COPY killed renamable $x19
+ ; CHECK-NEXT: BL @F56, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: renamable $x1 = LOADgot target-flags(aarch64-got) @glob
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 32, 0
+ ; CHECK-NEXT: dead $w2 = MOVi32imm 32, implicit-def $x2
+ ; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit-def $sp, implicit-def dead $x0
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 32, 0
+ ; CHECK-NEXT: BL @F78, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ST2Gi $sp, $sp, 2 :: (store (s256) into %ir.C, align 16), (store (s256) into %ir.A, align 16)
+ ; CHECK-NEXT: ST2Gi $sp, $sp, 0 :: (store (s256) into %ir.C, align 16), (store (s256) into %ir.A, align 16)
+ ; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 64, 0
+ ; CHECK-NEXT: early-clobber $sp, $lr, $x19 = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.3), (load (s64) from %stack.2)
+ ; CHECK-NEXT: RET_ReallyLR
+ renamable $x0 = IRGstack $sp, $xzr
+ renamable $x19 = TAGPstack %stack.0.A, 0, renamable $x0, 1
+ ST2Gi renamable $x0, renamable $x0, 0 :: (store (s256) into %ir.C.tag, align 16)
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ BL @F56, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ST2Gi renamable $x19, renamable $x19, 0 :: (store (s256) into %ir.A.tag, align 16)
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ $x0 = COPY killed renamable $x19
+ BL @F56, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ST2Gi $sp, %stack.0.A, 0 :: (store (s256) into %ir.A, align 16)
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ renamable $x1 = LOADgot target-flags(aarch64-got) @glob
+ $x0 = ADDXri %stack.0.A, 0, 0
+ dead $w2 = MOVi32imm 32, implicit-def $x2
+ BL &memcpy, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit-def $sp, implicit-def dead $x0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ $x0 = ADDXri %stack.0.A, 0, 0
+ BL @F78, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ST2Gi $sp, %stack.2.C, 0 :: (store (s256) into %ir.C, align 16)
+ RET_ReallyLR
+
+...
>From 174504ca36b6b2c604d8a8bad38a97c5e9df5fe9 Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Thu, 21 Nov 2024 16:25:30 +0000
Subject: [PATCH 2/3] [AArch64] Fix STG instruction being moved past memcpy
When merging STG instructions used for AArch64 stack tagging, we were
stopping on reaching a load or store instruction, but not calls, so it
was possible for an STG to be moved past a call to memcpy.
This test case (reduced from fuzzer-generated C code) was the result of
StackColoring merging allocas A and B into one stack slot, and
StackSafetyAnalysis proving that B does not need tagging, so we end up
with tagged and untagged objects in the same stack slot. The tagged
object (A) is live first, so it is important that it's memory is
restored to the background tag before it gets reused to hold B.
---
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 2 +-
llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 216244950ba9ee..320c36b4c54cb1 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -4572,7 +4572,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
break;
// Reject anything that may alias the collected instructions.
- if (MI.mayLoadOrStore() || MI.hasUnmodeledSideEffects())
+ if (MI.mayLoadOrStore() || MI.hasUnmodeledSideEffects() || MI.isCall())
break;
}
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
index 4bfe3d17633d7b..ca6a2df0ea5029 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
@@ -203,14 +203,14 @@ body: |
; CHECK-NEXT: ST2Gi renamable $x19, renamable $x19, 0 :: (store (s256) into %ir.A.tag, align 16)
; CHECK-NEXT: $x0 = COPY killed renamable $x19
; CHECK-NEXT: BL @F56, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ST2Gi $sp, $sp, 2 :: (store (s256) into %ir.A, align 16)
; CHECK-NEXT: renamable $x1 = LOADgot target-flags(aarch64-got) @glob
; CHECK-NEXT: $x0 = ADDXri $sp, 32, 0
; CHECK-NEXT: dead $w2 = MOVi32imm 32, implicit-def $x2
; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit-def $sp, implicit-def dead $x0
; CHECK-NEXT: $x0 = ADDXri $sp, 32, 0
; CHECK-NEXT: BL @F78, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
- ; CHECK-NEXT: ST2Gi $sp, $sp, 2 :: (store (s256) into %ir.C, align 16), (store (s256) into %ir.A, align 16)
- ; CHECK-NEXT: ST2Gi $sp, $sp, 0 :: (store (s256) into %ir.C, align 16), (store (s256) into %ir.A, align 16)
+ ; CHECK-NEXT: ST2Gi $sp, $sp, 0 :: (store (s256) into %ir.C, align 16)
; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 64, 0
; CHECK-NEXT: early-clobber $sp, $lr, $x19 = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.3), (load (s64) from %stack.2)
; CHECK-NEXT: RET_ReallyLR
>From fcc25877b7a7fc0ac587b87fdecfbd5d0600cf1f Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Thu, 21 Nov 2024 16:41:21 +0000
Subject: [PATCH 3/3] Simplify test
---
.../stack-tagging-merge-past-memcpy.mir | 143 +-----------------
1 file changed, 2 insertions(+), 141 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
index ca6a2df0ea5029..45f6bfe80ac2b3 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
@@ -1,19 +1,14 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s
--- |
- source_filename = "<stdin>"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-unknown-none-elf"
@glob = global [8 x i32] zeroinitializer, align 4
- define dso_local void @F78(ptr %B) {
- entry:
- %0 = load i32, ptr %B, align 4
- ret void
- }
+ declare dso_local void @F78(ptr %B)
- define void @F55() #0 {
+ define void @F55() sanitize_memtag "target-features"="+mte,+strict-align" {
entry:
%basetag = call ptr @llvm.aarch64.irg.sp(i64 0)
%A = alloca i32, i32 8, align 16
@@ -37,140 +32,11 @@
}
declare void @F56(ptr)
-
- declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
-
- declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
-
- declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2
-
- declare void @llvm.aarch64.settag(ptr nocapture writeonly, i64) #3
-
- declare ptr @llvm.aarch64.irg.sp(i64) #4
-
- declare ptr @llvm.aarch64.tagp.p0(ptr, ptr, i64 immarg) #5
-
- declare void @llvm.aarch64.settag.zero(ptr nocapture writeonly, i64) #3
-
- declare void @llvm.aarch64.stgp(ptr nocapture writeonly, i64, i64) #3
-
- attributes #0 = { sanitize_memtag "target-features"="+mte,+strict-align" }
- attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
- attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
- attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
- attributes #4 = { nocallback nofree nosync nounwind willreturn }
- attributes #5 = { nocallback nofree nosync nounwind willreturn memory(none) }
-
-...
----
-name: F78
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-noPhis: true
-isSSA: false
-noVRegs: true
-hasFakeUses: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHCatchret: false
-hasEHScopes: false
-hasEHFunclets: false
-isOutlined: false
-debugInstrRef: false
-failsVerification: false
-tracksDebugUserValues: true
-registers: []
-liveins: []
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 0
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- isCalleeSavedInfoValid: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack: []
-stack: []
-entry_values: []
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo: {}
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: F78
- ; CHECK: RET_ReallyLR
- RET_ReallyLR
-
...
---
name: F55
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-noPhis: true
-isSSA: false
-noVRegs: true
-hasFakeUses: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHCatchret: false
-hasEHScopes: false
-hasEHFunclets: false
-isOutlined: false
-debugInstrRef: false
-failsVerification: false
-tracksDebugUserValues: true
-registers: []
-liveins: []
frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 16
adjustsStack: true
- hasCalls: true
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 0
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- isCalleeSavedInfoValid: false
- localFrameSize: 64
- savePoint: ''
- restorePoint: ''
-fixedStack: []
stack:
- { id: 0, name: A, type: default, offset: 0, size: 32, alignment: 16,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
@@ -180,11 +46,6 @@ stack:
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -64, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
-entry_values: []
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo: {}
body: |
bb.0.entry:
; CHECK-LABEL: name: F55
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