[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

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@@ -1451,6 +1451,11 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // The `llvm.experimental.vector.partial.reduce.add` intrinsic
+  // Operands: Accumulator, Input
+  // Outputs: Output
+  PARTIAL_REDUCE_ADD,
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paulwalker-arm wrote:

There's no need for this.  At the IR level we're effectively warning people that caution should be used when using the intrinsic because the design hasn't been settled on and thus we may not follow the usual norms when making changes.  At the ISD level there are no such norms beyond "nothing can break" so the extra decoration is unnecessary.

https://github.com/llvm/llvm-project/pull/117185